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ECUs provide integrated Multiply, Add, and Accumulate Functions.
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Memory - Dual Port RAM |
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Embedded Computational Units |
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High Speed Logic Cells
248K Gates
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PLL |
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Memory - Dual Port RAM |
PLL |
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tPD |
Combinatorial Delay of the longest path: time taken by the combinatorial circuit to |
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0.257 ns |
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output |
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tSU |
Setup time: time the synchronous input of the flip-flop must be stable before the |
0.22 ns |
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active clock edge |
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tHL |
Hold time: time the synchronous input of the flip-flop must be stable after the active |
0 ns |
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clock edge |
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tCO |
Clock-to-out delay: the amount of time taken by the flip-flop to output after the |
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0.255 ns |
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active clock edge. |
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tCWHI |
Clock High Time: required minimum time the clock stays high |
0.46 ns |
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tCWLO |
Clock Low Time: required minimum time that the clock stays low |
0.46 ns |
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tSET |
Set Delay: time between when the flip-flop is ”set” (high) |
- |
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0.18 ns |
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and when the output is consequently “set” (high) |
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tRESET |
Reset Delay: time between when the flip-flop is ”reset” (low) and when the output |
- |
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0.09 ns |
is consequently “reset” (low) |
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tSW |
Set Width: time that the SET signal remains high/low |
0.3 ns |
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tRW |
Reset Width: time that the RESET signal remains high/low |
0.3 ns |
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SET
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RESET
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tRESET |
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tSET |
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tRW |
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tSW |
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Logic Cells (Internal) |
Clock signal generated internally |
1.51 ns (max) |
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Clock Pad |
Clock signal generated externally |
2.06 ns (max) |
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1.73 ns (max) |
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7DEOH (FOLSVH3OXV *OREDO &ORFN 'HOD\ |
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Global clock pin delay to quad net |
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1.34 ns |
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tPGCK |
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tBGCK |
Global clock tree delay (quad net to |
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0.56 ns |
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flip-flop) |
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Global Clock Buffer
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WA |
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RCLK |
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[9:0] |
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WCLK |
RD |
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ASYNCRD |
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RAM Module |
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tSWA |
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the |
0.675 ns |
- |
active edge of the WRITE CLOCK |
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tHWA |
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active |
0 ns |
- |
edge of the WRITE CLOCK |
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tSWD |
WD setup time to WCLK: time the WRITE DATA must be stable before the active |
0.654 ns |
- |
edge of the WRITE CLOCK |
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tHWD |
WD hold time to WCLK: time the WRITE DATA must be stable after the active edge |
0 ns |
- |
of the WRITE CLOCK |
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tSWE |
WE setup time to WCLK: time the WRITE ENABLE must be stable before the active |
0.623 ns |
- |
edge of the WRITE CLOCK |
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tHWE |
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active |
0 ns |
- |
edge of the WRITE CLOCK |
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tWCRD |
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the |
- |
4.38 ns |
time when the data is available at RD |
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WA |
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WD |
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tSWA |
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tHWA |
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tSWD |
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tHWD |
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tSWE |
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tHWE |
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old data |
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new data |
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tWCRD |
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tSRA |
RA setup time to RCLK: time the READ ADDRESS must be stable before the active |
0.686 ns |
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edge of the READ CLOCK |
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tHRA |
RA hold time to RCLK: time the READ ADDRESS must be stable after the active |
0 ns |
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edge of the READ CLOCK |
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tSRE |
RE setup time to WCLK: time the READ ENABLE must be stable before the active |
0.243 ns |
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edge of the READ CLOCK |
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tHRE |
RE hold time to WCLK: time the READ ENABLE must be stable after the active |
0 ns |
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edge of the READ CLOCK |
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tRCRD |
RCLK to RD: time between the active READ CLOCK edge and the time when the |
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4.38 ns |
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data is available at RD |
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rPDRD |
RA to RD: time between when the READ ADDRESS is input and when the DATA |
- |
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2.06 ns |
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is output |
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tHRE |
RD |
old data |
new data |
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tISU |
Input register setup time: time the synchronous input of the flip-flop must be stable |
3.12 ns |
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before the active clock edge |
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tIHL |
Input register hold time: time the synchronous input of the flip-flop must be stable |
0 ns |
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after the active clock edge |
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tICO |
Input register clock-to-out: time taken by the flip-flop to output after the active clock |
- |
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1.08 ns |
edge |
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tIRST |
Input register reset delay: time between when the flip-flop is “reset” (low) and when |
- |
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0.99 ns |
the output is consequently “reset” (low) |
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tIESU |
Input register clock enable setup time: time “enable” must be stable before the |
0.37 ns |
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active clock edge |
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tIEH |
Input register clock enable hold time: time “enable” must be stable after the active |
0 ns |
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clock edge |
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tSID (LVTTL) |
LVTTL input delay: Low Voltage TTL for 3.3 V applications |
- |
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0.34 ns |
tSID (LVCMOS2) |
LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower |
- |
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0.42 ns |
applications |
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tSID (GTL+) |
GTL+ input delay: Gunning Transceiver Logic |
- |
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0.68 ns |
tSID (SSTL3) |
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V |
- |
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0.55 ns |
tSID (SSTL2) |
SSTL2 input delay: Stub Series Terminated Logic for 2.5 V |
- |
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0.61 ns |
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OUTPUT
REGISTER
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3DUDPHWHU |
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tOUTLH |
Output Delay low to high (90% of H) |
- |
0.40 ns |
tOUTHL |
Output Delay high to low (10% of L) |
- |
0.55 ns |
tPZH |
Output Delay tri-state to high (90% of H) |
- |
2.94 ns |
tPZL |
Output Delay tri-state to low (10% of L) |
- |
2.34 ns |
tPHZ |
Output Delay high to tri-State |
- |
3.07 ns |
tPLZ |
Output Delay low to tri-State |
- |
2.53 ns |
tCOP |
Clock-to-out delay (does not include clock tree delays) |
- |
3.15 ns (fast slew) |
10.2 ns (slow slew) |
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7DEOH 2XWSXW 6OHZ 5DWHV # 9&&,2 9 |
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-0.5 V to 3.6 V |
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DC Input Current |
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Delay Factor |
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D.C. Supply Current on VCCIO |
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IREF |
D.C. Supply Current on INREF |
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Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively—these functions require high logic cell usage while garnering only moderate performance results.
The QL7100 architecture allows for functionality above and beyond that achievable using programmable logic devices. By embedding a dynamically reconfigurable computational unit, the QL7100 device can address various arithmetic functions efficiently. This approach offers greater performance than traditional programmable logic implementations. The embedded block is implemented at the transistor level as shown in )LJXUH .
RESET |
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The 10 QL7100 ECU blocks are placed next to the SRAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations.
Ten 8-bit Multiply-Accumulate (MAC) functions can be implemented per cycle for a total of 1 billion MACs/s when clocked at 100 MHz. Additional MAC functions can be implemented in the programmable logic.
The modes for the ECU block are dynamically re-programmable through the programmable logic as shown in 7DEOH .
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