QUICK LOGIC QL6325-E-6PQ208C, QL6325-E-6PQ208I, QL6325-E-6PQ208M, QL6325-E-6PS484C, QL6325-E-6PS484I Datasheet

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QL6325-E Eclipse-E Data Sheet

• • • • • • FPGA Combining Performance, Density, and Embedded RAM

Device Highlights

Embedded Computational Units

Flexible Programmable Logic

12 ECUs provide integrated Multiply, Add, and Accumulate Functions.

0.18 m six layer metal CMOS Process

 

 

 

1.8/2.5/3.3 V Drive Capable I/O

 

 

 

1,536 Logic Cells

PLL

Embedded RAM Blocks

PLL

320,640 Max System Gates

 

12 Embeded Computational Units

 

 

 

 

 

Up to 310 I/O Pins

 

 

 

Embedded Dual Port SRAM

 

Fabric

 

 

Twenty-four 2,304-bit Dual Port High

 

 

 

 

 

 

Performance SRAM Blocks

 

 

 

55,300 RAM bits

 

 

 

RAM/ROM/FIFO Wizard for Automatic

PLL

Embedded RAM Blocks

PLL

 

Configuration

 

 

 

Configurable and Cascadable

 

Figure 1: QL6325-E Eclipse-E Block

 

 

 

 

 

 

Diagram

 

Programmable I/O

High performance Enhanced I/O (EIO)— less than 3 ns Tco

Programmable Slew Rate Control

Programmable I/O Standards:

LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3

Eight Independent I/O Banks

Three Register Configurations: Input, Output, and Output Enable

Advanced Clock Network

Nine Global Clock Networks:

One Dedicated

Eight Programmable

20 Quad-Net Networks—five per Quadrant

16 I/O Controls—two per I/O Bank

Four phase locked loops

© 2002 QuickLogic Corporation

Preliminary

 

www.quicklogic.com 1

QL6325-E Eclipse-E Data Sheet Rev A

Electrical Specifications

AC Characteristics*

*at VCC = 2.5 V, TA = 25° C, Worst Case Corner, Speed Grade = -7 (K = 1.16)

The AC Specifications are provided from Table 1 to Table 10. Logic Cell diagrams and waveforms are provided from Figure 2 to Figure 15.

Figure 2: Eclipse-E Logic Cell

Table 1: Logic Cells

Symbol

Parameter

Value

Logic Cells

 

Min

 

Max

 

 

 

 

 

 

 

tPD

Combinatorial Delay of the longest path: time taken by the combinatorial circuit to

-

 

0.257 ns

output

 

tSU

Setup time: time the synchronous input of the flip-flop must be stable before the

0.22 ns

 

-

active clock edge

 

tHL

Hold time: time the synchronous input of the flip-flop must be stable after the active

0 ns

 

-

clock edge

 

tCO

Clock-to-out delay: the amount of time taken by the flip-flop to output after the

-

 

0.255 ns

active clock edge.

 

tCWHI

Clock High Time: required minimum time the clock stays high

0.46 ns

 

-

tCWLO

Clock Low Time: required minimum time that the clock stays low

0.46 ns

 

-

tSET

Set Delay: time between when the flip-flop is ”set” (high)

-

 

0.18 ns

and when the output is consequently “set” (high)

 

2 www.quicklogic.com Preliminary © 2002 QuickLogic Corporation

QL6325-E Eclipse-E Data Sheet Rev A

Table 1: Logic Cells (Continued)

Symbol

Parameter

Value

Logic Cells

 

Min

 

Max

 

 

 

 

 

 

 

tRESET

Reset Delay: time between when the flip-flop is ”reset” (low) and when the output

-

 

0.09 ns

is consequently “reset” (low)

 

tSW

Set Width: time that the SET signal remains high/low

0.3 ns

 

-

tRW

Reset Width: time that the RESET signal remains high/low

0.3 ns

 

-

SET

D

Q

CLK

RESET

Figure 3: Logic Cell Flip-Flop

CLK

tCWHI (min)

 

tCWLO (min)

 

SET

RESET

Q

 

 

tRESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSET

 

 

 

tRW

 

 

 

 

 

 

tSW

 

 

 

 

 

 

 

 

 

Figure 4: Logic Cell Flip-Flop Timings—First Waveform

© 2002 QuickLogic Corporation Preliminary www.quicklogic.com 3

QUICK LOGIC QL6325-E-6PQ208C, QL6325-E-6PQ208I, QL6325-E-6PQ208M, QL6325-E-6PS484C, QL6325-E-6PS484I Datasheet

QL6325-E Eclipse-E Data Sheet Rev A

CLK

D

tSU

tHL

 

Q

tCO

Figure 5: Logic Cell Flip-Flop Timings—Second Waveform

Quad net

Figure 6: Eclipse-E Global Clock Structure

Table 2: Eclipse-E Clock Delay

Clock Source

Parameters

Clock Performance

 

 

Global

 

Dedicated

 

 

 

 

 

 

 

 

Logic Cells (Internal)

Clock signal generated internally

1.51 ns (max)

 

 

 

 

 

 

 

Clock Pad

Clock signal generated externally

2.06 ns (max)

 

1.73 ns (max)

 

 

 

 

 

4 www.quicklogic.com Preliminary © 2002 QuickLogic Corporation

QL6325-E Eclipse-E Data Sheet Rev A

Table 3: Eclipse-E Global Clock Delay

Clock Segment

Parameter

 

Value

 

 

Min

 

Max

 

 

 

 

 

 

 

 

a

Global clock pin delay to quad net

-

 

1.34 ns

tPGCK

 

tBGCK

Global clock tree delay (quad net to

-

 

0.56 ns

flip-flop)

 

a. When using a PLL, tPGCK and tBGCK are effectively zero due to delay adjustment by Phase Locked Loop.

Programmable Clock

Global Clock Buffer

External Clock

 

Global Clock

Clock

 

Select

 

tPGCK

tBGCK

Figure 7: Global Clock Structure Schematic

[9:0]

RE

WA

[17:0]

RCLK

WD

WE

[9:0]

RA

 

[17:0]

WCLK

RD

ASYNCRD

RAM Module

Figure 8: RAM Module

© 2002 QuickLogic Corporation Preliminary www.quicklogic.com 5

QL6325-E Eclipse-E Data Sheet Rev A

Table 4: RAM Cell Synchronous Write Timing

Symbol

Parameter

Value

 

 

 

 

RAM Cell Synchronous Write Timing

Min

Max

 

 

 

 

tSWA

WA setup time to WCLK: time the WRITE ADDRESS must be stable before the

0.675 ns

-

active edge of the WRITE CLOCK

tHWA

WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active

0 ns

-

edge of the WRITE CLOCK

tSWD

WD setup time to WCLK: time the WRITE DATA must be stable before the active

0.654 ns

-

edge of the WRITE CLOCK

tHWD

WD hold time to WCLK: time the WRITE DATA must be stable after the active edge

0 ns

-

of the WRITE CLOCK

tSWE

WE setup time to WCLK: time the WRITE ENABLE must be stable before the active

0.623 ns

-

edge of the WRITE CLOCK

tHWE

WE hold time to WCLK: time the WRITE ENABLE must be stable after the active

0 ns

-

edge of the WRITE CLOCK

tWCRD

WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the

-

4.38 ns

time when the data is available at RD

WCLK

WA

tSWA tHWA

WD

tSWD tHWD

WE

tSWE tHWE

RD

old data

new data

tWCRD

Figure 9: RAM Cell Synchronous Write Timing

6 www.quicklogic.com Preliminary © 2002 QuickLogic Corporation

QL6325-E Eclipse-E Data Sheet Rev A

 

Table 5: RAM Cell Synchronous & Asynchronous Read Timing

 

 

 

 

 

 

 

Symbol

RAM Cell Synchronous Read Timing

Value

Parameter

Min

 

Max

 

 

 

 

 

 

 

 

tSRA

RA setup time to RCLK: time the READ ADDRESS must be stable before the active

0.686 ns

 

-

edge of the READ CLOCK

 

tHRA

RA hold time to RCLK: time the READ ADDRESS must be stable after the active

0 ns

 

-

edge of the READ CLOCK

 

tSRE

RE setup time to WCLK: time the READ ENABLE must be stable before the active

0.243 ns

 

-

edge of the READ CLOCK

 

tHRE

RE hold time to WCLK: time the READ ENABLE must be stable after the active

0 ns

 

-

edge of the READ CLOCK

 

tRCRD

RCLK to RD: time between the active READ CLOCK edge and the time when the

-

 

4.38 ns

data is available at RD

 

 

RAM Cell Asynchronous Read Timing

 

 

 

 

 

 

 

 

rPDRD

RA to RD: time between when the READ ADDRESS is input and when the DATA

-

 

2.06 ns

is output

 

RCLK

RA

 

 

 

tSRA

tHRA

RE

 

 

 

tSRE

tHRE

RD

old data

new data

tRCRD

rPDRD

Figure 10: RAM Cell Synchronous & Asynchronous Read Timing

© 2002 QuickLogic Corporation Preliminary www.quicklogic.com 7

QL6325-E Eclipse-E Data Sheet Rev A

 

+

 

-

INPUT

Q E

REGISTER

D

 

R

 

PAD

OUTPUT

Q

D

REGISTER

R

 

OUTPUT ENABLE

E Q

D

REGISTER

R

 

Figure 11: Eclipse-E Cell I/O

tISU

+

-

tSID

Q E

D

R

PAD

Figure 12: Eclipse-E Input Register Cell

8 www.quicklogic.com Preliminary © 2002 QuickLogic Corporation

QL6325-E Eclipse-E Data Sheet Rev A

Table 6: Input Register Cell

Symbol

Parameter: Input Register Cell Only

Value

Min

 

Max

 

 

 

 

 

 

 

 

 

tISU

Input register setup time: the time the synchronous input of the flip-flop must be

2.50 ns

 

-

stable before the active clock edge

 

tIHL

Input register hold time: the time the synchronous input of the flip-flop must be

0 ns

 

-

stable after the active clock edge

 

tICO

Input register clock-to-out: the time taken by the flip-flop to output after the active

-

 

1.08 ns

clock edge

 

tIRST

Input register reset delay: the time between when the flip-flop is “reset”(low) and

-

 

0.99 ns

when the output is consequently “reset” (low)

 

tIESU

Input register clock enable setup time: the time “enable” must be stable before the

0.37 ns

 

-

active clock edge

 

tIEH

Input register clock enable hold time: the time “enable” must be stable after the

0 ns

 

-

active clock edge

 

Table 7: Standard Input Delays

Symbol

Parameter

Value

Standard Input Delays

To get the total input delay add this delay to tISU

Min

 

Max

 

 

 

 

 

 

tSID (LVTTL)

LVTTL input delay: Low Voltage TTL for 3.3 V applications

-

 

0.34 ns

tSID (LVCMOS2)

LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower

-

 

0.42 ns

applications

 

 

 

 

 

 

tSID (LVCMOS18)

LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications

-

 

-

tSID (GTL+)

GTL+ input delay: Gunning Transceiver Logic

-

 

0.68 ns

tSID (SSTL3)

SSTL3 input delay: Stub Series Terminated Logic for 3.3 V

-

 

0.55 ns

tSID (SSTL2)

SSTL2 input delay: Stub Series Terminated Logic for 2.5 V

-

 

0.61 ns

© 2002 QuickLogic Corporation Preliminary www.quicklogic.com 9

QL6325-E Eclipse-E Data Sheet Rev A

R

CLK

D

tISU tIHL

Q

tICO

tIRST

E

tIESU tIEH

Figure 13: Eclipse-E Input Register Cell Timing

PAD

OUTPUT

REGISTER

Figure 14: Eclipse-E Output Register Cell

10 www.quicklogic.com Preliminary © 2002 QuickLogic Corporation

QL6325-E Eclipse-E Data Sheet Rev A

Table 8: Eclipse-E Output Register Cell

 

Symbol

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Register Cell Only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min

 

 

 

 

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOUTLH

Output Delay low to high (90% of H)

 

 

 

 

 

 

 

-

 

 

 

 

 

 

0.40 ns

 

 

tOUTHL

Output Delay high to low (10% of L)

 

 

 

 

 

 

 

-

 

 

 

 

 

 

0.55 ns

 

 

tPZH

Output Delay tri-state to high (90% of H)

 

 

 

 

 

 

 

-

 

 

 

 

 

 

2.94 ns

 

 

tPZL

Output Delay tri-state to low (10% of L)

 

 

 

 

 

 

 

-

 

 

 

 

 

 

2.34 ns

 

 

tPHZ

Output Delay high to tri-State

 

 

 

 

 

 

 

-

 

 

 

 

 

 

3.07 ns

 

 

tPLZ

Output Delay low to tri-State

 

 

 

 

 

 

 

-

 

 

 

 

 

 

2.53 ns

 

 

tCOP

Clock-to-out delay (does not include clock tree delays)

 

 

 

 

 

-

 

 

 

 

 

 

3.15 ns (fast slew)

 

 

 

 

 

 

 

 

 

 

 

 

 

10.2 ns (slow slew)

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOUTHL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOUTLH

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

H

 

 

 

 

 

 

 

tPZL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPZH

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

tPHZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

Z

 

 

 

 

 

 

 

 

 

 

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPLZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 15: Eclipse-E Output Register Cell Timing

 

 

 

 

 

 

 

 

Table 9: Output Slew Rates @ VCCIO = 3.3 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fast Slew

 

 

 

 

 

 

 

 

 

 

Slow Slew

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rising Edge

 

 

 

 

 

 

 

 

 

 

 

2.8 V/ns

 

 

 

 

 

 

 

 

 

 

 

1.0 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Falling Edge

 

 

 

 

 

 

 

 

 

 

 

2.86 V/ns

 

 

 

 

 

 

 

 

 

 

 

1.0 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 10: Output Slew Rates @ VCCIO = 2.5 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fast Slew

 

 

 

 

 

 

 

 

 

 

Slow Slew

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rising Edge

 

 

 

 

 

 

 

 

 

 

 

1.7 V/ns

 

 

 

 

 

 

 

 

 

 

 

0.6 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Falling Edge

 

 

 

 

 

 

 

 

 

 

 

1.9 V/ns

 

 

 

 

 

 

 

 

 

 

 

0.6 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

© 2002 QuickLogic Corporation Preliminary www.quicklogic.com 11

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