QL6325-E Eclipse-E Data Sheet
• • • • • • FPGA Combining Performance, Density, and Embedded RAM
Device Highlights |
Embedded Computational Units |
Flexible Programmable Logic
12 ECUs provide integrated Multiply, Add, and Accumulate Functions.
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0.18 m six layer metal CMOS Process |
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• 1.8/2.5/3.3 V Drive Capable I/O |
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1,536 Logic Cells |
PLL |
Embedded RAM Blocks |
PLL |
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320,640 Max System Gates |
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12 Embeded Computational Units |
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Up to 310 I/O Pins |
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Embedded Dual Port SRAM |
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Fabric |
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Twenty-four 2,304-bit Dual Port High |
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Performance SRAM Blocks |
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55,300 RAM bits |
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RAM/ROM/FIFO Wizard for Automatic |
PLL |
Embedded RAM Blocks |
PLL |
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Configuration |
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Configurable and Cascadable |
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Figure 1: QL6325-E Eclipse-E Block |
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Diagram |
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Programmable I/O
•High performance Enhanced I/O (EIO)— less than 3 ns Tco
•Programmable Slew Rate Control
•Programmable I/O Standards:
•LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3
•Eight Independent I/O Banks
•Three Register Configurations: Input, Output, and Output Enable
Advanced Clock Network
•Nine Global Clock Networks:
•One Dedicated
•Eight Programmable
•20 Quad-Net Networks—five per Quadrant
•16 I/O Controls—two per I/O Bank
•Four phase locked loops
© 2002 QuickLogic Corporation |
Preliminary |
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www.quicklogic.com •• 1
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QL6325-E Eclipse-E Data Sheet Rev A
Electrical Specifications
AC Characteristics*
*at VCC = 2.5 V, TA = 25° C, Worst Case Corner, Speed Grade = -7 (K = 1.16)
The AC Specifications are provided from Table 1 to Table 10. Logic Cell diagrams and waveforms are provided from Figure 2 to Figure 15.
Figure 2: Eclipse-E Logic Cell
Table 1: Logic Cells
Symbol |
Parameter |
Value |
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Logic Cells |
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Min |
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Max |
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tPD |
Combinatorial Delay of the longest path: time taken by the combinatorial circuit to |
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0.257 ns |
output |
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tSU |
Setup time: time the synchronous input of the flip-flop must be stable before the |
0.22 ns |
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active clock edge |
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tHL |
Hold time: time the synchronous input of the flip-flop must be stable after the active |
0 ns |
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clock edge |
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tCO |
Clock-to-out delay: the amount of time taken by the flip-flop to output after the |
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0.255 ns |
active clock edge. |
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tCWHI |
Clock High Time: required minimum time the clock stays high |
0.46 ns |
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tCWLO |
Clock Low Time: required minimum time that the clock stays low |
0.46 ns |
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tSET |
Set Delay: time between when the flip-flop is ”set” (high) |
- |
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0.18 ns |
and when the output is consequently “set” (high) |
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2 •• www.quicklogic.com Preliminary © 2002 QuickLogic Corporation
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QL6325-E Eclipse-E Data Sheet Rev A
Table 1: Logic Cells (Continued)
Symbol |
Parameter |
Value |
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Logic Cells |
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Min |
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Max |
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tRESET |
Reset Delay: time between when the flip-flop is ”reset” (low) and when the output |
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0.09 ns |
is consequently “reset” (low) |
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tSW |
Set Width: time that the SET signal remains high/low |
0.3 ns |
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tRW |
Reset Width: time that the RESET signal remains high/low |
0.3 ns |
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SET
D
Q
CLK
RESET
Figure 3: Logic Cell Flip-Flop
CLK
tCWHI (min) |
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tCWLO (min) |
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SET
RESET
Q
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tRESET |
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tSET |
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tRW |
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tSW |
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Figure 4: Logic Cell Flip-Flop Timings—First Waveform
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© 2002 QuickLogic Corporation Preliminary www.quicklogic.com •• 3
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QL6325-E Eclipse-E Data Sheet Rev A
CLK
D |
tSU |
tHL |
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Q
tCO
Figure 5: Logic Cell Flip-Flop Timings—Second Waveform
Quad net
Figure 6: Eclipse-E Global Clock Structure
Table 2: Eclipse-E Clock Delay
Clock Source |
Parameters |
Clock Performance |
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Global |
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Dedicated |
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Logic Cells (Internal) |
Clock signal generated internally |
1.51 ns (max) |
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Clock Pad |
Clock signal generated externally |
2.06 ns (max) |
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1.73 ns (max) |
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4 •• www.quicklogic.com Preliminary © 2002 QuickLogic Corporation
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QL6325-E Eclipse-E Data Sheet Rev A
Table 3: Eclipse-E Global Clock Delay
Clock Segment |
Parameter |
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Value |
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Min |
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Max |
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a |
Global clock pin delay to quad net |
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1.34 ns |
tPGCK |
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tBGCK |
Global clock tree delay (quad net to |
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0.56 ns |
flip-flop) |
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a. When using a PLL, tPGCK and tBGCK are effectively zero due to delay adjustment by Phase Locked Loop.
Programmable Clock |
Global Clock Buffer |
External Clock
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Global Clock |
Clock |
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Select |
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tPGCK |
tBGCK |
Figure 7: Global Clock Structure Schematic |
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[9:0] |
RE |
WA |
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[17:0] |
RCLK |
WD |
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WE |
[9:0] |
RA |
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[17:0] |
WCLK |
RD |
ASYNCRD |
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RAM Module |
Figure 8: RAM Module
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© 2002 QuickLogic Corporation Preliminary www.quicklogic.com •• 5
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QL6325-E Eclipse-E Data Sheet Rev A
Table 4: RAM Cell Synchronous Write Timing
Symbol |
Parameter |
Value |
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RAM Cell Synchronous Write Timing |
Min |
Max |
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tSWA |
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the |
0.675 ns |
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active edge of the WRITE CLOCK |
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tHWA |
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active |
0 ns |
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edge of the WRITE CLOCK |
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tSWD |
WD setup time to WCLK: time the WRITE DATA must be stable before the active |
0.654 ns |
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edge of the WRITE CLOCK |
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tHWD |
WD hold time to WCLK: time the WRITE DATA must be stable after the active edge |
0 ns |
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of the WRITE CLOCK |
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tSWE |
WE setup time to WCLK: time the WRITE ENABLE must be stable before the active |
0.623 ns |
- |
edge of the WRITE CLOCK |
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tHWE |
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active |
0 ns |
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edge of the WRITE CLOCK |
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tWCRD |
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the |
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4.38 ns |
time when the data is available at RD |
WCLK
WA
tSWA tHWA
WD
tSWD tHWD
WE
tSWE tHWE
RD |
old data |
new data |
tWCRD
Figure 9: RAM Cell Synchronous Write Timing
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6 •• www.quicklogic.com Preliminary © 2002 QuickLogic Corporation
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QL6325-E Eclipse-E Data Sheet Rev A
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Table 5: RAM Cell Synchronous & Asynchronous Read Timing |
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RAM Cell Synchronous Read Timing |
Value |
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Min |
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Max |
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tSRA |
RA setup time to RCLK: time the READ ADDRESS must be stable before the active |
0.686 ns |
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edge of the READ CLOCK |
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tHRA |
RA hold time to RCLK: time the READ ADDRESS must be stable after the active |
0 ns |
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edge of the READ CLOCK |
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tSRE |
RE setup time to WCLK: time the READ ENABLE must be stable before the active |
0.243 ns |
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edge of the READ CLOCK |
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tHRE |
RE hold time to WCLK: time the READ ENABLE must be stable after the active |
0 ns |
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edge of the READ CLOCK |
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tRCRD |
RCLK to RD: time between the active READ CLOCK edge and the time when the |
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4.38 ns |
data is available at RD |
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RAM Cell Asynchronous Read Timing |
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rPDRD |
RA to RD: time between when the READ ADDRESS is input and when the DATA |
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2.06 ns |
is output |
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RCLK
RA |
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tSRA |
tHRA |
RE |
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tSRE |
tHRE |
RD |
old data |
new data |
tRCRD
rPDRD
Figure 10: RAM Cell Synchronous & Asynchronous Read Timing
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© 2002 QuickLogic Corporation Preliminary www.quicklogic.com •• 7
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QL6325-E Eclipse-E Data Sheet Rev A
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INPUT |
Q E |
REGISTER |
D |
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PAD |
OUTPUT |
Q |
D |
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REGISTER |
R |
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OUTPUT ENABLE |
E Q |
D |
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REGISTER |
R |
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Figure 11: Eclipse-E Cell I/O
tISU
+
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tSID
Q E
D
R
PAD
Figure 12: Eclipse-E Input Register Cell
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8 •• www.quicklogic.com Preliminary © 2002 QuickLogic Corporation
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QL6325-E Eclipse-E Data Sheet Rev A
Table 6: Input Register Cell
Symbol |
Parameter: Input Register Cell Only |
Value |
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Min |
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Max |
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tISU |
Input register setup time: the time the synchronous input of the flip-flop must be |
2.50 ns |
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stable before the active clock edge |
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tIHL |
Input register hold time: the time the synchronous input of the flip-flop must be |
0 ns |
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stable after the active clock edge |
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tICO |
Input register clock-to-out: the time taken by the flip-flop to output after the active |
- |
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1.08 ns |
clock edge |
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tIRST |
Input register reset delay: the time between when the flip-flop is “reset”(low) and |
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0.99 ns |
when the output is consequently “reset” (low) |
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tIESU |
Input register clock enable setup time: the time “enable” must be stable before the |
0.37 ns |
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active clock edge |
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tIEH |
Input register clock enable hold time: the time “enable” must be stable after the |
0 ns |
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active clock edge |
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Table 7: Standard Input Delays
Symbol |
Parameter |
Value |
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Standard Input Delays |
To get the total input delay add this delay to tISU |
Min |
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Max |
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tSID (LVTTL) |
LVTTL input delay: Low Voltage TTL for 3.3 V applications |
- |
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0.34 ns |
tSID (LVCMOS2) |
LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower |
- |
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0.42 ns |
applications |
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tSID (LVCMOS18) |
LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications |
- |
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tSID (GTL+) |
GTL+ input delay: Gunning Transceiver Logic |
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0.68 ns |
tSID (SSTL3) |
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V |
- |
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0.55 ns |
tSID (SSTL2) |
SSTL2 input delay: Stub Series Terminated Logic for 2.5 V |
- |
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0.61 ns |
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© 2002 QuickLogic Corporation Preliminary www.quicklogic.com •• 9
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QL6325-E Eclipse-E Data Sheet Rev A
R
CLK
D
tISU tIHL
Q |
tICO |
tIRST
E
tIESU tIEH
Figure 13: Eclipse-E Input Register Cell Timing
PAD
OUTPUT
REGISTER
Figure 14: Eclipse-E Output Register Cell
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10 •• www.quicklogic.com Preliminary © 2002 QuickLogic Corporation
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QL6325-E Eclipse-E Data Sheet Rev A
Table 8: Eclipse-E Output Register Cell
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Parameter |
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Value |
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Output Register Cell Only |
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Min |
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Max |
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tOUTLH |
Output Delay low to high (90% of H) |
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- |
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0.40 ns |
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tOUTHL |
Output Delay high to low (10% of L) |
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0.55 ns |
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tPZH |
Output Delay tri-state to high (90% of H) |
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2.94 ns |
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tPZL |
Output Delay tri-state to low (10% of L) |
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2.34 ns |
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tPHZ |
Output Delay high to tri-State |
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3.07 ns |
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tPLZ |
Output Delay low to tri-State |
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2.53 ns |
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tCOP |
Clock-to-out delay (does not include clock tree delays) |
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- |
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3.15 ns (fast slew) |
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10.2 ns (slow slew) |
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H |
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tOUTHL |
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H |
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tOUTLH |
L |
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tPZL |
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Z |
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tPZH |
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tPHZ |
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tPLZ |
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Figure 15: Eclipse-E Output Register Cell Timing |
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Table 9: Output Slew Rates @ VCCIO = 3.3 V |
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Fast Slew |
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Slow Slew |
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Rising Edge |
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2.8 V/ns |
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1.0 V/ns |
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Falling Edge |
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2.86 V/ns |
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1.0 V/ns |
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Table 10: Output Slew Rates @ VCCIO = 2.5 V |
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Fast Slew |
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Slow Slew |
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Rising Edge |
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1.7 V/ns |
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0.6 V/ns |
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Falling Edge |
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1.9 V/ns |
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0.6 V/ns |
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•
© 2002 QuickLogic Corporation Preliminary www.quicklogic.com •• 11
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