QUICK LOGIC QL6250-5PT208C, QL6250-5PT208I, QL6250-5PT208M, QL6250-5PT280C, QL6250-5PT280I Datasheet

...
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4/ (FOLSVH 'DWD 6KHHW

W W W W W W &RPELQLQJ 3HUIRUPDQFH 'HQVLW\ DQG (PEHGGHG 5$0

'HYLFH +LJKOLJKWV

)OH[LEOH 3URJUDPPDEOH /RJLF

.25 m, Five layer metal CMOS Process

2.5 V VCC, 2.5/3.3 V Drive Capable I/O

960 Logic Cells

248,160 Max System Gates

Up to 250 I/O Pins

(PEHGGHG 'XDO 3RUW 65$0

Twenty 2,304-bit Dual Port High Performance SRAM Blocks

46,100 RAM Bits

RAM/ROM/FIFO Wizard for Automatic Configuration

Configurable and Cascadable

3URJUDPPDEOH , 2

$GYDQFHG &ORFN 1HWZRUN

Nine Global Clock Networks:

One Dedicated

Eight Programmable

20 Quad-Net Networks: Five per Quadrant

16 I/O Controls: Two per I/O Bank

Memory - Dual Port RAM

High Speed Logic Cells

248K Gates

Memory - Dual Port RAM

)LJXUH (FOLSVH %ORFN 'LDJUDP

High performance Enhanced I/O (EIO): Less than 3 ns Tco

Programmable Slew Rate Control

Programmable I/O Standards:

LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3

Eight Independent I/O Banks

Three Register Configurations: Input, Output, and Output Enable

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4/ (FOLSVH 'DWD 6KHHW 5HY %

(OHFWULFDO 6SHFLILFDWLRQV

$& &KDUDFWHULVWLFV DW 9&& 9 7$ ƒ& .

The AC Specifications are provided from 7DEOH to 7DEOH . Logic Cell diagrams and waveforms are provided from to )LJXUH .

)LJXUH (FOLSVH /RJLF &HOO

7DEOH /RJLF &HOOV

6\PERO

3DUDPHWHU

9DOXH QV

/RJLF &HOOV

 

0LQ

 

0D[

 

 

 

 

 

 

 

tPD

Combinatorial Delay of the longest path: time taken by the combinatorial circuit to

-

 

0.257

output

 

tSU

Setup time: time the synchronous input of the flip flop must be stable before the

0.22

 

-

active clock edge

 

tHL

Hold time: time the synchronous input of the flip flop must be stable after the active

0

 

-

clock edge

 

tCO

Clock to out delay: the amount of time taken by the flip flop to output after the

-

 

0.255

active clock edge.

 

tCWHI

Clock High Time: required minimum time the clock stays high

0.46

 

-

tCWLO

Clock Low Time: required minimum time that the clock stays low

0.46

 

-

tSET

Set Delay: time between when the flip flop is ”set” (high)

-

 

0.18

and when the output is consequently “set” (high)

 

tRESET

Reset Delay: time between when the flip flop is ”reset” (low) and when the output

-

 

0.09

is consequently “reset” (low)

 

tSW

Set Width: time that the SET signal remains high/low

0.3

 

-

tRW

Reset Width: time that the RESET signal remains high/low

0.3

 

-

 

W

 

 

 

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‹ 4XLFN/RJLF &RUSRUDWLRQ

 

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W

 

 

 

 

 

 

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W

 

 

4/ (FOLSVH 'DWD 6KHHW 5HY %

SET

D

Q

CLK

RESET

)LJXUH /RJLF &HOO )OLS )ORS

CLK

tCWHI (min)

 

tCWLO (min)

 

SET

RESET

Q

CLK

D

Q

 

 

tRESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSET

 

 

 

 

tRW

 

 

 

 

 

tSW

 

 

 

 

 

 

 

 

 

 

 

 

)LJXUH /RJLF &HOO )OLS )ORS 7LPLQJV )LUVW :DYHIRUP

tSU tHL

tCO

)LJXUH /RJLF &HOO )OLS )ORS 7LPLQJV 6HFRQG :DYHIRUP

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QUICK LOGIC QL6250-5PT208C, QL6250-5PT208I, QL6250-5PT208M, QL6250-5PT280C, QL6250-5PT280I Datasheet

4/ (FOLSVH 'DWD 6KHHW 5HY %

Quad net

)LJXUH (FOLSVH *OREDO &ORFN 6WUXFWXUH

7DEOH (FOLSVH &ORFN 3HUIRUPDQFH

&ORFN

3DUDPHWHUV

&ORFN 3HUIRUPDQFH

 

 

*OREDO

 

'HGLFDWHG

 

 

 

 

 

 

 

 

 

Logic Cells (Internal)

Clock signal generated internally

1.51 ns (max)

 

1.59 ns (max)

 

 

 

 

 

 

I/O’s (External)

Clock signal generated externally

2.06 ns (max)

 

1.73 ns (max)

 

 

 

 

 

 

 

7DEOH (FOLSVH *OREDO &ORFN 3HUIRUPDQFH

 

 

 

 

 

 

 

 

&ORFN 6HJPHQW

3DUDPHWHU

9DOXH QV

 

 

0LQ

 

 

0D[

 

 

 

 

 

 

 

 

 

 

tPGCK

Global clock pin delay to quad net

-

 

1.34

tBGCK

Global clock buffer delay

-

 

0.56

(quad net to flip flop)

 

Programmable Clock

External Clock

tPGCK

Global Clock Buffer

Global Clock

Clock

Select

tBGCK

)LJXUH *OREDO &ORFN 6WUXFWXUH 6FKHPDWLF

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W

W

4/ (FOLSVH 'DWD 6KHHW 5HY %

[9:0]

RE

WA

[17:0]

RCLK

WD

WE

[9:0]

RA

 

[17:0]

WCLK

RD

 

ASYNCRD

RAM Module

)LJXUH 5$0 0RGXOH

7DEOH 5$0 &HOO 6\QFKURQRXV :ULWH 7LPLQJ

6\PERO

3DUDPHWHU

9DOXH QV

 

 

 

 

5$0 &HOO 6\QFKURQRXV :ULWH 7LPLQJ

0LQ

0D[

 

 

 

 

tSWA

WA setup time to WCLK: time the WRITE ADDRESS must be stable before the

0.675

-

active edge of the WRITE CLOCK

tHWA

WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active

0

-

edge of the WRITE CLOCK

tSWD

WD setup time to WCLK: time the WRITE DATA must be stable before the active

0.654

-

edge of the WRITE CLOCK

tHWD

WD hold time to WCLK: time the WRITE DATA must be stable after the active edge

0

-

of the WRITE CLOCK

tSWE

WE setup time to WCLK: time the WRITE ENABLE must be stable before the active

0.623

-

edge of the WRITE CLOCK

tHWE

WE hold time to WCLK: time the WRITE ENABLE must be stable after the active

0

-

edge of the WRITE CLOCK

tWCRD

WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the

-

4.38

time when the data is available at RD

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W

4/ (FOLSVH 'DWD 6KHHW 5HY %

 

WCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSWA

 

 

 

 

 

tHWA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSWD

 

 

 

tHWD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSWE

 

 

 

tHWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RD

 

old data

 

 

 

 

new data

 

 

 

 

 

 

 

 

 

 

 

 

tWCRD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

)LJXUH 5$0 &HOO 6\QFKURQRXV :ULWH 7LPLQJ

 

 

 

7DEOH 5$0 &HOO 6\QFKURQRXV $V\QFKURQRXV 5HDG 7LPLQJ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6\PERO

 

 

 

3DUDPHWHU

 

 

 

 

 

9DOXH QV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5$0 &HOO 6\QFKURQRXV 5HDG 7LPLQJ

 

 

 

 

 

 

 

 

 

 

 

0LQ

0D[

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSRA

RA setup time to RCLK: time the READ ADDRESS must be stable before the active

0.686

-

edge of the READ CLOCK

 

 

 

 

 

 

 

 

 

 

 

tHRA

RA hold time to RCLK: time the READ ADDRESS must be stable after the active

0

-

edge of the READ CLOCK

 

 

 

 

 

 

 

 

 

 

 

tSRE

RE setup time to WCLK: time the READ ENABLE must be stable before the active

0.243

-

edge of the READ CLOCK

 

 

 

 

 

 

 

 

 

 

 

tHRE

RE hold time to WCLK: time the READ ENABLE must be stable after the active

0

-

edge of the READ CLOCK

 

 

 

 

 

 

 

 

 

 

 

tRCRD

RCLK to RD: time between the active READ CLOCK edge and the time when the

-

4.38

data is available at RD

 

 

 

 

 

 

 

 

 

 

 

5$0 &HOO $V\QFKURQRXV 5HDG 7LPLQJ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rPDRD

RA to RD: time between when the READ ADDRESS is input and when the DATA

-

2.06

is output

 

 

 

 

 

 

 

 

 

 

 

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W

W

4/ (FOLSVH 'DWD 6KHHW 5HY %

RCLK

RA

 

tSRA

tHRA

RE

 

 

 

tSRE

tHRE

RD

old data

new data

tRCRD

rPDRD

)LJXUH 5$0 &HOO 6\QFKURQRXV $V\QFKURQRXV 5HDG 7LPLQJ

INPUT

Q E

REGISTER

D

 

R

OUTPUT

Q

D

 

REGISTER

 

 

R

OUTPUT ENABLE

E Q

D

REGISTER

 

 

R

+

-

PAD

)LJXUH (FOLSVH &HOO , 2

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4/ (FOLSVH 'DWD 6KHHW 5HY %

 

tICLK

tIN, tINI

t

 

ISU

+

-

tSID

Q E

D

R

PAD

)LJXUH (FOLSVH ,QSXW 5HJLVWHU &HOO

7DEOH ,QSXW 5HJLVWHU &HOO

6\PERO

3DUDPHWHU

9DOXH QV

 

 

 

 

,QSXW 5HJLVWHU &HOO 2QO\

0LQ

0D[

 

 

 

 

tISU

Input register setup time: time the synchronous input of the flip flop must be stable

3.12

-

before the active clock edge

tIHL

Input register hold time: time the synchronous input of the flip flop must be stable

0

-

after the active clock edge

tICO

Input register clock to out: time taken by the flip flop to output after the active clock

-

1.08

edge

tIRST

Input register reset delay: time between when the flip flop is “reset” (low) and when

-

0.99

the output is consequently “reset” (low)

tIESU

Input register clock enable setup time: time “enable” must be stable before the

0.37

-

active clock edge

tIEH

Input register clock enable hold time: time “enable” must be stable after the active

0

-

clock edge

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W

W

W

4/ (FOLSVH 'DWD 6KHHW 5HY %

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

CLK

 

 

 

 

D

 

 

 

 

tISU

tIHL

 

 

 

Q

tICO

 

 

 

E

tIEH

 

 

 

tIESU

 

 

 

7DEOH 6WDQGDUG ,QSXW 'HOD\V

 

 

6\PERO

 

3DUDPHWHU

9DOXH QV

6WDQGDUG ,QSXW 'HOD\V

7R JHW WKH WRWDO LQSXW GHOD\ DGG WKLV GHOD\ WR W,68

0LQ

0D[

tSID (LVTTL)

LVTTL input delay: Low Voltage TTL for 3.3 V applications

-

0.34

tSID (LVCMOS2)

LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower

-

0.42

applications

 

tSID (GTL+)

GTL+ input delay: Gunning Transceiver Logic

-

0.68

tSID (SSTL3)

SSTL3 input delay: Stub Series Terminated Logic for 3.3 V

-

0.55

tSID (SSTL2)

SSTL2 input delay: Stub Series Terminated Logic for 2.5 V

-

0.61

tIRST

)LJXUH (FOLSVH ,QSXW 5HJLVWHU &HOO 7LPLQJ

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W

W

4/ (FOLSVH 'DWD 6KHHW 5HY %

PAD

OUTPUT

REGISTER

)LJXUH (FOLSVH 2XWSXW 5HJLVWHU &HOO

7DEOH (FOLSVH 2XWSXW 5HJLVWHU &HOO

6\PERO

3DUDPHWHU

 

9DOXH QV

 

 

 

 

 

2XWSXW 5HJLVWHU &HOO 2QO\

0LQ

 

0D[

 

 

 

 

 

tOUTLH

Output Delay low to high (90% of H)

-

 

0.40

tOUTHL

Output Delay high to low (10% of L)

-

 

0.55

tPZH

Output Delay tri-state to high (90% of H)

-

 

2.94

tPZL

Output Delay tri-state to low (10% of L)

-

 

2.34

tPHZ

Output Delay high to tri-State

-

 

3.07

tPLZ

Output Delay low to tri-State

-

 

2.53

tCOP

Clock-to-out delay (does not include clock tree delays)

-

 

3.15 (fast slew)

 

10.2 (slow slew)

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W

W

W

4/ (FOLSVH 'DWD 6KHHW 5HY %

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOUTHL

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOUTLH

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPZL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPZH

Z

L

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

tPHZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

tPLZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

)LJXUH (FOLSVH 2XWSXW 5HJLVWHU &HOO 7LPLQJ

 

 

 

 

7DEOH 2XWSXW 6OHZ 5DWHV # 9&&,2 9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

)DVW 6OHZ

 

 

 

 

 

 

 

 

 

 

6ORZ 6OHZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rising Edge

 

 

 

 

 

 

 

 

 

 

2.8 V/ns

 

 

 

 

 

 

 

 

 

 

 

1.0 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Falling Edge

 

 

 

 

 

 

 

 

 

 

2.86 V/ns

 

 

 

 

 

 

 

 

 

 

 

1.0 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7DEOH 2XWSXW 6OHZ 5DWHV # 9&&,2 9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

)DVW 6OHZ

 

 

 

 

 

 

 

 

 

 

6ORZ 6OHZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rising Edge

 

 

 

 

 

 

 

 

 

 

1.7 V/ns

 

 

 

 

 

 

 

 

 

 

 

0.6 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Falling Edge

 

 

 

 

 

 

 

 

 

 

1.9 V/ns

 

 

 

 

 

 

 

 

 

 

 

0.6 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

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4/ (FOLSVH 'DWD 6KHHW 5HY %

'& &KDUDFWHULVWLFV

The DC Specifications are provided in 7DEOH through 7DEOH .

7DEOH $EVROXWH 0D[LPXP 5DWLQJV

 

3DUDPHWHU

 

 

9DOXH

 

 

 

 

3DUDPHWHU

 

 

 

 

9DOXH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9&& 9ROWDJH

 

 

-0.5 V to 3.6 V

 

 

 

'& ,QSXW &XUUHQW

 

 

±20 mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9&&,2 9ROWDJH

 

 

-0.5 V to 4.6 V

 

 

 

(6' 3DG 3URWHFWLRQ

 

 

±2000 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

,15() 9ROWDJH

 

 

2.7 V

 

 

 

/HDGHG 3DFNDJH

-65° C to + 150° C

 

 

 

 

 

 

6WRUDJH 7HPSHUDWXUH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

,QSXW 9ROWDJH

 

-0.5 V to VCCIO +0.5 V

 

 

/DPLQDWH 3DFNDJH %*$

-55° C to + 125° C

 

/DWFK XS ,PPXQLW\

 

 

±100 mA

 

 

 

6WRUDJH 7HPSHUDWXUH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7DEOH 2SHUDWLQJ 5DQJH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6\PERO

 

3DUDPHWHU

0LOLWDU\

 

,QGXVWULDO

 

&RPPHUFLDO

8QLW

 

 

 

 

 

 

 

0LQ

 

0D[

 

0LQ

 

0D[

 

0LQ

 

0D[

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

Supply Voltage

2.3

 

2.7

 

2.3

 

2.7

 

2.3

 

2.7

V

 

VCCIO

I/O Input Tolerance Voltage

2.3

 

3.6

 

2.3

 

3.6

 

2.3

 

3.6

V

 

 

TA

Ambient Temperature

-55

 

 

 

-40

 

85

 

0

 

70

°C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TC

Case Temperature

-

 

 

125

 

-

 

-

 

-

 

-

°C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-4 Speed Grade

0.42

 

2.3

 

0.43

 

2.16

 

0.47

 

2.11

n/a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

Delay Factor

-5 Speed Grade

0.42

 

1.92

 

0.43

 

1.80

 

0.46

 

1.76

n/a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-6 Speed Grade

0.42

 

1.35

 

0.43

 

1.26

 

0.46

 

1.23

n/a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-7 Speed Grade

0.42

 

1.28

 

0.43

 

1.19

 

0.46

 

1.16

n/a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7DEOH '& &KDUDFWHULVWLFV

6\PERO

3DUDPHWHU

&RQGLWLRQV

0LQ

0D[

8QLWV

 

 

 

 

 

 

 

 

II

I or I/O Input Leakage Current

VI = VCCIO or GND

-10

10

µA

IOZ

3-State Output Leakage Current

VI = VCCIO or GND

-10

10

µA

CI

Input Capacitancea

 

-

 

-

8

pF

I

Output Short Circuit Currentb

Vo = GND

-15

-180

mA

 

OS

 

Vo = VCC

40

210

mA

 

 

 

I

CC

D.C. Supply Currentc

V V = V

CCIO

or GND

0.50 (typ)

2

mA

 

 

I, o

 

 

 

 

ICCIO

D.C. Supply Current on VCCIO

 

-

 

0

2

mA

ICCIO(DIF)

D.C. Supply Current on VCCIO

 

-

 

-

-

mA

for Differential I/O

 

 

 

 

 

 

 

 

 

 

IREF

D.C. Supply Current on INREF

 

-

 

-10

10

µA

IPD

Pad Pull-down (programmable)

VCCIO = 3.6 V

-

150

µA

D &DSDFLWDQFH LV VDPSOH WHVWHG RQO\ &ORFN SLQV DUH S) PD[LPXP

E 2QO\ RQH RXWSXW DW D WLPH 'XUDWLRQ VKRXOG QRW H[FHHG VHFRQGV

F )RU FRPPHUFLDO JUDGH GHYLFHV RQO\ 0D[LPXP ,&& LV P$ IRU FRPPHUFLDO

JUDGH DQG DOO LQGXVWULDO JUDGH GHYLFHV DQG P$ IRU DOO PLOLWDU\ JUDGH GHYLFHV

W

W

W ZZZ TXLFNORJLF FRP ‹ 4XLFN/RJLF &RUSRUDWLRQ

W

W

W

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