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tPD |
Combinatorial Delay of the longest path: time taken by the combinatorial circuit to |
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output |
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tSU |
Setup time: time the synchronous input of the flip flop must be stable before the |
0.22 |
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active clock edge |
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tHL |
Hold time: time the synchronous input of the flip flop must be stable after the active |
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clock edge |
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tCO |
Clock to out delay: the amount of time taken by the flip flop to output after the |
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active clock edge. |
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tCWHI |
Clock High Time: required minimum time the clock stays high |
0.46 |
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tCWLO |
Clock Low Time: required minimum time that the clock stays low |
0.46 |
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tSET |
Set Delay: time between when the flip flop is ”set” (high) |
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0.18 |
and when the output is consequently “set” (high) |
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tRESET |
Reset Delay: time between when the flip flop is ”reset” (low) and when the output |
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0.09 |
is consequently “reset” (low) |
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tSW |
Set Width: time that the SET signal remains high/low |
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Reset Width: time that the RESET signal remains high/low |
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Logic Cells (Internal) |
Clock signal generated internally |
1.51 ns (max) |
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1.59 ns (max) |
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I/O’s (External) |
Clock signal generated externally |
2.06 ns (max) |
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1.73 ns (max) |
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7DEOH (FOLSVH *OREDO &ORFN 3HUIRUPDQFH |
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Global clock pin delay to quad net |
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tBGCK |
Global clock buffer delay |
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(quad net to flip flop) |
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Programmable Clock
External Clock
tPGCK
Global Clock Buffer
Global Clock
Clock
Select
tBGCK
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tSWA |
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the |
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WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active |
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WD setup time to WCLK: time the WRITE DATA must be stable before the active |
0.654 |
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WD hold time to WCLK: time the WRITE DATA must be stable after the active edge |
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WE setup time to WCLK: time the WRITE ENABLE must be stable before the active |
0.623 |
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tHWE |
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active |
0 |
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tWCRD |
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the |
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time when the data is available at RD |
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tSWA |
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tHWA |
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tSWD |
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tWCRD |
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tSRA |
RA setup time to RCLK: time the READ ADDRESS must be stable before the active |
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tHRA |
RA hold time to RCLK: time the READ ADDRESS must be stable after the active |
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RE setup time to WCLK: time the READ ENABLE must be stable before the active |
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edge of the READ CLOCK |
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tHRE |
RE hold time to WCLK: time the READ ENABLE must be stable after the active |
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edge of the READ CLOCK |
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tRCRD |
RCLK to RD: time between the active READ CLOCK edge and the time when the |
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data is available at RD |
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rPDRD |
RA to RD: time between when the READ ADDRESS is input and when the DATA |
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2.06 |
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is output |
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RD |
old data |
new data |
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tISU |
Input register setup time: time the synchronous input of the flip flop must be stable |
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before the active clock edge |
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tIHL |
Input register hold time: time the synchronous input of the flip flop must be stable |
0 |
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after the active clock edge |
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tICO |
Input register clock to out: time taken by the flip flop to output after the active clock |
- |
1.08 |
edge |
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tIRST |
Input register reset delay: time between when the flip flop is “reset” (low) and when |
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0.99 |
the output is consequently “reset” (low) |
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tIESU |
Input register clock enable setup time: time “enable” must be stable before the |
0.37 |
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active clock edge |
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Input register clock enable hold time: time “enable” must be stable after the active |
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clock edge |
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LVTTL input delay: Low Voltage TTL for 3.3 V applications |
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LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower |
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applications |
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tSID (GTL+) |
GTL+ input delay: Gunning Transceiver Logic |
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0.68 |
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tSID (SSTL3) |
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V |
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0.55 |
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tSID (SSTL2) |
SSTL2 input delay: Stub Series Terminated Logic for 2.5 V |
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tOUTLH |
Output Delay low to high (90% of H) |
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tOUTHL |
Output Delay high to low (10% of L) |
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tPZH |
Output Delay tri-state to high (90% of H) |
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2.94 |
tPZL |
Output Delay tri-state to low (10% of L) |
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2.34 |
tPHZ |
Output Delay high to tri-State |
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3.07 |
tPLZ |
Output Delay low to tri-State |
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tCOP |
Clock-to-out delay (does not include clock tree delays) |
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3.15 (fast slew) |
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7DEOH 2XWSXW 6OHZ 5DWHV # 9&&,2 9 |
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Rising Edge |
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2.8 V/ns |
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1.0 V/ns |
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Falling Edge |
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2.86 V/ns |
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1.0 V/ns |
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7DEOH 2XWSXW 6OHZ 5DWHV # 9&&,2 9 |
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Rising Edge |
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1.7 V/ns |
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0.6 V/ns |
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Falling Edge |
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1.9 V/ns |
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0.6 V/ns |
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9&& 9ROWDJH |
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2.7 V |
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,QSXW 9ROWDJH |
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-0.5 V to VCCIO +0.5 V |
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VCC |
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Case Temperature |
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125 |
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0.42 |
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2.3 |
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2.16 |
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Delay Factor |
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0.42 |
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1.92 |
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0.43 |
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1.80 |
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0.46 |
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1.76 |
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0.42 |
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1.35 |
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0.43 |
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1.26 |
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1.23 |
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0.42 |
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1.28 |
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0.43 |
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1.19 |
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0.46 |
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1.16 |
n/a |
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3-State Output Leakage Current |
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Input Capacitancea |
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Output Short Circuit Currentb |
Vo = GND |
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D.C. Supply Currentc |
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D.C. Supply Current on VCCIO |
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D.C. Supply Current on VCCIO |
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IREF |
D.C. Supply Current on INREF |
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- |
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-10 |
10 |
µA |
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IPD |
Pad Pull-down (programmable) |
VCCIO = 3.6 V |
- |
150 |
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