QUICK LOGIC QL4090-2PQ240C, QL4090-2PQ240I, QL4090-3CF208C, QL4090-3CF208I, QL4090-3CF208M Datasheet

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© 2002 QuickLogic Corporati on
www.quicklogic.com
1
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Device Highlights
90,000 Usable PLD Gates with 316 I/Os
300 MHz 16-bit Counters, 400 MHz
Datapaths, 160+ MHz FIFOs
0.35µm four-layer metal non-volatile CMOS
process for smallest die sizes
High Speed Embedded SRAM
22 dual-port RAM modules, organized in
user-configurable 1,152 bit blocks
5 ns access times, each port independently
accessible
Fast and efficient for FIFO, RAM, and ROM
functions
Easy to Use / Fast Developm ent
Cycles
100% routable with 100% utilization and
complete pin-out stability
Variable-grain logic cells provide high
performance and 100% utilization
Comprehensive design tools include high
quality Verilog/VHDL synthesis
Advanced I/O Capabilities
Interfaces with both 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V busses
for -1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O Cells with individually controlled
Registered Input Path and Output Enables
Figure 1: QuickRAM Block Diagram
22
RA M
Blocks
1,58 4
Hi gh Sp eed
Logic Cells
Interface
QL4090 QuickRAM Data Sheet
90,000 Usable PLD Gate QuickRAM ESP Combining Performance,
Density and Embedded RAM
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© 2002 QuickLogic Corporation
QL4090 QuickRAM Data Sheet Rev H
Architecture Overview
The QuickRAM
TM
family of ESPs (Embedded Standard Products) offers FPGA logic in
combination with Dual-Port SRAM modules. The QL4090 is a 90,000 usable PLD gate
member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35 µm
four-layer metal process using QuickLogic's patented ViaLink
TM
technology to provide a
unique combination of high performance, high density, low cost, and extreme ease-of-use.
The QL4090 contains 1,584 logic cells and 22 Dual Port RAM modules (see Figure 1). Each
RAM module has 1,152 RAM bits, for a total of 25,344 bits. RAM Modules are Dual Port
(one read port, one write port) and can be configured into one of four modes: 64 (deep) x18
(wide), 128x9, 256x4, or 512x2 (see
Figure 4). With a maximum of 82 I/Os, the QL4090
is available in 208-pin PQFP, 208-pin CQFP 240-pin PQFP and 456-pin PBGA packages.
Designers can cascade multiple RAM modules to increase the depth or width allowed in
single modules by connecting corresponding address lines together and dividing the words
between modules (see
Figure 2). This approach allows up to 512-deep configurations as
large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device.
Software support for the complete QuickRAM family, including the QL4090, is available
through two basic packages. The turnkey QuickWorks
TM
package provides the most
complete ESP software solution from design entry to logic synthesis, to place and route, to
simulation. The QuickTools
TM
packages provides a solution for designers who use Cadence,
Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for
design entry, synthesis, or simulation.
The QuickLogic variable grain logic cell features up to 16 simultaneous inputs and 5 outputs
within a cell that can be fragmented into 5 independent cells. Each cell has a fan-in of 29
including register and control lines (see
Figure 3).
Figure 2: QuickRAM Module Bits
RDATAWDATA
RADDR
RDATA
WADDR
WDATA
RAM
Module
(1,152 bits)
RAM
Module
(1,152 bits)
© 2002 QuickLogic Corporati on
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3
QL4090 QuickRAM Data Sheet Rev H
Product Summary
Total of 316 I/O Pins
308 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
8 high-drive input/distributed network pins
Eight Low-Skew Distributed Networks
Two array clock/control networks available to the logic cell flip-flop clock, set and reset
inputs—each driven by an input-only pin
Six global clock/control networks available to the logic cell F1, clock, set and reset inputs
and the input and I/O register clock, reset and enable inputs as well as the output enable
control—each driven by an input-only or I/O pin, or any logic cell output or I/O cell
feedback
High Performance Silicon
Input + logic cell + output total delays under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
FIFO speeds over 160+ MHz
4
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© 2002 QuickLogic Corporation
QL4090 QuickRAM Data Sheet Rev H
AC Characteristics at V
CC
= 3.3 V, T
A
= 25° C (K = 1.00)
To calculate delays, multiply the appropriate K factor from Table 10: Operating Range by the
following numbers in the tables provided.
Figure 3: QuickRAM Logic Cell
Table 1: Logic Cell
Symbol Parameter
Propagation Delays (ns)
Fanout (5)
1 2 3 4 5
t
PD
Combinatorial Delay
a
a. These limits are derived from a representative selection of the slowest paths through the Quick-
RAM logic cell including typical net delays. Worst case delay values for specific paths should be
determined from timing analysis of your particular design.
1.4 1.7 1.9 2.2 3.2
t
SU
Setup Time
a
1.7 1.7 1.7 1.7 1.7
t
H
Hold Time 0.0 0.0 0.0 0.0 0.0
t
CLK
Clock to Q Delay 0.7 1.0 1.2 1.5 2.5
t
CWHI
Clock High Time 1.2 1.2 1.2 1.2 1.2
t
CWLO
Clock Low Time 1.2 1.2 1.2 1.2 1.2
t
SET
Set Delay 1.0 1.3 1.5 1.8 2.8
t
RESET
Reset Delay 0.8 1.1 1.3 1.6 2.6
t
SW
Set Width 1.9 1.9 1.9 1.9 1.9
t
RW
Reset Width 1.8 1.8 1.8 1.8 1.8
QS
A1
A2
A3
A4
A5
A6
F1
F2
F3
F4
F5
F6
QS
OP
B1
B2
C1
C2
MP
MS
D1
D2
E1
E2
NP
NS
QC
QR
OZ
AZ
QZ
NZ
FZ
© 2002 QuickLogic Corporati on
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5
QL4090 QuickRAM Data Sheet Rev H
Figure 4: QuickRAM Module
Table 2: RAM Cell Synchronous Write Timing
Symbol Parameter
Propagation Delays (ns)
Fanout
1 2 3 4 5
t
SWA
WA Setup Time to WCLK 1.0 1.0 1.0 1.0 1.0
t
HWA
WA Hold Time to WCLK 0.0 0.0 0.0 0.0 0.0
t
SWD
WD Setup Time to WCLK 1.0 1.0 1.0 1.0 1.0
t
HWD
WD Hold Time to WCLK 0.0 0.0 0.0 0.0 0.0
t
SWE
WE Setup Time to WCLK 1.0 1.0 1.0 1.0 1.0
t
HWE
WE Hold Time to WCLK 0.0 0.0 0.0 0.0 0.0
t
WCRD
WCLK to RD (WA=RA)
a
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
T
A
= 25° C. Multiply by the app ropriate Delay Factor, K, for speed gra de, voltage and tempe ratur e
settings as specified in the Operating Range.
5.0 5.3 5.6 5.9 7.1
Table 3: RAM Cell Synchronous Read Timing
Symbol Parameter
Propagation Delays (ns)
Fanout
Logic Cells 1 2 3 4 5
t
SRA
RA Setup Time to RCLK 1.0 1.0 1.0 1.0 1.0
t
HRA
RA Hold Time to RCLK 0.0 0.0 0.0 0.0 0.0
t
SRE
RE Setup Time to RCLK 1.0 1.0 1.0 1.0 1.0
t
HRE
RE Hold Time to RCLK 0.0 0.0 0.0 0.0 0.0
t
RCRD
RCLK to RD
a
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
T
A
= 25° C. Multiply by the app ropriate Delay Factor, K, for speed gra de, voltage and tempe ratur e
settings as specified in the Operating Range.
4.0 4.3 4.6 4.9 6.1
WA
WD
WE
WCLK
RE
RCLK
RA
RD
[8:0]
[17:0]
[8:0]
[17:0 ]
MODE ASYNCRD
[1:0]
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© 2002 QuickLogic Corporation
QL4090 QuickRAM Data Sheet Rev H
Table 4: RAM Cell Asynchronous Read Timing
Symbol Parameter
Propagation Delays (ns)
Fanout
1 2 3 4 5
RPDRD RA to RD
a
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
T
A
= 25° C. Multiply by the app ropriate Delay Factor, K, for speed gra de, voltage and tempe ratur e
settings as specified in the Operating Range.
3.0 3.3 3.6 3.9 5.1
Table 5: Input-Only / Clock Cells
Symbol Parameter
Propagation Delays (ns)
Fanout
1 2 3 4 8 12 24
t
IN
High Drive Input Delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4
t
INI
High Drive Input, Inverting Delay 1.6 1.7 .19 2.0 2.5 3.0 4.5
t
ISU
Input Register Set-Up Time 3.1 3.1 3.1 3.1 3.1 3.1 3.1
t
IH
Input Register Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
t
ICLK
Input Register Clock To Q 0.7 0.8 1.0 1.1 1.6 2.1 3.6
t
IRST
Input Register Reset Delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5
t
IESU
Input Register Clock Enable Setup Time 2.3 2.3 2.3 2.3 2.3 2.3 2.3
t
IEH
Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
Table 6: Clock Cells
Symbol Parameter
Propagation Delays (ns)
Fanout
a
a. The array dist ribu ted ne tw ork s co nsi st of 40 ha lf columns and the glo bal d is tribu ted networks con-
sist of 44 half columns, each driven by an independent buffer. The number of half columns used
does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global
clock has up to 11 loads per half column.
1 2 3 4 8 10 11
t
ACK
Array Clock Delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7
t
GCKP
Global Clock Pin Delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7
t
GCKB
Global Clock Buffer Delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3
© 2002 QuickLogic Corporati on
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7
QL4090 QuickRAM Data Sheet Rev H
Table 7: I/O Cell Input Delays
Symbol Parameter
Propagation Delays (ns)
Fanout
a
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
T
A
= 25° C. Multiply by the ap prop ria te D e lay Fa cto r, K, for speed grade, vo ltage and temperature
settings as specified in the Operating Range.
1 2 3 4 8 10
t
I/O
Input Delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6
t
ISU
Input Register Set-Up Time 3.1 3.1 3.1 3.1 3.1 3.1
t
IH
Input Register Hold Time 0.0 0.0 0.0 0.0 0.0 0.0
t
IOCLK
Input Register Clock to Q 0.7 1.0 1.2 1.5 2.5 3.0
t
IORST
Input Register Reset Delay 0.6 0.9 1.1 1.4 2.4 2.9
t
IESU
Input Register Clock Enable Set-Up Time 2.3 2.3 2.3 2.3 2.3 2.3
t
IEH
Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0
Table 8: I/O Cell Output Delays
Symbol Parameter
Propagation Delays (ns)
Output Load Capacitance (pF)
3 50 75 100 150
t
OUTLH
Output Delay Low to High 2.1 2.5 3.1 3.6 4.7
t
OUTHL
Output Delay High to Low 2.2 2.6 3.2 3.7 4.8
t
PZH
Output Delay Tri-state to High 1.2 1.7 2.2 2.8 3.9
t
PZL
Output Delay Tri-state to Low 1.6 2.0 2.6 3.1 4.2
t
PHZ
Output Delay High to Tri-state
a
a. The following loads are used for t
PXZ
2.0 - - - -
t
PLZ
Output Delay High to Tri-state
a
1.2 - - - -
1ΚΩ
1ΚΩ
tPHZ
tPLZ
5 pF
5 pF
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