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LA-6053P NALAE Hamburg 10AD
Schematic
43 pgs559.46 Kb0

Compal LA-6053P NALAE Hamburg 10AD, Satellite L670, Satellite L670D, Satellite L675, Satellite L675D Schematic

0 (0)
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A
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B
C
C
D
D
E
E
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Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
142Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
142Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
142Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
NALAE LA-6053P Schematics Document
Mobile AMD S1G4/ RS880M / SB820M
Compal confidential
Hamburg 10AD
2009-02-04 Rev. 0.2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
242Wednesday, May 19, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
242Wednesday, May 19, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
242Wednesday, May 19, 2010
2008/04/14 2009/04/14
Compal Electronics, Inc.
1.5V 2.5GHz(250MB/s)
Audio & USB/B
page 33
page 20
page 35,36,37.38,39
40,41
Page 33
Power/B
Power On/Off CKT.
page 20,21,22,23,24
page 34
RTC CKT.
Page 33
page 5,6,7,8
DC/DC Interface CKT.
Power Circuit DC/DC
PCIe 4x
ADM1032ARMZ
page 9,10
Thermal Sensor Fan Control
1.5V DDRIII 1066/1333MHZ
SB820M
Model Name : NALAE
page 7
BANK 0, 1, 2, 3
page 11,12,13,14,15
PCIe Port 2
File Name : LA-6053P
Dual Channel
page 5
PCI-e Mini Card WLAN
page 28
Clock Generator
RS880M
Memory BUS(DDRIII)
AMD S1G4 CPU
200pin DDRIII-SO-DIMM X2
uFCPGA-638 Package
page 16
Compal Confidential
SLG8SP626
A-Link Express II
4X PCI-E
Hyper Transport Link 2.6GHz
16X16
AMD
AMD
LED/B
Page 33
ODD/B
Page 25
page 26
RJ45
page 26
RTL 8105E 10/100M
PCIe port 3
MIC CONN
page 18
Int.
page 32 page 29
MDC 1.5 Conn
Int.KBD
page 32
ALC259Q
page 31
SPI ROM
page 32
HDA Codec
ENE KB926 D3
page 32
Debug Port
LPC BUS
3.3V 33 MHz
HP CONN
page 30
HD Audio
3.3V 24.576MHz/48Mhz
SPK CONN
page 30
MIC CONN
page 30
5V 1.5GHz(150MB/s)
SATA port 3
page 25
eSATA
SATA ODD
page 25
5V 1.5GHz(150MB/s)
USB port 2
5V 480MHz
SATA port 1
page 25
SATA HDD
5V 1.5GHz(150MB/s)
SATA port 0
LCD Conn.
CRT
page 17
page 18
HDMI Conn.
page 19
USB Port 8
Touch Pad/B
Page 33
Card Reader
USB port 5
page 27
USB port 9
page 18
Int. Camera
USB port 6
page 28
BT conn
USB port 0,1
page 28
USB/B
USB
5V 480MHz
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
342Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
342Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
342Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
+NB_CORE
DESIGN CURRENT 6A
APL5331KAC
+1.05VS
DESIGN CURRENT 1.5A
VR_ON#
+1.8VS
DESIGN CURRENT 2.5A
MP2121DQ
SUSP#
+3V_LAN
AO-3413
P-CHANNEL
WOL_EN#
DESIGN CURRENT 330mA
APL5508
+2.5VS
B+
DESIGN CURRENT 300mA
RT8205EGQW
AO-3413
+LCD_VDD
DESIGN CURRENT 1A
ENVDD
+3VALW
DESIGN CURRENT 5A
+5VALW
DESIGN CURRENT 5A
RT8209BGQW
+1.1VALW
DESIGN CURRENT 12A
ISL6265A
+CPU_CORE0
DESIGN CURRENT 36A
+VDDNB
DESIGN CURRENT 4A
VR_ON
RT8209BGQW
+1.5V
DESIGN CURRENT 7.5A
SYSON
POK
+3VL
+5VL
DESIGN CURRENT 0.1A
DESIGN CURRENT 0.1A
N-CHANNEL
SI4800
SUSP
+5VS
DESIGN CURRENT 2A
N-CHANNEL
SI4800
+3VS
DESIGN CURRENT 1.5A
SUSP
AO-3413
BT_PWR#
P-CHANNEL
+BT_VCC
DESIGN CURRENT 180mA
N-CHANNEL
IRF8113
VLDT_EN#
+1.1VS
DESIGN CURRENT 3.5A
N-CHANNEL
IRF8113
SUSP
+1.5VS
DESIGN CURRENT 1A
NALAE Hamburg AMD UMA
APL5331KAC
SUSP
+0.75VS
DESIGN CURRENT 1A
P-CHANNEL
N-CHANNEL
IRF8113
VLDT_EN#
Ipeak = 5A, Imax = 3.5A, Iocp_min = 7.7A
Ipeak = 5A, Imax = 3.5A, Iocp_min = 7.9A
Ipeak = 36A, Imax = 25.2A, Iocp_min = 54A
Ipeak = 12A, Imax = 8.4A, Iocp_min = 18.7A
Ipeak = 7.5A, Imax = 5.25A, Iocp_min = 8.7A
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
442Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
442Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
442Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Voltage Rails
O : ON
X : OFF
O
O
X
S3
X
X
S1
O
OO
OO
X
XX
power
plane
O
O
O
O
O
X
S5 S4/ Battery only
XX X
State
S5 S4/AC & Battery
don't exist
S5 S4/AC
S0
O
O
@ : just reserve , no build
1 0 1 0 0 0 1 0A2
I2C / SMBUS ADDRESSING
1 0 1 0 0 0 0 0
D2
A0
CLOCK GENERATOR (EXT.)
HEX
DDR SO-DIMM 1
ADDRESS
DDR SO-DIMM 0
1 1 0 1 0 0 1 0
DEVICE
SENSOR
EC_SMB_CK2
BATT
KB926
SOURCE
SMBUS Control Table
CLK
GEN
SODIMM
THERMAL
EC_SMB_CK1
EC_SMB_DA2
WLAN
KB926
EC_SMB_DA1
LCD
DDC
ROM
I / II
V
V
V
RS880M
I2C_DATA
I2C_CLK
HDMI
DDC
ROM
RS880M
DDC_DATA0
DDC_CLK0
V
V
+3VS
+3VALW
+5VS
+2.5VS
+1.5VS
+1.5V
+5VALW
+1.8VS
+1.05VS+3VL
+1.1VS
+1.1VALW +VDDNB
HEX
16H
EC SM Bus1 address
Device Address
0001 011X b
Smart Battery
+CPU_CORE
+0.75VS+5VL
HDMI-CEC 34H
0011 010X b
EC KB926D3
CPU SB
S1G4 SB820M
NB
RS880M
VGA
NA
+RTCVCC
BTO (Build-To-Order) Option Table
( B )
Function
BTO
Explain
Description (Y)
HDMI
H@
BLUE TOOTH
BT@
CPU
Comment
EC KB926D3
HEX
Address
EC SM Bus2 address
Device
98H
1001 100X b
ADI1032-1 CPU
9AH
1001 101X b
ADI1032-2 VGA
Platform
Danube
SCL0
SDA0
SB820
VV
SB820
SDA1
SCL1
B+
+NB_CORE
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
H_CADIN1
H_CADIN0
H_CADIP3
H_CADIN2
H_CADIP2
H_CADIP1
H_CADIN3
H_CADIP4
H_CADIN5
H_CADIN4
H_CADIP5
H_CADIN6
H_CADIN8
H_CADIN7
H_CADIN9
H_CADIP8
H_CADIP6
H_CADIP7
H_CADIN10
H_CADIP10
H_CADIN11
H_CADIP11
H_CADIP9
H_CADIN13
H_CADIN12
H_CADIP14
H_CADIP12
H_CADIN14
H_CADIP0
H_CADIN15
H_CADIP15
H_CADIP13
H_CADON15
H_CADOP13
H_CADON2
H_CADON3
H_CADON9
H_CADON6
H_CADON0
H_CADOP11
H_CADOP8
H_CADOP6
H_CADON13
H_CADOP1
H_CADOP2
H_CADOP4
H_CADOP5
H_CADON12
H_CADON7
H_CADON5
H_CADON10
H_CADON8
H_CADON4
H_CADON1
H_CADOP12
H_CADOP15
H_CADOP9
H_CADOP10
H_CADOP14
H_CADOP7
H_CADOP3
H_CADOP0
H_CADON14
H_CADON11
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADIP[0..15]
+VLDT_B
+FAN1
+FAN1
H_CADON[0..15] <11>H_CADIN[0..15]<11>
H_CADOP[0..15] <11>
H_CLKIN0<11>
H_CLKIN1<11>
H_CLKIP1<11>
H_CTLIN1<11>
H_CLKIP0<11>
H_CTLIP1<11>
H_CADIP[0..15]<11>
H_CTLIN0<11>
H_CTLIP0<11>
H_CLKOP0 <11>
H_CLKON0 <11>
H_CLKOP1 <11>
H_CLKON1 <11>
H_CTLOP0 <11>
H_CTLON0 <11>
H_CTLOP1 <11>
H_CTLON1 <11>
EN_DFAN1<30>
FAN_SPEED1 <30>
+1.1VS
+1.1VS
+1.1VS
+5VS
+3VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
542Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
542Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
542Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
250 mil
VLDT=500mA
Near CPU SocketVLDT CAP.
< To NB >< From NB >
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
C7 close to cpu pin
1A
< FAN Control Circuit : Vout = 1.6 x Vset >
HT LINK
JCPUA
FOX_PZ6382A-284S-41F_Champlian
HT LINK
JCPUA
FOX_PZ6382A-284S-41F_Champlian
VLDT_A3
D4
VLDT_A2
D3
VLDT_A1
D2
VLDT_A0
D1
VLDT_B3
AE5
VLDT_B2
AE4
VLDT_B1
AE3
VLDT_B0
AE2
L0_CADIN_H15
N5
L0_CADIN_L15
P5
L0_CADIN_H14
M3
L0_CADIN_L14
M4
L0_CADIN_H13
L5
L0_CADIN_L13
M5
L0_CADIN_H12
K3
L0_CADIN_L12
K4
L0_CADIN_H11
H3
L0_CADIN_L11
H4
L0_CADIN_H10
G5
L0_CADIN_L10
H5
L0_CADIN_H9
F3
L0_CADIN_L9
F4
L0_CADIN_H8
E5
L0_CADIN_L8
F5
L0_CADIN_H7
N3
L0_CADIN_L7
N2
L0_CADIN_H6
L1
L0_CADIN_L6
M1
L0_CADIN_H5
L3
L0_CADIN_L5
L2
L0_CADIN_H4
J1
L0_CADIN_L4
K1
L0_CADIN_H3
G1
L0_CADIN_L3
H1
L0_CADIN_H2
G3
L0_CADIN_L2
G2
L0_CADIN_H1
E1
L0_CADIN_L1
F1
L0_CADIN_H0
E3
L0_CADIN_L0
E2
L0_CADOUT_H15
T4
L0_CADOUT_L15
T3
L0_CADOUT_H14
V5
L0_CADOUT_L14
U5
L0_CADOUT_H13
V4
L0_CADOUT_L13
V3
L0_CADOUT_H12
Y5
L0_CADOUT_L12
W5
L0_CADOUT_H11
AB5
L0_CADOUT_L11
AA5
L0_CADOUT_H10
AB4
L0_CADOUT_L10
AB3
L0_CADOUT_H9
AD5
L0_CADOUT_L9
AC5
L0_CADOUT_H8
AD4
L0_CADOUT_L8
AD3
L0_CADOUT_H7
T1
L0_CADOUT_L7
R1
L0_CADOUT_H6
U2
L0_CADOUT_L6
U3
L0_CADOUT_H5
V1
L0_CADOUT_L5
U1
L0_CADOUT_H4
W2
L0_CADOUT_L4
W3
L0_CADOUT_H3
AA2
L0_CADOUT_L3
AA3
L0_CADOUT_H2
AB1
L0_CADOUT_L2
AA1
L0_CADOUT_H1
AC2
L0_CADOUT_L1
AC3
L0_CADOUT_H0
AD1
L0_CADOUT_L0
AC1
L0_CLKIN_H1
J5
L0_CLKIN_L1
K5
L0_CLKIN_H0
J3
L0_CLKIN_L0
J2
L0_CTLIN_H1
P3
L0_CTLIN_L1
P4
L0_CTLIN_H0
N1
L0_CTLIN_L0
P1
L0_CLKOUT_H1
Y4
L0_CLKOUT_L1
Y3
L0_CLKOUT_H0
Y1
L0_CLKOUT_L0
W1
L0_CTLOUT_H1
T5
L0_CTLOUT_L1
R5
L0_CTLOUT_H0
R2
L0_CTLOUT_L0
R3
U31
APL5607KI-TRG_SO8
U31
APL5607KI-TRG_SO8
EN
1
VIN
2
VOUT
3
VSET
4
GND
8
GND
7
GND
6
GND
5
C1121
1000P_0402_25V8J
@
C1121
1000P_0402_25V8J
@
1
2
C1119
10U_0805_10V4Z
C1119
10U_0805_10V4Z
1
2
C3
0.22U_0603_16V4Z
C3
0.22U_0603_16V4Z
1
2
JFAN
ACES_85204-0300N@
JFAN
ACES_85204-0300N@
1
1
2
2
3
3
GND
4
GND
5
C1122
0.01U_0402_25V7K
@
C1122
0.01U_0402_25V7K
@
1
2
C1120
10U_0805_10V4Z
C1120
10U_0805_10V4Z
1
2
C5
180P_0402_50V8J
C5
180P_0402_50V8J
1
2
C2
10U_0805_10V4Z
C2
10U_0805_10V4Z
1
2
C4
0.22U_0603_16V4Z
C4
0.22U_0603_16V4Z
1
2
C6
180P_0402_50V8J
C6
180P_0402_50V8J
1
2
R795
10K_0402_5%
R795
10K_0402_5%
12
C1
10U_0805_10V4Z
C1
10U_0805_10V4Z
1
2
C7
10U_0805_10V4Z
C7
10U_0805_10V4Z
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_B_MA10
DDR_B_MA7
DDR_B_MA1
DDR_B_MA12
DDR_B_MA6
DDR_B_MA11
DDR_B_MA0
DDR_B_MA9
DDR_B_MA15
DDR_B_MA3
DDR_B_MA5
DDR_B_MA8
DDR_B_MA13
DDR_B_MA2
DDR_B_MA4
DDR_CKE1_DIMMB
DDR_B_D0
DDR_CKE0_DIMMB
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS3
DDR_B_DQS#3
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS7
MEM_P
MEM_N VTT_SENSE
DDR_B_ODT0
DDR_B_ODT1
DDR_A_ODT1
DDR_A_ODT0
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_B_D28
DDR_B_D16
DDR_B_D22
DDR_B_D19
DDR_B_D9
DDR_B_D50
DDR_B_D35
DDR_B_D46
DDR_B_D5
DDR_B_D37
DDR_B_D26
DDR_B_D3
DDR_B_D8
DDR_B_D29
DDR_B_D14
DDR_B_D7
DDR_B_D59
DDR_B_D51
DDR_B_D10
DDR_B_D17
DDR_B_D44
DDR_B_D41
DDR_B_D38
DDR_B_D47
DDR_B_D63
DDR_B_D32
DDR_B_D20
DDR_B_D52
DDR_B_D30
DDR_B_D53
DDR_B_D40
DDR_B_D27
DDR_B_D45
DDR_B_D55
DDR_B_D56
DDR_B_D11
DDR_B_D48
DDR_B_D39
DDR_B_D1
DDR_B_D42
DDR_B_D36
DDR_B_D2
DDR_B_D58
DDR_B_D33
DDR_B_D62
DDR_B_D31
DDR_B_D21
DDR_B_D54
DDR_B_D24
DDR_B_D15
DDR_B_D60
DDR_B_D12
DDR_B_D49
DDR_B_D43
DDR_B_D18
DDR_B_D61
DDR_B_D34
DDR_B_D4
DDR_B_DM6
DDR_B_DM4
DDR_B_DM2
DDR_B_DM0
DDR_B_DM5
DDR_B_DM3
DDR_B_DM1
DDR_B_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0
DDR_A_DM7
DDR_A_D59
DDR_A_D3
DDR_A_D13
DDR_A_D60
DDR_A_D40
DDR_A_D29
DDR_A_D56
DDR_A_D20
DDR_A_D28
DDR_A_D36
DDR_A_D19
DDR_A_D23
DDR_A_D34
DDR_A_D61
DDR_A_D15
DDR_A_D4
DDR_A_D0
DDR_A_D53
DDR_A_D47
DDR_A_D43
DDR_A_D33
DDR_A_D24
DDR_A_D39
DDR_A_D46
DDR_A_D22
DDR_A_D51
DDR_A_D9
DDR_A_D5
DDR_A_D6
DDR_A_D54
DDR_A_D8
DDR_A_D31
DDR_A_D7
DDR_A_D50
DDR_A_D57
DDR_A_D12
DDR_A_D21
DDR_A_D26
DDR_A_D63
DDR_A_D62
DDR_A_D42
DDR_A_D48
DDR_A_D44
DDR_A_D25
DDR_A_D58
DDR_A_D32
DDR_A_D1
DDR_A_D17
DDR_A_D2
DDR_A_D55
DDR_A_D38
DDR_A_D11
DDR_A_D10
DDR_A_D27
DDR_A_D18
DDR_A_D14
DDR_A_D41
DDR_A_D49
DDR_A_D16
DDR_A_D52
DDR_A_D37
DDR_A_D35
DDR_A_D30
DDR_B_D6
DDR_A_D45
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_A_WE#
DDR_B_D25
DDR_A_CAS#
DDR_A_RAS#
DDR_B_D23
DDR_B_D57
DDR_B_D13
DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0
DDR_A_MA15
DDR_A_MA12
DDR_A_MA14
DDR_A_MA13
DDR_A_MA11
DDR_A_MA10
DDR_A_MA6
DDR_A_MA1
DDR_A_MA7
DDR_A_MA2
DDR_A_MA3
DDR_A_MA8
DDR_A_MA5
DDR_A_MA4
DDR_A_MA9
DDR_A_MA0
DDR_B_MA14
DDR_CS1_DIMMA# DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMA#
+MCH_REF
MEM_MB_RST#
MEM_MA_RST#
+MCH_REF
DDR_B_CLK#0
DDR_B_CLK0
DDR_B_CLK#1
DDR_B_CLK1
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1
DDR_CKE1_DIMMB <10>
DDR_CKE0_DIMMB <10>
DDR_CS0_DIMMA#<9>
DDR_CS1_DIMMA#<9> DDR_CS0_DIMMB# <10>
DDR_CS1_DIMMB# <10>
DDR_B_D[63..0]<10>
DDR_A_D[63..0] <9>
DDR_B_DQS7<10>
DDR_B_DQS#7<10>
DDR_B_DQS6<10>
DDR_B_DQS5<10>
DDR_B_DQS4<10>
DDR_B_DQS3<10>
DDR_B_DQS2<10>
DDR_B_DQS1<10>
DDR_B_DQS0<10>
DDR_B_DQS#6<10>
DDR_B_DQS#5<10>
DDR_B_DQS#4<10>
DDR_B_DQS#3<10>
DDR_B_DQS#2<10>
DDR_B_DQS#1<10>
DDR_B_DQS#0<10>
DDR_A_RAS#<9>
DDR_A_CAS#<9>
DDR_A_WE#<9>
DDR_A_BS#0<9>
DDR_A_BS#1<9>
DDR_A_BS#2<9>
DDR_A_MA[15..0]<9>
DDR_CKE0_DIMMA<9>
DDR_CKE1_DIMMA<9>
DDR_A_ODT0<9>
DDR_A_ODT1<9>
DDR_B_ODT0 <10>
DDR_B_ODT1 <10>
DDR_B_MA[15..0] <10>
DDR_B_BS#0 <10>
DDR_B_BS#1 <10>
DDR_B_BS#2 <10>
DDR_B_RAS# <10>
DDR_B_CAS# <10>
DDR_B_DM[7..0]<10> DDR_A_DM[7..0] <9>
DDR_A_DQS0 <9>
DDR_B_WE# <10>
DDR_A_DQS#0 <9>
DDR_A_DQS1 <9>
DDR_A_DQS#1 <9>
DDR_A_DQS2 <9>
DDR_A_DQS#2 <9>
DDR_A_DQS3 <9>
DDR_A_DQS#3 <9>
DDR_A_DQS4 <9>
DDR_A_DQS#4 <9>
DDR_A_DQS5 <9>
DDR_A_DQS#5 <9>
DDR_A_DQS6 <9>
DDR_A_DQS#6 <9>
DDR_A_DQS7 <9>
DDR_A_DQS#7 <9>
MEM_MB_RST# <10>
MEM_MA_RST#<9>
DDR_B_CLK0 <10>
DDR_B_CLK#0 <10>
DDR_B_CLK1 <10>
DDR_B_CLK#1 <10>
DDR_A_CLK0<9>
DDR_A_CLK#0<9>
DDR_A_CLK1<9>
DDR_A_CLK#1<9>
+1.05VS+1.05VS
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
642Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
642Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
642Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Place them close to CPU within 1"
< Processor DDR3 Memory Interface >
< From/To SO_DIMMB >
< From/To SO_DIMMA >
< VTT regulator voltage >
< To SO_DIMMB > < To SO_DIMMA >
< From/To SO_DIMMB > < From/To SO_DIMMA >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< DDR3 VREF is 0.5 ratio >
Close to CPU
R1
1K_0402_1%
R1
1K_0402_1%
1 2
MEM:DATA
JCPUC
FOX_PZ6382A-284S-41F_Champlian
MEM:DATA
JCPUC
FOX_PZ6382A-284S-41F_Champlian
MB_DATA63
AD11
MB_DATA62
AF11
MB_DATA61
AF14
MB_DATA60
AE14
MB_DATA59
Y11
MB_DATA58
AB11
MB_DATA57
AC12
MB_DATA56
AF13
MB_DATA55
AF15
MB_DATA54
AF16
MB_DATA53
AC18
MB_DATA52
AF19
MB_DATA51
AD14
MB_DATA50
AC14
MB_DATA49
AE18
MB_DATA48
AD18
MB_DATA47
AD20
MB_DATA46
AC20
MB_DATA45
AF23
MB_DATA44
AF24
MB_DATA43
AF20
MB_DATA42
AE20
MB_DATA41
AD22
MB_DATA40
AC22
MB_DATA39
AE25
MB_DATA38
AD26
MB_DATA37
AA25
MB_DATA36
AA26
MB_DATA35
AE24
MB_DATA34
AD24
MB_DATA33
AA23
MB_DATA32
AA24
MB_DATA31
G24
MB_DATA30
G23
MB_DATA29
D26
MB_DATA28
C26
MB_DATA27
G26
MB_DATA26
G25
MB_DATA25
E24
MB_DATA24
E23
MB_DATA23
C24
MB_DATA22
B24
MB_DATA21
C20
MB_DATA20
B20
MB_DATA19
C25
MB_DATA18
D24
MB_DATA17
A21
MB_DATA16
D20
MB_DATA15
D18
MB_DATA14
C18
MB_DATA13
D14
MB_DATA12
C14
MB_DATA11
A20
MB_DATA10
A19
MB_DATA9
A16
MB_DATA8
A15
MB_DATA7
A13
MB_DATA6
D12
MB_DATA5
E11
MB_DATA4
G11
MB_DATA3
B14
MB_DATA2
A14
MB_DATA1
A11
MB_DATA0
C11
MA_DATA63
AA12
MA_DATA62
AB12
MA_DATA61
AA14
MA_DATA60
AB14
MA_DATA59
W11
MA_DATA58
Y12
MA_DATA57
AD13
MA_DATA56
AB13
MA_DATA55
AD15
MA_DATA54
AB15
MA_DATA53
AB17
MA_DATA52
Y17
MA_DATA51
Y14
MA_DATA50
W14
MA_DATA49
W16
MA_DATA48
AD17
MA_DATA47
Y18
MA_DATA46
AD19
MA_DATA45
AD21
MA_DATA44
AB21
MA_DATA43
AB18
MA_DATA42
AA18
MA_DATA41
AA20
MA_DATA40
Y20
MA_DATA39
AA22
MA_DATA38
Y22
MA_DATA37
W21
MA_DATA36
W22
MA_DATA35
AA21
MA_DATA34
AB22
MA_DATA33
AB24
MA_DATA32
Y24
MA_DATA31
H22
MA_DATA30
H20
MA_DATA29
E22
MA_DATA28
E21
MA_DATA27
J19
MA_DATA26
H24
MA_DATA25
F22
MA_DATA24
F20
MA_DATA23
C23
MA_DATA22
B22
MA_DATA21
F18
MA_DATA20
E18
MA_DATA19
E20
MA_DATA18
D22
MA_DATA17
C19
MA_DATA16
G18
MA_DATA15
G17
MA_DATA14
C17
MA_DATA13
F14
MA_DATA12
E14
MA_DATA11
H17
MA_DATA10
E17
MA_DATA9
E15
MA_DATA8
H15
MA_DATA7
E13
MA_DATA6
C13
MA_DATA5
H12
MA_DATA4
H11
MA_DATA3
G14
MA_DATA2
H14
MA_DATA1
F12
MA_DATA0
G12
MB_DM7
AD12
MB_DM6
AC16
MB_DM5
AE22
MB_DM4
AB26
MB_DM3
E25
MB_DM2
A22
MB_DM1
B16
MB_DM0
A12
MB_DQS_H7
AF12
MB_DQS_L7
AE12
MB_DQS_H6
AE16
MB_DQS_L6
AD16
MB_DQS_H5
AF21
MB_DQS_L5
AF22
MB_DQS_H4
AC25
MB_DQS_L4
AC26
MB_DQS_H3
F26
MB_DQS_L3
E26
MB_DQS_H2
A24
MB_DQS_L2
A23
MB_DQS_H1
D16
MB_DQS_L1
C16
MB_DQS_H0
C12
MB_DQS_L0
B12
MA_DM7
Y13
MA_DM6
AB16
MA_DM5
Y19
MA_DM4
AC24
MA_DM3
F24
MA_DM2
E19
MA_DM1
C15
MA_DM0
E12
MA_DQS_H7
W12
MA_DQS_L7
W13
MA_DQS_H6
Y15
MA_DQS_L6
W15
MA_DQS_H5
AB19
MA_DQS_L5
AB20
MA_DQS_H4
AD23
MA_DQS_L4
AC23
MA_DQS_H3
G22
MA_DQS_L3
G21
MA_DQS_H2
C22
MA_DQS_L2
C21
MA_DQS_H1
G16
MA_DQS_L1
G15
MA_DQS_H0
G13
MA_DQS_L0
H13
R5 39.2_0402_1%R5 39.2_0402_1%
1 2
C8
1000P_0402_25V8J
C8
1000P_0402_25V8J
1
2
R2
1K_0402_1%
R2
1K_0402_1%
1 2
C9
0.1U_0402_16V7K
C9
0.1U_0402_16V7K
1
2
R4 39.2_0402_1%R4 39.2_0402_1%
1 2
T1PAD T1PAD
MEM:CMD/CTRL/CLK
JCPUB
FOX_PZ6382A-284S-41F_Champlian
MEM:CMD/CTRL/CLK
JCPUB
FOX_PZ6382A-284S-41F_Champlian
VDDR1
D10
VDDR2
C10
VDDR3
B10
VDDR4
AD10
VDDR5
W10
VDDR6
AC10
VDDR7
AB10
VDDR8
AA10
VDDR9
A10
MA1_ODT1
V19
MA1_ODT0
U21
MA0_ODT1
V22
MA0_ODT0
T19
MB1_ODT0
Y26
MB0_ODT1
W23
MB0_ODT0
W26
MB_RESET_L
B18
MB1_CS_L0
U22
MB0_CS_L1
W25
MB0_CS_L0
V26
MA0_CS_L1
U19
MA1_CS_L1
V20
MA1_CS_L0
U20
MA0_CS_L0
T20
MA_ADD15
K19
MA_ADD14
K24
MA_ADD13
V24
MA_ADD12
K20
MA_ADD11
L22
MA_ADD10
R21
MA_ADD9
K22
MA_ADD8
L19
MA_ADD7
L21
MA_ADD6
M24
MA_ADD5
L20
MA_ADD4
M22
MA_ADD3
M19
MA_ADD2
N22
MA_ADD1
M20
MA_ADD0
N21
MA_BANK2
J21
MA_BANK1
R23
MA_BANK0
R20
MA_RAS_L
R19
MA_CAS_L
T22
MA_WE_L
T24
MEMZP
AF10
MEMZN
AE10
VDDR_SENSE
Y10
MEMVREF
W17
MA_CLK_H4
P19
MA_CLK_L4
P20
MA_CLK_H7
Y16
MA_CLK_L7
AA16
MA_CLK_H1
E16
MA_CLK_L1
F16
MA_CLK_H5
N19
MA_CLK_L5
N20
MB_CLK_H4
R26
MB_CLK_L4
R25
MB_CLK_H7
AF18
MB_CLK_L7
AF17
MB_CLK_H1
A17
MB_CLK_L1
A18
MB_CLK_H5
P22
MB_CLK_L5
R22
MA_CKE0
J22
MA_CKE1
J20
MB_CKE0
J25
MB_CKE1
H26
MB_ADD15
J24
MB_ADD14
J23
MB_ADD13
W24
MB_ADD12
L25
MB_ADD11
L26
MB_ADD10
T26
MB_ADD9
K26
MB_ADD8
M26
MB_ADD7
L24
MB_ADD6
N25
MB_ADD5
L23
MB_ADD4
N26
MB_ADD3
N23
MB_ADD2
P26
MB_ADD1
N24
MB_ADD0
P24
MB_BANK2
J26
MB_BANK1
U26
MB_BANK0
R24
MB_RAS_L
U25
MB_CAS_L
U24
MB_WE_L
U23
MA_RESET_L
H16
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CPU_HTREF0
CPU_HTREF1
CPU_THERMTRIP#_R
LDT_RST#
H_PWRGD
LDT_STOP#
+2.5VDDA
THERMDA_CPU
+2.5VDDA
LDT_STOP#
THERMDC_CPU
CPU_DBREQ#
CPU_SVC
CPU_SVD
CPU_TEST21
CPU_TEST24
CPU_TEST29_L_FBCLKOUT_N
CPU_TEST29_H_FBCLKOUT_P
H_PWRGD
LDT_RST#
CPU_PROCHOT#
THERMDA_CPU
THERMDC_CPU
EC_SMB_CK2
EC_SMB_DA2
CPU_THERMTRIP#_R
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
CPU_VDD0_RUN_FB_H
CPU_VDD0_RUN_FB_L
CPU_VDD1_RUN_FB_H
CPU_VDD1_RUN_FB_L
CPU_TDO
CPU_TMS
CPU_TDI
CPU_DBRDY
CPU_TDO
CPU_TRST#
CPU_TCK
LDT_RST#
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
CPU_CLKIN_SC_N
CPU_CLKIN_SC_P
CPU_DBREQ#
CPU_TEST20
CPU_TEST23
CPU_SID
CPU_SIC
CPU_DBRDY
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TCK
CPU_TEST18
CPU_TEST25H
CPU_TEST25L
CPU_TEST19
CPU_TEST12
CPU_TEST22
CPU_TEST27
CPU_TEST17
CPU_TEST16
CPU_TEST14
CPU_TEST15
CPU_SVD
CPU_SVC
CPU_TEST25H
CPU_TEST25L
CPU_TEST22
CPU_TEST24
CPU_TEST20
CPU_TEST19
CPU_TEST18
CPU_TEST12
CPU_TEST21
CPU_TEST27
CPU_TEST23
CPU_PROCHOT#
LDT_STOP#<12,19>
LDT_RST#<19>
CPU_VDDNB_RUN_FB_H <40>
CPU_VDDNB_RUN_FB_L <40>
CPU_VDD0_RUN_FB_H<40>
CPU_VDD0_RUN_FB_L<40>
CPU_VDD1_RUN_FB_H<40>
CPU_VDD1_RUN_FB_L<40>
EC_SMB_DA2 <30>
EC_SMB_CK2 <30>
CPU_SVD <40>
CPU_SVC <40>
H_THERMTRIP# <20>
H_PWRGD<19,40>
CLK_CPU_BCLK<19>
CLK_CPU_BCLK#<19>
H_PROCHOT# <19>
+1.1VS
+2.5VDDA+2.5VS
+1.5VS
+1.5VS
+1.5VS
+3VS
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
742Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
742Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
742Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
VDDA=300mA
route as differential
as short as possible
testpoint under package
< HDT Connector >
< Thermal Sensor >
< Filtered PLL Supply Voltage >
< Serial VID Interface clock & data >
< 200-MHz PLL Reference Clock >
Address:100_1100 Place close to CPU wihtin 1.5"
R36 220_0402_5%R36 220_0402_5%
1 2
SAMTEC_ASP-68200-07
JP2
@ SAMTEC_ASP-68200-07
JP2
@
2
4
6
8
10
12
14
16
18
20
22
2423
21
19
17
15
13
11
9
7
5
3
1
26
JCPUD
FOX_PZ6382A-284S-41F_Champlian
JCPUD
FOX_PZ6382A-284S-41F_Champlian
VDDA1
F8
VDDA2
F9
RESET_L
B7
PWROK
A7
LDTSTOP_L
F10
SIC
AF4
SID
AF5
HT_REF1
P6
HT_REF0
R6
VDD0_FB_H
F6
VDD0_FB_L
E6
VDDIO_FB_H
W9
VDDIO_FB_L
Y9
THERMTRIP_L
AF6
PROCHOT_L
AC7
RSVD2
A5
LDTREQ_L
C6
SVC
A6
SVD
A4
RSVD6
C5
RSVD4
B5
RSVD1
A3
CLKIN_H
A9
CLKIN_L
A8
DBRDY
G10
TMS
AA9
TCK
AC9
TRST_L
AD9
TDI
AF9
DBREQ_L
E10
TDO
AE9
TEST25_H
E9
TEST25_L
E8
TEST19
G9
TEST18
H10
RSVD8
AA7
TEST9
C2
TEST17
D7
TEST16
E7
TEST15
F7
TEST14
C7
TEST12
AC8
TEST7
C3
TEST6
AA6
THERMDC
W7
THERMDA
W8
VDD1_FB_H
Y6
VDD1_FB_L
AB6
TEST29_H
C9
TEST29_L
C8
TEST24
AE7
TEST23
AD7
TEST22
AE8
TEST21
AB8
TEST20
AF7
TEST28_H
J7
TEST28_L
H8
TEST27
AF8
ALERT_L
AE6
TEST10
K8
TEST8
C4
RSVD3
B3
RSVD5
C1
VDDNB_FB_H
H6
VDDNB_FB_L
G6
RSVD7
D5
RSVD11
W18
MEMHOT_L
AA8
RSVD10
H18
RSVD9
H19
VSS
M11
R15 44.2_0402_1%R15 44.2_0402_1%
1 2
R7 1K_0402_5%R7 1K_0402_5%
1 2
T7PAD T7PAD
C14
0.22U_0603_16V4Z
C14
0.22U_0603_16V4Z
1
2
C15
3900P_0402_50V7K
C15
3900P_0402_50V7K
1 2
R39 220_0402_5%R39 220_0402_5%
1 2
R34 1K_0402_5%R34 1K_0402_5%
12
U1
ADM1032ARM-1 ZREEL_MSOP8
U1
ADM1032ARM-1 ZREEL_MSOP8
VDD
1
ALERT#
6
THERM#
4
GND
5
D+
2
D-
3
SCLK
8
SDATA
7
T4PAD T4PAD
L1 FBM_L11_201209_300L_0805L1 FBM_L11_201209_300L_0805
1 2
R31 1K_0402_5%R31 1K_0402_5%
12
T3PAD T3PAD
R21
300_0402_5%
R21
300_0402_5%
1 2
R13
0_0402_5%
@R13
0_0402_5%
@
1 2
T6PAD T6PAD
R25 80.6_0402_1%R25 80.6_0402_1%
12
C13
3300P_0402_50V7K
C13
3300P_0402_50V7K
1
2
R32 1K_0402_5%R32 1K_0402_5%
12
R24
0_0402_5%
R24
0_0402_5%
1 2
R22 510_0402_5%R22 510_0402_5%
12
R28 1K_0402_5%R28 1K_0402_5%
12
R12 1K_0402_5%R12 1K_0402_5%
1 2
R40 300_0402_5%R40 300_0402_5%
1 2
R27 510_0402_5%R27 510_0402_5%
1 2
R265 1K_0402_5%R265 1K_0402_5%
12
R18
300_0402_5%
R18
300_0402_5%
1 2
T2 PADT2 PAD
R201K_0402_5% R201K_0402_5%
1 2
C17
0.01U_0402_25V7K
@
C17
0.01U_0402_25V7K
@
1
2
R38 220_0402_5%R38 220_0402_5%
1 2
C21
3300P_0402_50V7-K
@
C21
3300P_0402_50V7-K
@
1 2
C18
0.01U_0402_25V7K
@
C18
0.01U_0402_25V7K
@
1
2
R37 220_0402_5%R37 220_0402_5%
1 2
R17
300_0402_5%
R17
300_0402_5%
1 2
C20
0.1U_0402_16V7K
C20
0.1U_0402_16V7K
1
2
+
C11
150U_B2_6.3VM_R45M
@
+
C11
150U_B2_6.3VM_R45M
@
1
2
R35 1K_0402_5%R35 1K_0402_5%
12
R6 10K_0402_5%R6 10K_0402_5%
1 2
E
B
C
Q1
MMBT3904_NL_SOT23-3
E
B
C
Q1
MMBT3904_NL_SOT23-3
2
3 1
T5PAD T5PAD
R14 1K_0402_5%R14 1K_0402_5%
1 2
R33 1K_0402_5%R33 1K_0402_5%
12
R29 1K_0402_5%R29 1K_0402_5%
12
C12
4.7U_0805_10V4Z
C12
4.7U_0805_10V4Z
1
2
C16
3900P_0402_50V7K
C16
3900P_0402_50V7K
1 2
R10
169_0402_1%
R10
169_0402_1%
12
C19
0.1U_0402_16V7K
@
C19
0.1U_0402_16V7K
@
1
2
R16 44.2_0402_1%R16 44.2_0402_1%
1 2
R30 1K_0402_5%R30 1K_0402_5%
12
R11 300_0402_5%R11 300_0402_5%
1 2
R191K_0402_5% R191K_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+CPU_CORE +CPU_CORE
+VDDNB
+CPU_CORE
+CPU_CORE +CPU_CORE
+CPU_CORE +CPU_CORE
+1.05VS
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
+VDDNB
+1.05VS
+1.5V
+1.05VS +1.05VS
+1.5V
+1.5V
+CPU_CORE
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
842Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
842Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
842Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Between CPU Socket and DIMM
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
VTT decoupling.
VDD decoupling : +CPU_CORE
VDDIO decoupling : DDR SDRAM I/O ring power
+VDDNB decoupling : Northbridge power
Under CPU Socket
Between CPU Socket and DIMM
Near CPU Socket Right side
Near CPU Socket Left side
Under CPU SocketNear CPU Socket
Under CPU Socket
Under CPU Socket
Under CPU Socket
Between CPU Socket and DIMM
C56 Co-layout with C75
C1124 Co-layout with C1125
Between CPU Socket and DIMM
Near CPU Socket
C46
0.22U_0603_16V4Z
C46
0.22U_0603_16V4Z
1
2
C78
0.22U_0603_16V4Z
C78
0.22U_0603_16V4Z
1
2
C60
0.22U_0603_16V4Z
C60
0.22U_0603_16V4Z
1
2
C82
180P_0402_50V8J
C82
180P_0402_50V8J
1
2
C83
180P_0402_50V8J
C83
180P_0402_50V8J
1
2
C72
4.7U_0805_10V4Z
C72
4.7U_0805_10V4Z
1
2
C45
22U_0805_6.3V6M
C45
22U_0805_6.3V6M
1
2
C30
22U_0805_6.3V6M
C30
22U_0805_6.3V6M
1
2
C67
180P_0402_50V8J
C67
180P_0402_50V8J
1
2
C40
0.01U_0402_25V7K
C40
0.01U_0402_25V7K
1
2
C71
4.7U_0805_10V4Z
C71
4.7U_0805_10V4Z
1
2
C35
22U_0805_6.3V6M
C35
22U_0805_6.3V6M
1
2
C36
0.22U_0603_16V4Z
C36
0.22U_0603_16V4Z
1
2
+
C89
330U_2.5V_M
+
C89
330U_2.5V_M
1
2
C52
0.22U_0603_16V4Z
C52
0.22U_0603_16V4Z
1
2
JCPUE
FOX_PZ6382A-284S-41F_Champlian
JCPUE
FOX_PZ6382A-284S-41F_Champlian
VDD1_25
AC4
VDD1_26
AD2
VDD0_1
G4
VDD0_2
H2
VDD0_3
J9
VDD0_4
J11
VDD0_5
J13
VDD0_7
K6
VDD0_8
K10
VDD0_9
K12
VDD0_10
K14
VDD0_11
L4
VDD0_12
L7
VDD0_13
L9
VDD0_14
L11
VDD0_15
L13
VDD0_17
M2
VDD0_18
M6
VDD0_19
M8
VDD0_20
M10
VDD0_21
N7
VDD0_22
N9
VDD0_23
N11
VDD1_1
P8
VDD1_2
P10
VDD1_3
R4
VDD1_4
R7
VDD1_5
R9
VDD1_6
R11
VDD1_7
T2
VDD1_8
T6
VDD1_9
T8
VDD1_10
T10
VDD1_11
T12
VDD1_12
T14
VDD1_13
U7
VDD1_14
U9
VDD1_15
U11
VDD1_16
U13
VDD1_18
V6
VDD1_19
V8
VDD1_20
V10
VDD1_21
V12
VDD1_22
V14
VDD1_23
W4
VDD1_24
Y2
VDD0_6
J15
VDDNB_1
K16
VDD0_16
L15
VDDNB_2
M16
VDDNB_3
P16
VDDNB_4
T16
VDD1_17
U15
VDDNB_5
V16
VDDIO1
H25
VDDIO2
J17
VDDIO3
K18
VDDIO4
K21
VDDIO5
K23
VDDIO6
K25
VDDIO7
L17
VDDIO8
M18
VDDIO9
M21
VDDIO10
M23
VDDIO11
M25
VDDIO12
N17
VDDIO13
P18
VDDIO14
P21
VDDIO15
P23
VDDIO16
P25
VDDIO17
R17
VDDIO18
T18
VDDIO19
T21
VDDIO20
T23
VDDIO21
T25
VDDIO22
U17
VDDIO23
V18
VDDIO24
V21
VDDIO25
V23
VDDIO26
V25
VDDIO27
Y25
C44
22U_0805_6.3V6M
C44
22U_0805_6.3V6M
1
2
C58
4.7U_0805_10V4Z
C58
4.7U_0805_10V4Z
1
2
C59
0.22U_0603_16V4Z
C59
0.22U_0603_16V4Z
1
2
C57
4.7U_0805_10V4Z
C57
4.7U_0805_10V4Z
1
2
C65
0.01U_0402_25V7K
C65
0.01U_0402_25V7K
1
2
C31
22U_0805_6.3V6M
C31
22U_0805_6.3V6M
1
2
C62
1000P_0402_25V8J
C62
1000P_0402_25V8J
1
2
C61
1000P_0402_25V8J
C61
1000P_0402_25V8J
1
2
C73
4.7U_0805_10V4Z
C73
4.7U_0805_10V4Z
1
2
C64
0.01U_0402_25V7K
C64
0.01U_0402_25V7K
1
2
C77
4.7U_0805_10V4Z
C77
4.7U_0805_10V4Z
1
2
C39
0.22U_0603_16V4Z
C39
0.22U_0603_16V4Z
1
2
JCPUF
FOX_PZ6382A-284S-41F_Champlian
JCPUF
FOX_PZ6382A-284S-41F_Champlian
VSS1
AA4
VSS2
AA11
VSS3
AA13
VSS4
AA15
VSS5
AA17
VSS6
AA19
VSS7
AB2
VSS8
AB7
VSS9
AB9
VSS10
AB23
VSS11
AB25
VSS12
AC11
VSS13
AC13
VSS14
AC15
VSS15
AC17
VSS16
AC19
VSS17
AC21
VSS18
AD6
VSS19
AD8
VSS20
AD25
VSS21
AE11
VSS22
AE13
VSS23
AE15
VSS24
AE17
VSS25
AE19
VSS26
AE21
VSS27
AE23
VSS28
B4
VSS29
B6
VSS30
B8
VSS31
B9
VSS32
B11
VSS33
B13
VSS34
B15
VSS35
B17
VSS36
B19
VSS37
B21
VSS38
B23
VSS39
B25
VSS40
D6
VSS41
D8
VSS42
D9
VSS43
D11
VSS44
D13
VSS45
D15
VSS46
D17
VSS47
D19
VSS48
D21
VSS49
D23
VSS50
D25
VSS51
E4
VSS52
F2
VSS53
F11
VSS54
F13
VSS55
F15
VSS56
F17
VSS57
F19
VSS58
F21
VSS59
F23
VSS60
F25
VSS61
H7
VSS62
H9
VSS63
H21
VSS64
H23
VSS65
J4
VSS66
J6
VSS67
J8
VSS68
J10
VSS69
J12
VSS70
J14
VSS71
J16
VSS72
J18
VSS73
K2
VSS74
K7
VSS75
K9
VSS76
K11
VSS77
K13
VSS78
K15
VSS79
K17
VSS80
L6
VSS81
L8
VSS82
L10
VSS83
L12
VSS84
L14
VSS85
L16
VSS86
L18
VSS87
M7
VSS88
M9
VSS89
AC6
VSS90
M17
VSS91
N4
VSS92
N8
VSS93
N10
VSS94
N16
VSS95
N18
VSS96
P2
VSS97
P7
VSS98
P9
VSS99
P11
VSS100
P17
VSS101
R8
VSS102
R10
VSS103
R16
VSS104
R18
VSS105
T7
VSS106
T9
VSS107
T11
VSS108
T13
VSS109
T15
VSS110
T17
VSS111
U4
VSS112
U6
VSS113
U8
VSS114
U10
VSS115
U12
VSS116
U14
VSS117
U16
VSS118
U18
VSS119
V2
VSS120
V7
VSS121
V9
VSS122
V11
VSS123
V13
VSS124
V15
VSS125
V17
VSS126
W6
VSS127
Y21
VSS128
Y23
VSS129
N6
+
C23
330U_X_2VM_R6M
@
+
C23
330U_X_2VM_R6M
@
1
2
C32
22U_0805_6.3V6M
C32
22U_0805_6.3V6M
1
2
+
C1125
330U_D2E_2.5VM
@
+
C1125
330U_D2E_2.5VM
@
1
2
C41
180P_0402_50V8J
C41
180P_0402_50V8J
1
2
C33
22U_0805_6.3V6M
C33
22U_0805_6.3V6M
1
2
+
C1124
390U_2.5V_M_R10
+
C1124
390U_2.5V_M_R10
1
2
C37
0.01U_0402_25V7K
C37
0.01U_0402_25V7K
1
2
C80
1000P_0402_25V8J
C80
1000P_0402_25V8J
1
2
C50
180P_0402_50V8J
C50
180P_0402_50V8J
1
2
+
C56
390U_2.5V_M_R10
+
C56
390U_2.5V_M_R10
1
2
C49
22U_0805_6.3V6M
C49
22U_0805_6.3V6M
1
2
C48
180P_0402_50V8J
C48
180P_0402_50V8J
1
2
C79
0.22U_0603_16V4Z
C79
0.22U_0603_16V4Z
1
2
C51
0.22U_0603_16V4Z
C51
0.22U_0603_16V4Z
1
2
C81
1000P_0402_25V8J
C81
1000P_0402_25V8J
1
2
C68
180P_0402_50V8J
C68
180P_0402_50V8J
1
2
C54
0.22U_0603_16V4Z
C54
0.22U_0603_16V4Z
1
2
+
C90
330U_2.5V_M
+
C90
330U_2.5V_M
1
2
C70
180P_0402_50V8J
C70
180P_0402_50V8J
1
2
C63
180P_0402_50V8J
C63
180P_0402_50V8J
1
2
C76
4.7U_0805_10V4Z
C76
4.7U_0805_10V4Z
1
2
+
C25
330U_X_2VM_R6M
+
C25
330U_X_2VM_R6M
1
2
C29
22U_0805_6.3V6M
C29
22U_0805_6.3V6M
1
2
C34
22U_0805_6.3V6M
C34
22U_0805_6.3V6M
1
2
+
C26
330U_X_2VM_R6M
+
C26
330U_X_2VM_R6M
1
2
C47
0.22U_0603_16V4Z
C47
0.22U_0603_16V4Z
1
2
C28
22U_0805_6.3V6M
C28
22U_0805_6.3V6M
1
2
+
C24
330U_X_2VM_R6M
@
+
C24
330U_X_2VM_R6M
@
1
2
C53
0.22U_0603_16V4Z
C53
0.22U_0603_16V4Z
1
2
C42
22U_0805_6.3V6M
C42
22U_0805_6.3V6M
1
2
C66
180P_0402_50V8J
C66
180P_0402_50V8J
1
2
C38
180P_0402_50V8J
C38
180P_0402_50V8J
1
2
C43
22U_0805_6.3V6M
C43
22U_0805_6.3V6M
1
2
C74
4.7U_0805_10V4Z
C74
4.7U_0805_10V4Z
1
2
C69
180P_0402_50V8J
C69
180P_0402_50V8J
1
2
+
C75
330U_D2E_2.5VM_R6M
@
+
C75
330U_D2E_2.5VM_R6M
@
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
DDR_A_D36
DDR_A_D63
DDR_A_D26
DDR_A_DQS6
DDR_A_D2
DDR_A_D5
DDR_A_D22
DDR_A_D25
DDR_A_D35
DDR_A_MA12
DDR_A_D14
DDR_A_DQS#0
DDR_A_DQS4
DDR_A_DM6
DDR_A_D42
DDR_CKE1_DIMMA
DDR_A_D27
DDR_A_MA15
DDR_A_D31
DDR_CKE0_DIMMA
DDR_A_D12
DDR_A_D59
DDR_A_MA3
DDR_A_D6
DDR_CS1_DIMMA#
DDR_A_D39
DDR_A_BS#1
DDR_A_WE#
DDR_A_MA7
DDR_A_DQS0
DDR_A_MA0
DDR_A_DM2
DDR_A_DQS7
DDR_A_DM1
DDR_A_D57
DDR_A_D46
DDR_A_D0
DDR_A_D28
DDR_A_DM0
DDR_A_DQS#5
DDR_A_D51
DDR_A_D19
DDR_A_DM4
DDR_A_D4
DDR_A_D30
DDR_A_DQS2
DDR_A_D44
DDR_A_RAS#
DDR_A_D33
DDR_A_D58
DDR_A_DM5
DDR_A_DQS3
DDR_A_MA8
DDR_CS0_DIMMA#
DDR_A_D10
DDR_A_MA6
DDR_A_MA10
DDR_A_D3
MEM_MA_RST#
DDR_A_DQS#7
DDR_A_DQS#6
DDR_A_D1
DDR_A_D40
DDR_A_MA9
DDR_A_D16
DDR_A_D29
DDR_A_DQS#4
DDR_A_D52
DDR_A_DM3
DDR_A_DQS5
DDR_A_D54
DDR_A_D49
DDR_A_BS#2
DDR_A_D45
DDR_A_D9
DDR_A_DM7
DDR_A_MA1
DDR_A_D7
DDR_A_D13
DDR_A_D20
DDR_A_D60
DDR_A_BS#0
DDR_A_CAS# DDR_A_ODT0
DDR_A_D37
DDR_A_MA5
DDR_A_DQS#1
DDR_A_MA14
DDR_A_D55
DDR_A_MA4
DDR_A_D21
DDR_A_D62
DDR_A_D24
DDR_A_D15
DDR_A_D56
DDR_A_D23
DDR_A_D53
DDR_A_D47
DDR_A_ODT1
DDR_A_D18
DDR_A_D43
DDR_A_D34
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_D48
DDR_A_DQS#2
DDR_A_D11
DDR_A_D38
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_D32
DDR_A_DQS#3
DDR_A_MA13
DDR_A_MA11
DDR_A_D50
DDR_A_D8
DDR_A_DQS1
DDR_A_D61
DDR_A_MA2
DDR_A_D41
DDR_A_D17
+VREF_CA+VREF_DQ
DDR_A_MA[0..15] <6>
DDR_A_D[0..63] <6>
DDR_A_DM[0..7] <6>
DDR_CKE0_DIMMA<6>
DDR_CS1_DIMMA#<6>
DDR_A_BS#1 <6>
DDR_A_WE#<6>
DDR_A_RAS# <6>
DDR_CS0_DIMMA# <6>
MEM_MA_RST# <6>
DDR_A_BS#2<6>
DDR_A_BS#0<6>
DDR_A_CAS#<6> DDR_A_ODT0 <6>
DDR_A_ODT1 <6>
DDR_A_CLK#1 <6>
DDR_A_CLK1 <6>
DDR_A_CLK0<6>
DDR_A_CLK#0<6>
DDR_CKE1_DIMMA <6>
SMB_CK_DAT0 <10,20>
SMB_CK_CLK0 <10,20>
DDR_A_DQS3 <6>
DDR_A_DQS0 <6>
DDR_A_DQS#3 <6>
DDR_A_DQS#0 <6>
DDR_A_DQS5 <6>
DDR_A_DQS#5 <6>
DDR_A_DQS7 <6>
DDR_A_DQS#7 <6>
DDR_A_DQS#1<6>
DDR_A_DQS1<6>
DDR_A_DQS#2<6>
DDR_A_DQS2<6>
DDR_A_DQS#4<6>
DDR_A_DQS4<6>
DDR_A_DQS#6<6>
DDR_A_DQS6<6>
+1.5V
+0.75VS
+3VS
+1.5V +1.5V
+VREF_CA
+1.5V
+VREF_DQ
+1.5V
+0.75VS
+0.75VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
942Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
942Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
942Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
DIMM_A STD H:5.2 mm
<Address: 00>
< Close to JDDRH & JDDRL >
Place near DIMM1
C665
0.1U_0402_16V4Z
C665
0.1U_0402_16V4Z
1
2
C351
4.7U_0805_10V4Z
C351
4.7U_0805_10V4Z
1
2
C664
0.1U_0402_16V4Z
C664
0.1U_0402_16V4Z
1
2
C84
4.7U_0805_10V4Z
C84
4.7U_0805_10V4Z
1
2
C961
4.7U_0603_6.3V6K
C961
4.7U_0603_6.3V6K
1
2
C235
1000P_0402_25V8J
C235
1000P_0402_25V8J
1
2
C640
0.1U_0402_16V4Z
C640
0.1U_0402_16V4Z
1
2
R315
1K_0402_1%
R315
1K_0402_1%
1 2
C647
0.1U_0402_16V4Z
C647
0.1U_0402_16V4Z
1
2
C645
0.1U_0402_16V4Z
C645
0.1U_0402_16V4Z
1
2
C91
0.1U_0402_16V4Z
C91
0.1U_0402_16V4Z
1
2
C646
0.1U_0402_16V4Z
C646
0.1U_0402_16V4Z
1
2
R310
1K_0402_1%
R310
1K_0402_1%
1 2
C641
0.1U_0402_16V4Z
C641
0.1U_0402_16V4Z
1
2
R49
1K_0402_1%
R49
1K_0402_1%
1 2
C642
0.1U_0402_16V4Z
C642
0.1U_0402_16V4Z
1
2
R48
1K_0402_1%
R48
1K_0402_1%
1 2
C87
0.1U_0402_16V4Z
C87
0.1U_0402_16V4Z
1
2
C643
0.1U_0402_16V4Z
C643
0.1U_0402_16V4Z
1
2
C680
0.01U_0402_25V7K
C680
0.01U_0402_25V7K
1
2
JDDRL
TYCO_2-2013289-1
JDDRL
TYCO_2-2013289-1
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
C85
0.01U_0402_25V7K
C85
0.01U_0402_25V7K
1
2
C10
1000P_0402_25V8J
C10
1000P_0402_25V8J
1
2
C88
0.1U_0402_16V4Z
C88
0.1U_0402_16V4Z
1
2
C644
0.1U_0402_16V4Z
C644
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_B_D[0..63]
DDR_B_MA[0..15]
DDR_B_DM[0..7]
DDR_B_DQS6
DDR_B_D26
DDR_B_D63
DDR_B_D36
DDR_B_D35
DDR_B_D25
DDR_B_D22
DDR_B_D5
DDR_B_D2
DDR_B_DQS#0
DDR_B_D14
DDR_B_MA12
DDR_CKE1_DIMMB
DDR_B_D42
DDR_B_DM6
DDR_B_DQS4
DDR_B_MA15
DDR_B_D27
DDR_B_D12
DDR_CKE0_DIMMB
DDR_B_D31
DDR_B_MA3
DDR_B_D59
DDR_B_BS#1
DDR_B_D39
DDR_CS1_DIMMB#
DDR_B_D6
DDR_B_DQS0
DDR_B_MA7
DDR_B_WE#
DDR_B_MA0
DDR_B_DM2
DDR_B_D0
DDR_B_D46
DDR_B_D57
DDR_B_DM1
DDR_B_DQS7
DDR_B_DM0
DDR_B_D28
DDR_B_DM4
DDR_B_D19
DDR_B_D51
DDR_B_DQS#5
DDR_B_DQS2
DDR_B_D30
DDR_B_D4
DDR_B_D33
DDR_B_RAS#
DDR_B_D44
DDR_B_DQS3
DDR_B_DM5
DDR_B_D58
DDR_B_MA8
DDR_CS0_DIMMB#
DDR_B_MA10
DDR_B_MA6
DDR_B_D10
DDR_B_DQS#6
DDR_B_DQS#7
MEM_MB_RST#
DDR_B_D3
DDR_B_D16
DDR_B_MA9
DDR_B_D1
DDR_B_DQS#4
DDR_B_D29
DDR_B_D49
DDR_B_D54
DDR_B_DQS5
DDR_B_DM3
DDR_B_D9
DDR_B_D45
DDR_B_BS#2
DDR_B_D20
DDR_B_D13
DDR_B_D7
DDR_B_MA1
DDR_B_DM7
DDR_B_BS#0
DDR_B_D60
DDR_B_D37
DDR_B_ODT0DDR_B_CAS#
DDR_B_D55
DDR_B_MA14
DDR_B_DQS#1
DDR_B_MA5
DDR_B_D21
DDR_B_MA4
DDR_B_D62
DDR_B_D15
DDR_B_D24
DDR_B_D47
DDR_B_D53
DDR_B_D23
DDR_B_D56
DDR_B_D43
DDR_B_D18
DDR_B_ODT1
DDR_B_CLK#1
DDR_B_CLK1
DDR_B_D34
DDR_B_DQS#2
DDR_B_D48
DDR_B_CLK#0
DDR_B_CLK0
DDR_B_D11
DDR_B_D50
DDR_B_MA11
DDR_B_MA13
DDR_B_DQS#3
DDR_B_D32
DDR_B_MA2
DDR_B_D61
DDR_B_DQS1
DDR_B_D8
DDR_B_D17
DDR_B_D41
DDR_B_D40
DDR_B_D38
DDR_B_D52
DDR_B_MA[0..15] <6>
DDR_B_D[0..63] <6>
DDR_B_DM[0..7] <6>
DDR_CS1_DIMMB#<6>
DDR_CKE0_DIMMB<6>
DDR_CS0_DIMMB# <6>
DDR_B_RAS# <6>
DDR_B_WE#<6>
DDR_B_BS#1 <6>
DDR_B_CAS#<6>
DDR_B_BS#0<6>
DDR_B_BS#2<6>
MEM_MB_RST# <6>
DDR_B_CLK1 <6>
DDR_B_CLK#1 <6>
DDR_B_ODT1 <6>
DDR_B_ODT0 <6>
DDR_CKE1_DIMMB <6>
DDR_B_CLK#0<6>
DDR_B_CLK0<6>
DDR_B_DQS2<6>
DDR_B_DQS#2<6>
DDR_B_DQS4<6>
DDR_B_DQS#4<6>
DDR_B_DQS6<6>
DDR_B_DQS#6<6>
DDR_B_DQS#0 <6>
DDR_B_DQS0 <6>
DDR_B_DQS#3 <6>
DDR_B_DQS3 <6>
DDR_B_DQS5 <6>
DDR_B_DQS#5 <6>
DDR_B_DQS7 <6>
DDR_B_DQS#7 <6>
DDR_B_DQS#1<6>
DDR_B_DQS1<6>
SMB_CK_DAT0 <9,20>
SMB_CK_CLK0 <9,20>
+0.75VS
+1.5V+1.5V
+3VS
+VREF_CA
+1.5V
+1.5V
+0.75VS
+1.5V
+VREF_DQ
+0.75VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
10 42Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
10 42Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
10 42Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
DIMM_B STD H:9.2mm
<Address: 01>
Place near DIMM2
C128 Co-layout with C86
C675
0.1U_0402_16V4Z
C675
0.1U_0402_16V4Z
1
2
C353
0.1U_0402_16V4Z
C353
0.1U_0402_16V4Z
1
2
C682
1000P_0402_25V8J
C682
1000P_0402_25V8J
1
2
C666
0.1U_0402_16V4Z
C666
0.1U_0402_16V4Z
1
2
C92
4.7U_0805_10V4Z
C92
4.7U_0805_10V4Z
1
2
C677
0.1U_0402_16V4Z
C677
0.1U_0402_16V4Z
1
2
C671
0.1U_0402_16V4Z
C671
0.1U_0402_16V4Z
1
2
C668
0.1U_0402_16V4Z
C668
0.1U_0402_16V4Z
1
2
C676
0.1U_0402_16V4Z
C676
0.1U_0402_16V4Z
1
2
C925
4.7U_0603_6.3V6K
C925
4.7U_0603_6.3V6K
1
2
C674
0.1U_0402_16V4Z
C674
0.1U_0402_16V4Z
1
2
C669
0.1U_0402_16V4Z
C669
0.1U_0402_16V4Z
1
2
+
C128
390U_2.5V_M_R10
+
C128
390U_2.5V_M_R10
1
2
JDDRH
LOTES_AAA-DDR-111-K01
JDDRH
LOTES_AAA-DDR-111-K01
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G2
206
G1
205
C672
0.1U_0402_16V4Z
C672
0.1U_0402_16V4Z
1
2
C352
4.7U_0805_10V4Z
C352
4.7U_0805_10V4Z
1
2
C667
0.1U_0402_16V4Z
C667
0.1U_0402_16V4Z
1
2
C670
0.1U_0402_16V4Z
C670
0.1U_0402_16V4Z
1
2
C673
0.1U_0402_16V4Z
C673
0.1U_0402_16V4Z
1
2
+
C86
330U_X_2VM_R6M
@
+
C86
330U_X_2VM_R6M
@
1
2
C683
1000P_0402_25V8J
C683
1000P_0402_25V8J
1
2
C93
0.1U_0402_16V4Z
C93
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3
PCIE_CALRP
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
H_CADIN[0..15]
H_CADIP[0..15]H_CADOP[0..15]
H_CADON[0..15]
PCIE_CALRN
SB_TX1N_C
H_CADIN0
H_CADIP1
H_CADIN1
HT_RXCALP
HT_RXCALN
H_CADIN2
H_CADIP2
H_CADIN3
H_CADIP3
HT_TXCALP
HT_TXCALN
H_CTLIN0
H_CTLIP0
H_CTLON0
H_CADIN4
H_CADIP4
H_CADIN5
H_CADIP5
H_CADIN6
H_CADIP6
H_CADIN7
H_CADIP7
H_CADIN8
H_CADIP8
H_CADIN9
H_CADIP9
H_CADIN10
H_CADIP10
H_CTLOP0
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIN13
H_CADIP13
H_CADIN14
H_CADIP14
H_CADIN15
H_CADIP15
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CTLIP1
H_CTLIN1
H_CADON2
H_CTLOP1
H_CADOP2
H_CTLON1
H_CADOP3
H_CADON3
H_CADON4
H_CADOP4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADON10
H_CADOP10
H_CADON9
H_CADOP9
H_CADOP8
H_CADON8
H_CADIP0
PCIE_ITX_C_PRX_P2 <27>
PCIE_ITX_C_PRX_N2 <27>
PCIE_ITX_C_PRX_P3 <25>
PCIE_ITX_C_PRX_N3 <25>
PCIE_PTX_C_IRX_P3<25>
PCIE_PTX_C_IRX_N3<25>
PCIE_PTX_C_IRX_P2<27>
PCIE_PTX_C_IRX_N2<27>
SB_RX1P<19>
SB_RX1N<19>
SB_RX0P<19>
SB_RX0N<19>
SB_TX0P <19>
SB_TX1N <19>
SB_TX0N <19>
SB_TX1P <19>
SB_RX3P<19>
SB_RX3N<19>
SB_RX2P<19>
SB_RX2N<19>
SB_TX2P <19>
SB_TX2N <19>
SB_TX3N <19>
SB_TX3P <19>
H_CLKIN0 <5>
H_CLKIP0 <5>
H_CTLIN0 <5>
H_CTLIP0 <5>
H_CLKON0<5>
H_CLKOP0<5>
H_CLKOP1<5>
H_CLKON1<5>
H_CTLOP0<5>
H_CTLON0<5>
H_CLKIN1 <5>
H_CLKIP1 <5>
H_CTLIN1 <5>
H_CTLIP1 <5>H_CTLOP1<5>
H_CTLON1<5>
H_CADIP[0..15] <5>
H_CADIN[0..15] <5>
H_CADOP[0..15] <5>
H_CADON[0..15] <5>
HDMI_CLK0+ <18>
HDMI_CLK0- <18>
HDMI_TXD2+ <18>
HDMI_TXD2- <18>
HDMI_TXD1+ <18>
HDMI_TXD1- <18>
HDMI_TXD0+ <18>
HDMI_TXD0- <18>
+1.1VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
11 42Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
11 42Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
11 42Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
< To LAN >
< To WLAN >
0718 Place within 1"
layout 1:2
0718 Place within 1"
layout 1:2
DP0 GFX_TX0,TX1,TX2 and TX3
RS880M Display Port Support (muxed on GFX)
DP1 GFX_TX4,TX5,TX6 and TX7
AUX0 and HPD0
AUX1 and HPD1
< To LAN >
< To WLAN >
< To SB820 : x4 PCEI A-link>
< From SB820 : x4 PCIE A-link >
< TX Impedance Calibration. Connect to GND >
< RX Impedance Calibration. Connect to VDDPCIE >
< From S1G4 CPU : x16 HT> < To S1G4 CPU : x16 HT>
< Transmitter Calibration Resistor to HT_TXCALN >
< If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs >
C131 0.1U_0402_16V7KC131 0.1U_0402_16V7K
1 2
C136 0.1U_0402_16V7KC136 0.1U_0402_16V7K
1 2
C132 0.1U_0402_16V7KC132 0.1U_0402_16V7K
1 2
C129 0.1U_0402_16V7KC129 0.1U_0402_16V7K
1 2
C138 0.1U_0402_16V7KC138 0.1U_0402_16V7K
1 2
C139 0.1U_0402_16V7KC139 0.1U_0402_16V7K
1 2
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
U3B
RS780M_FCBGA528880MR1@
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
U3B
RS780M_FCBGA528880MR1@
SB_TX3P
AD5
SB_TX3N
AE5
GPP_TX2P
AA2
GPP_TX2N
AA1
GPP_TX3P
Y1
GPP_TX3N
Y2
SB_RX3P
W5
SB_RX3N
Y5
GPP_RX2P
AD1
GPP_RX2N
AD2
GPP_RX3P
V5
GPP_RX3N
W6
SB_TX0P
AD7
SB_TX0N
AE7
SB_TX1P
AE6
SB_TX1N
AD6
SB_RX0P
AA8
SB_RX0N
Y8
SB_RX1P
AA7
SB_RX1N
Y7
PCE_CALRP(PCE_BCALRP)
AC8
PCE_CALRN(PCE_BCALRN)
AB8
SB_TX2N
AC6
SB_RX2P
AA5
SB_RX2N
AA6
SB_TX2P
AB6
GPP_RX0P
AE3
GPP_RX0N
AD4
GPP_RX1P
AE2
GPP_RX1N
AD3
GPP_TX0P
AC1
GPP_TX0N
AC2
GPP_TX1P
AB4
GPP_TX1N
AB3
GFX_RX0P
D4
GFX_RX0N
C4
GFX_RX1P
A3
GFX_RX1N
B3
GFX_RX2P
C2
GFX_RX2N
C1
GFX_RX3P
E5
GFX_RX3N
F5
GFX_RX4P
G5
GFX_RX4N
G6
GFX_RX5P
H5
GFX_RX5N
H6
GFX_RX6P
J6
GFX_RX6N
J5
GFX_RX7P
J7
GFX_RX7N
J8
GFX_RX8P
L5
GFX_RX8N
L6
GFX_RX9P
M8
GFX_RX9N
L8
GFX_RX10P
P7
GFX_RX10N
M7
GFX_RX11P
P5
GFX_RX11N
M5
GFX_RX12P
R8
GFX_RX12N
P8
GFX_RX13P
R6
GFX_RX13N
R5
GFX_RX14P
P4
GFX_RX14N
P3
GFX_RX15P
T4
GFX_RX15N
T3
GFX_TX0P
A5
GFX_TX0N
B5
GFX_TX1P
A4
GFX_TX1N
B4
GFX_TX2P
C3
GFX_TX2N
B2
GFX_TX3P
D1
GFX_TX3N
D2
GFX_TX4P
E2
GFX_TX4N
E1
GFX_TX5P
F4
GFX_TX5N
F3
GFX_TX6P
F1
GFX_TX6N
F2
GFX_TX7P
H4
GFX_TX7N
H3
GFX_TX8P
H1
GFX_TX8N
H2
GFX_TX9P
J2
GFX_TX9N
J1
GFX_TX10P
K4
GFX_TX10N
K3
GFX_TX11P
K1
GFX_TX11N
K2
GFX_TX12P
M4
GFX_TX12N
M3
GFX_TX13P
M1
GFX_TX13N
M2
GFX_TX14P
N2
GFX_TX14N
N1
GFX_TX15P
P1
GFX_TX15N
P2
GPP_TX4P
Y4
GPP_TX4N
Y3
GPP_TX5P
V1
GPP_TX5N
V2
GPP_RX4P
U5
GPP_RX4N
U6
GPP_RX5P
U8
GPP_RX5N
U7
C134 0.1U_0402_16V7KC134 0.1U_0402_16V7K
1 2
C137 0.1U_0402_16V7KC137 0.1U_0402_16V7K
1 2
R61 301_0402_1%R61 301_0402_1%
1 2
R59 1.27K_0402_1%R59 1.27K_0402_1%
1 2
PART 1 OF 6
HYPER TRANSPORT CPU I/F
U3A
RS780M_FCBGA528880MR1@
PART 1 OF 6
HYPER TRANSPORT CPU I/F
U3A
RS780M_FCBGA528880MR1@
HT_RXCAD15P
U19
HT_RXCAD15N
U18
HT_RXCAD14P
U20
HT_RXCAD14N
U21
HT_RXCAD13P
V21
HT_RXCAD13N
V20
HT_RXCAD12P
W21
HT_RXCAD12N
W20
HT_RXCAD11P
Y22
HT_RXCAD11N
Y23
HT_RXCAD10P
AA24
HT_RXCAD10N
AA25
HT_RXCAD9P
AB25
HT_RXCAD9N
AB24
HT_RXCAD8P
AC24
HT_RXCAD8N
AC25
HT_RXCAD7P
N24
HT_RXCAD7N
N25
HT_RXCAD6P
P25
HT_RXCAD6N
P24
HT_RXCAD5P
P22
HT_RXCAD5N
P23
HT_RXCAD4P
T25
HT_RXCAD4N
T24
HT_RXCAD3P
U24
HT_RXCAD3N
U25
HT_RXCAD2P
V25
HT_RXCAD2N
V24
HT_RXCAD1P
V22
HT_RXCAD1N
V23
HT_RXCAD0P
Y25
HT_RXCAD0N
Y24
HT_RXCLK1P
AB23
HT_RXCLK1N
AA22
HT_RXCLK0P
T22
HT_RXCLK0N
T23
HT_RXCTL0P
M22
HT_RXCTL0N
M23
HT_RXCTL1P
R21
HT_RXCTL1N
R20
HT_RXCALP
C23
HT_RXCALN
A24
HT_TXCAD15P
P18
HT_TXCAD15N
M18
HT_TXCAD14P
M21
HT_TXCAD14N
P21
HT_TXCAD13P
M19
HT_TXCAD13N
L18
HT_TXCAD12P
L19
HT_TXCAD12N
J19
HT_TXCAD11P
J18
HT_TXCAD11N
K17
HT_TXCAD10P
J20
HT_TXCAD10N
J21
HT_TXCAD9P
G20
HT_TXCAD9N
H21
HT_TXCAD8P
F21
HT_TXCAD8N
G21
HT_TXCAD7P
K23
HT_TXCAD7N
K22
HT_TXCAD6P
K24
HT_TXCAD6N
K25
HT_TXCAD5P
J25
HT_TXCAD5N
J24
HT_TXCAD4P
H23
HT_TXCAD4N
H22
HT_TXCAD3P
F23
HT_TXCAD3N
F22
HT_TXCAD2P
F24
HT_TXCAD2N
F25
HT_TXCAD1P
E24
HT_TXCAD1N
E25
HT_TXCAD0P
D24
HT_TXCAD0N
D25
HT_TXCLK1P
L21
HT_TXCLK1N
L20
HT_TXCLK0P
H24
HT_TXCLK0N
H25
HT_TXCTL0P
M24
HT_TXCTL0N
M25
HT_TXCTL1P
P19
HT_TXCTL1N
R18
HT_TXCALP
B24
HT_TXCALN
B25
C135 0.1U_0402_16V7KC135 0.1U_0402_16V7K
1 2
C130 0.1U_0402_16V7KC130 0.1U_0402_16V7K
1 2
R60301_0402_1% R60301_0402_1%
1 2
R58 2K_0402_1%R58 2K_0402_1%
1 2
C140 0.1U_0402_16V7KC140 0.1U_0402_16V7K
1 2
C133 0.1U_0402_16V7KC133 0.1U_0402_16V7K
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+NB_HTPVDD
+VDDLTP18
+VDDLT18
NB_RESET#
NB_REFCLK_P
+NB_PLLVDD
UMA_CRT_R
UMA_CRT_G
UMA_CRT_B
UMA_CRT_R
UMA_CRT_B
UMA_CRT_VSYNC
UMA_CRT_G
UMA_CRT_HSYNC
NB_PWRGD
HT_REFCLKP
HT_REFCLKN
+AVDD2
NB_PWRGD
NB_LDTSTOP#
+VDDA18PCIEPLL
+VDDA18HTPLL
+AVDDQ
+AVDD1
+NB_PLLVDD
VARY_ENBKL
+AVDD1
+AVDD2
+AVDDQ
+NB_HTPVDD
+VDDLT18
+VDDLTP18
CPU_LDT_REQ#
NB_LDTSTOP#
NB_REFCLK_N
NB_PWRGD<20>
UMA_CRT_HSYNC<15,16>
UMA_CRT_VSYNC<15,16>
NB_REFCLK_P<19>
CLK_SBSRC_BCLK<19>
CLK_SBSRC_BCLK#<19>
HPD <18>
HT_REFCLKP<19>
HT_REFCLKN<19>
PLT_RST#<15,19,25,27,30,31>
UMA_CRT_R<16>
UMA_CRT_G<16>
UMA_CRT_B<16>
AUX_CAL<15>
SUS_STAT# <15,20>
UMA_CRT_CLK<16>
UMA_CRT_DATA<16>
LCD_TXOUT2- <17>
LCD_TXOUT0- <17>
LCD_TXOUT1- <17>
LCD_TXOUT2+ <17>
LCD_TXOUT0+ <17>
LCD_TXOUT1+ <17>
LCD_TXCLK- <17>
LCD_TXCLK+ <17>
CPU_LDT_REQ#<19>
HDMIDAT_UMA<18>
HDMICLK_UMA<18>
LCD_EDID_DATA<17>
LCD_EDID_CLK<17>
LCD_TZOUT2+ <17>
LCD_TZOUT0+ <17>
LCD_TZOUT1+ <17>
LCD_TZOUT2- <17>
LCD_TZOUT0- <17>
LCD_TZOUT1- <17>
LCD_TZCLK- <17>
LCD_TZCLK+ <17>
UMA_ENBKL <30>
UMA_ENVDD <17>
GMCH_INVT_PWM <17>
LDT_STOP#<7,19>
NB_REFCLK_N<19>
+NB_PLLVDD
+NB_HTPVDD
+VDDA18PCIEPLL
+VDDA18HTPLL
+1.8VS
+1.8VS
+1.1VS
+1.8VS
+3VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
12 42Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
12 42Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
12 42Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Strap pin
< Strap option pin or gate side-port memory IO >
AVDD=100mA
< LVDS dual channel : channel 1 >
< LVDS dual channel : channel 2 >
< HDMI hot-plug detection >
< Dedicated power for the DAC which can affect display quality >
L7
BLM18PG121SN1D_0603
L7
BLM18PG121SN1D_0603
1 2
C149
0.1U_0402_16V7K
C149
0.1U_0402_16V7K
1 2
L4
0_0603_5%
L4
0_0603_5%
L3
BLM18PG121SN1D_0603
L3
BLM18PG121SN1D_0603
1 2
C156
0.1U_0402_16V7K
C156
0.1U_0402_16V7K
1
2
R72 0_0402_5%R72 0_0402_5%
1 2
R70 4.7K_0402_5%R70 4.7K_0402_5%
1 2
R68 300_0402_5%R68 300_0402_5%
1 2
R87 140_0402_1%R87 140_0402_1%
1 2
T8 PADT8 PAD
R71 0_0402_5%@R71 0_0402_5%@
1 2
L10
BLM18PG121SN1D_0603
L10
BLM18PG121SN1D_0603
1 2
L8
BLM18PG121SN1D_0603
L8
BLM18PG121SN1D_0603
1 2
R65 715_0402_1%R65 715_0402_1%
1 2
C144
2.2U_0603_6.3V4Z
C144
2.2U_0603_6.3V4Z
1
2
R101 0_0402_5%
@
R101 0_0402_5%
@
1 2
C141
2.2U_0603_6.3V4Z
C141
2.2U_0603_6.3V4Z
1
2
C157
4.7U_0805_10V4Z
C157
4.7U_0805_10V4Z
1
2
R89 150_0402_1%R89 150_0402_1%
1 2
C154
2.2U_0603_6.3V4Z
C154
2.2U_0603_6.3V4Z
1
2
U2
NC7SZ08P5X_NL_SC70-5
U2
NC7SZ08P5X_NL_SC70-5
B
2
A
1
Y
4
P
5
G
3
L9
BLM18PG121SN1D_0603
L9
BLM18PG121SN1D_0603
1 2
C145
0.1U_0402_16V7K
C145
0.1U_0402_16V7K
1
2
C150
2.2U_0603_6.3V4Z
C150
2.2U_0603_6.3V4Z
1
2
R66 0_0402_5%R66 0_0402_5%
1 2
R83
2.2K_0402_5%
R83
2.2K_0402_5%
1 2
PART 3 OF 6
PM
CLOCKs PLL PWR
MIS.
CRT/TVOUT
LVTM
U3C
RS780M_FCBGA528880MR1@
PART 3 OF 6
PM
CLOCKs PLL PWR
MIS.
CRT/TVOUT
LVTM
U3C
RS780M_FCBGA528880MR1@
VDDA18HTPLL
H17
SYSRESETb
D8
POWERGOOD
A10
LDTSTOPb
C10
ALLOW_LDTSTOP
C12
REFCLK_P/OSCIN(OSCIN)
E11
PLLVDD(NC)
A12
HPD(NC)
D10
DDC_CLK0/AUX0P(NC)
A8
DDC_DATA0/AUX0N(NC)
B8
THERMALDIODE_P
AE8
THERMALDIODE_N
AD8
I2C_CLK
B9
STRP_DATA
B10
GFX_REFCLKP
T2
GFX_REFCLKN
T1
GPP_REFCLKP
U1
GPP_REFCLKN
U2
PLLVDD18(NC)
D14
PLLVSS(NC)
B12
TXOUT_L0P(NC)
A22
TXOUT_L0N(NC)
B22
TXOUT_L1P(NC)
A21
TXOUT_L1N(NC)
B21
TXOUT_L2P(NC)
B20
TXOUT_L2N(DBG_GPIO0)
A20
TXOUT_L3P(NC)
A19
TXOUT_U0P(NC)
B18
TXOUT_L3N(DBG_GPIO2)
B19
TXOUT_U0N(NC)
A18
TXOUT_U1P(PCIE_RESET_GPIO3)
A17
TXOUT_U1N(PCIE_RESET_GPIO2)
B17
TXOUT_U2P(NC)
D20
TXOUT_U2N(NC)
D21
TXOUT_U3P(PCIE_RESET_GPIO5)
D18
TXOUT_U3N(NC)
D19
TXCLK_LP(DBG_GPIO1)
B16
TXCLK_LN(DBG_GPIO3)
A16
TXCLK_UP(PCIE_RESET_GPIO4)
D16
TXCLK_UN(PCIE_RESET_GPIO1)
D17
VDDLTP18(NC)
A13
VSSLTP18(NC)
B13
C_Pr(DFT_GPIO5)
E17
Y(DFT_GPIO2)
F17
COMP_Pb(DFT_GPIO4)
F15
RED(DFT_GPIO0)
G18
TMDS_HPD(NC)
D9
I2C_DATA
A9
TESTMODE
D13
HT_REFCLKN
C24
HT_REFCLKP
C25
SUS_STAT#(PWM_GPIO5)
D12
GREEN(DFT_GPIO1)
E18
BLUE(DFT_GPIO3)
E19
DAC_VSYNC(PWM_GPIO6)
B11
DAC_HSYNC(PWM_GPIO4)
A11
DAC_RSET(PWM_GPIO1)
G14
AVDD1(NC)
F12
AVDD2(NC)
E12
REDb(NC)
G17
GREENb(NC)
F18
AVDDDI(NC)
F14
AVSSDI(NC)
G15
AVDDQ(NC)
H15
AVSSQ(NC)
H14
VDDLT18_2(NC)
B15
VDDLT33_1(NC)
A14
VDDLT33_2(NC)
B14
VSSLT1(VSS)
C14
VSSLT2(VSS)
D15
VDDLT18_1(NC)
A15
VSSLT3(VSS)
C16
VSSLT4(VSS)
C18
VSSLT5(VSS)
C20
LVDS_DIGON(PCE_TCALRP)
E9
LVDS_BLON(PCE_RCALRP)
F7
LVDS_ENA_BL(PWM_GPIO2)
G12
VSSLT6(VSS)
E20
VDDA18PCIEPLL1
D7
VDDA18PCIEPLL2
E7
BLUEb(NC)
F19
AUX_CAL(NC)
C8
GPPSB_REFCLKP(SB_REFCLKP)
V4
GPPSB_REFCLKN(SB_REFCLKN)
V3
DDC_DATA1/AUX1N(NC)
A7
DDC_CLK1/AUX1P(NC)
B7
DAC_SCL(PCE_RCALRN)
F8
DAC_SDA(PCE_TCALRN)
E8
REFCLK_N(PWM_GPIO3)
F11
VSSLT7(VSS)
C22
RSVD
G11
C153
2.2U_0603_6.3V4Z
C153
2.2U_0603_6.3V4Z
1
2
L5
BLM18PG121SN1D_0603
L5
BLM18PG121SN1D_0603
1 2
C142
2.2U_0603_6.3V4Z
C142
2.2U_0603_6.3V4Z
1
2
R366 1K_0402_1%R366 1K_0402_1%
1 2
L2
BLM18PG121SN1D_0603
L2
BLM18PG121SN1D_0603
1 2
C146
2.2U_0603_6.3V4Z
C146
2.2U_0603_6.3V4Z
1
2
R69 4.7K_0402_5%R69 4.7K_0402_5%
1 2
R76 0_0402_5%R76 0_0402_5%
1 2
C148
2.2U_0603_6.3V4Z
C148
2.2U_0603_6.3V4Z
1
2
L6
BLM18PG121SN1D_0603
L6
BLM18PG121SN1D_0603
1 2
R88 150_0402_1%R88 150_0402_1%
1 2
R84 1.8K_0402_5%R84 1.8K_0402_5%
1 2
2
2
1
1
B B
A A
+1.8VS
+1.1VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
13 42Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
13 42Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401870
B
SCHEMATIC,MB A6053
Custom
13 42Wednesday, May 19, 2010
2009-02-12 2009-02-12
Compal Electronics, Inc.
SBD_MEM/DVO_I/F
PAR 4 OF 6
U3D
RS780M_FCBGA528880MR1@
SBD_MEM/DVO_I/F
PAR 4 OF 6
U3D
RS780M_FCBGA528880MR1@
MEM_A0(NC)
AB12
MEM_A1(NC)
AE16
MEM_A2(NC)
V11
MEM_A3(NC)
AE15
MEM_A4(NC)
AA12
MEM_A5(NC)
AB16
MEM_A6(NC)
AB14
MEM_A7(NC)
AD14
MEM_A8(NC)
AD13
MEM_A9(NC)
AD15
MEM_A10(NC)
AC16
MEM_A11(NC)
AE13
MEM_A12(NC)
AC14
MEM_A13(NC)
Y14
MEM_BA0(NC)
AD16
MEM_BA1(NC)
AE17
MEM_BA2(NC)
AD17
MEM_RASb(NC)
W12
MEM_CASb(NC)
Y12
MEM_WEb(NC)
AD18
MEM_CSb(NC)
AB13
MEM_CKE(NC)
AB18
MEM_ODT(NC)
V14
MEM_CKP(NC)
V15
MEM_CKN(NC)
W14
MEM_DM0(NC)
W17
MEM_DM1/DVO_D8(NC)
AE19
MEM_DQS0P/DVO_IDCKP(NC)
Y17
MEM_DQS0N/DVO_IDCKN(NC)
W18
MEM_DQS1P(NC)
AD20
MEM_DQS1N(NC)
AE21
MEM_DQ0/DVO_VSYNC(NC)
AA18
MEM_DQ1/DVO_HSYNC(NC)
AA20
MEM_DQ2/DVO_DE(NC)
AA19
MEM_DQ3/DVO_D0(NC)
Y19
MEM_DQ4(NC)
V17
MEM_DQ5/DVO_D1(NC)
AA17
MEM_DQ6/DVO_D2(NC)
AA15
MEM_DQ7/DVO_D4(NC)
Y15
MEM_DQ8/DVO_D3(NC)
AC20
MEM_DQ9/DVO_D5(NC)
AD19
MEM_DQ10/DVO_D6(NC)
AE22
MEM_DQ11/DVO_D7(NC)
AC18
MEM_DQ12(NC)
AB20
MEM_DQ13/DVO_D9(NC)
AD22
MEM_DQ14/DVO_D10(NC)
AC22
MEM_DQ15/DVO_D11(NC)
AD21
MEM_COMPP(NC)
AE12
MEM_COMPN(NC)
AD12
MEM_VREF(NC)
AE18
IOPLLVDD18(NC)
AE23
IOPLLVSS(NC)
AD23
IOPLLVDD(NC)
AE24
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