How it Works
show menu
Compal
Loading...
LA-4971P 10AR
Schematic
46 pgs2.32 Mb0

Compal LA-4971P 10AR, Satellite A500, Satellite L500, Satellite L505, Satellite L500D Schematic

...
0 (0)
A
1 1
B
C
D
E
Compal confidential
2 2
Liverpool 10AR/10ARG
KSWAE LA-4971P Schematics Document
Mobile AMD S1G2 S1G3/ RS780MN & RS780MC & RX781 & RS880 /
3 3
SB700 & SB710
2009-02-09 Rev. 0.3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-4971P
LA-4971P
LA-4971P
1 45Wednesday, February 25, 2009
1 45Wednesday, February 25, 2009
1 45Wednesday, February 25, 2009
E
0.1
0.1
0.1
A
Compal Confidential
M o d e l N a m e : K S W A E
M o d e l N a m e : K S W A E
M o d e l N a m e : K S W A EM o d e l N a m e : K S W A E
F i l e N a m e : L A - 4 9 7 1 P
F i l e N a m e : L A - 4 9 7 1 P
F i l e N a m e : L A - 4 9 7 1 PF i l e N a m e : L A - 4 9 7 1 P
G r i f f i n P l a t f o r m
G r i f f i n P l a t f o r m
G r i f f i n P l a t f o r mG r i f f i n P l a t f o r m
1 1
H D M I C E C C o n t r o l l e r
H D M I C E C C o n t r o l l e r
H D M I C E C C o n t r o l l e rH D M I C E C C o n t r o l l e r
EC SMBUS
2 2
R T L 8 1 0 3 E L L A N 1 0 / 1 0 0 M
R T L 8 1 0 3 E L L A N 1 0 / 1 0 0 M
R T L 8 1 0 3 E L L A N 1 0 / 1 0 0 MR T L 8 1 0 3 E L L A N 1 0 / 1 0 0 M
PCIe port 3
3 3
C l o c k G e n e r a t o r
C l o c k G e n e r a t o r
C l o c k G e n e r a t o rC l o c k G e n e r a t o r
SLG8SP626VTR
R T C C K T .
R T C C K T .
R T C C K T .R T C C K T .
P o w e r O n / O f f C K T .
P o w e r O n / O f f C K T .
P o w e r O n / O f f C K T .P o w e r O n / O f f C K T .
D C / D C I n t e r f a c e C K T .
D C / D C I n t e r f a c e C K T .
D C / D C I n t e r f a c e C K T .D C / D C I n t e r f a c e C K T .
P o w e r C i r c u i t D C / D C
P o w e r C i r c u i t D C / D C
P o w e r C i r c u i t D C / D CP o w e r C i r c u i t D C / D C
page 37,38,39,40
4 4
41,42,43,44
R J 4 5
R J 4 5
R J 4 5R J 4 5
page 26
page 15
page 37
page 35
page 36
R5F211A4SP
page 26
U S B / B
U S B / B
U S B / BU S B / B
page 32
P o w e r / B
P o w e r / B
P o w e r / BP o w e r / B
page 35
S W / B
S W / B
S W / BS W / B
page 35
page 18
P C I e M i n i C a r d W L A N
P C I e M i n i C a r d W L A N
P C I e M i n i C a r d W L A NP C I e M i n i C a r d W L A N
PCIe Port 2
page 27
B
A T I M 9 2 / 9 6
A T I M 9 2 / 9 6
A T I M 9 2 / 9 6A T I M 9 2 / 9 6
with VRAM
V G A M X M C o n n
V G A M X M C o n n
V G A M X M C o n nV G A M X M C o n n
C R T
C R T
C R T C R T
page 16
L C D C o n n .
L C D C o n n .
L C D C o n n .L C D C o n n .
page 17
H D M I C o n n .
H D M I C o n n .
H D M I C o n n .H D M I C o n n .
page 18
PCIe 4x
N E W C a r d
N E W C a r d
N E W C a r dN E W C a r d
USB port 11
PCIe port 0
e S A T A
e S A T A
e S A T Ae S A T A
USB port 2
SATA port 2
C a r d B u s C o n t r o l l e r
C a r d B u s C o n t r o l l e r
C a r d B u s C o n t r o l l e rC a r d B u s C o n t r o l l e r
OZ601
D e b u g P o r t
D e b u g P o r t
D e b u g P o r tD e b u g P o r t
page 33
G s e n s o r
G s e n s o r
G s e n s o rG s e n s o r
page 35
Page 19
1.5V 2.5GHz(250MB/s)
page 27
page 25
page 28
E N E K B 9 2 6 D 2
E N E K B 9 2 6 D 2
E N E K B 9 2 6 D 2E N E K B 9 2 6 D 2
T o u c h P a d
T o u c h P a d
T o u c h P a dT o u c h P a d
page 35
C
H y p e r T r a n s p o r t L i n k 2 . 6 G H z
H y p e r T r a n s p o r t L i n k 2 . 6 G H z
H y p e r T r a n s p o r t L i n k 2 . 6 G H zH y p e r T r a n s p o r t L i n k 2 . 6 G H z
1 6 X 1 6
1 6 X 1 6
1 6 X 1 61 6 X 1 6
A - L i n k E x p r e s s I I
A - L i n k E x p r e s s I I
A - L i n k E x p r e s s I IA - L i n k E x p r e s s I I 4 X P C I - E
4 X P C I - E
4 X P C I - E4 X P C I - E
5V 480MHzUSB
SATA 5V 1.5GHz(150MB/s)
5V 480MHzUSB
PCI BUS
3.3V 33 MHz
LPC BUS
3.3V 33 MHz
page 34
I n t . K B D
I n t . K B D
I n t . K B DI n t . K B D
page 33
S P I R O M
S P I R O M
S P I R O MS P I R O M
A M D S 1 G 2 C P U
A M D S 1 G 2 C P U
A M D S 1 G 2 C P UA M D S 1 G 2 C P U
uFCPGA-638 Package
page 4,5,6,7
A T I
A T I
A T IA T I
RS780MN
RS780MC
RX781
RS880
page 10,11,12,13,14
A T I
A T I
A T IA T I
SB700 SB710
page 20,21,22,23,24
page 33
HD Audio
ADM1032ARMZ
R i g h t U S B C o n n
R i g h t U S B C o n n
R i g h t U S B C o n nR i g h t U S B C o n n
USB Port 0,1
USB 5x
5V 480MHz
USBPort 8
SATA
5V 1.5GHz(150MB/s)
SATA
5V 1.5GHz(150MB/s)
3.3V 24.576MHz/48Mhz
M D C 1 . 5
M D C 1 . 5
M D C 1 . 5 M D C 1 . 5
page 33
R J 1 1
R J 1 1
R J 1 1R J 1 1
page 33
TPA6017
D
T h e r m a l S e n s o r
T h e r m a l S e n s o r F a n C o n t r o l
T h e r m a l S e n s o rT h e r m a l S e n s o r
page 6
2 0 0 p i n D D R I I - S O - D I M M X 2
2 0 0 p i n D D R I I - S O - D I M M X 2
2 0 0 p i n D D R I I - S O - D I M M X 22 0 0 p i n D D R I I - S O - D I M M X 2
BANK 0, 1, 2, 3
M e m o r y B U S ( D D R I I )
M e m o r y B U S ( D D R I I )
M e m o r y B U S ( D D R I I )M e m o r y B U S ( D D R I I ) D u a l C h a n n e l
D u a l C h a n n e l
D u a l C h a n n e lD u a l C h a n n e l 1 . 8 V D D R I I 6 6 7 / 8 0 0 M H Z
1 . 8 V D D R I I 6 6 7 / 8 0 0 M H Z
1 . 8 V D D R I I 6 6 7 / 8 0 0 M H Z1 . 8 V D D R I I 6 6 7 / 8 0 0 M H Z
I n t . C a m e r a
I n t . C a m e r a
I n t . C a m e r aI n t . C a m e r a
page 32
W L A N
W L A N
W L A NW L A N
page 27
A M P L I F I E R
A M P L I F I E R
A M P L I F I E RA M P L I F I E R
page 31
S P K C O N N
S P K C O N N
S P K C O N NS P K C O N N
page 31
USBPort 9
USBPort 7
S A T A H D D 1
S A T A H D D 1
S A T A H D D 1S A T A H D D 1
SATA port 0
S A T A O D D
S A T A O D D
S A T A O D DS A T A O D D
SATA port 3
H D A C o d e c
H D A C o d e c
H D A C o d e cH D A C o d e c
ALC272
M I C C O N N
M I C C O N N
M I C C O N NM I C C O N N
F i n g e r P r i n t e r
F i n g e r P r i n t e r
F i n g e r P r i n t e rF i n g e r P r i n t e r
page 25
page 25
page 30
page 31
F a n C o n t r o l
F a n C o n t r o lF a n C o n t r o l
APL5607KI-TRG
page 8,9
page 32
page 27
I n t . M I C
I n t . M I C
I n t . M I C I n t . M I C
page 31
USBPort 6
USBPort 4
R T S 5 1 5 9 E
R T S 5 1 5 9 E
R T S 5 1 5 9 ER T S 5 1 5 9 E
page 4
B l u e t o o t h
B l u e t o o t h
B l u e t o o t hB l u e t o o t h
page 32
page 29
H P C O N N
H P C O N N
H P C O N NH P C O N N
page 31
3IN1
E
3IN1
page 29
V o l u m e C o n t r o l
V o l u m e C o n t r o l
V o l u m e C o n t r o lV o l u m e C o n t r o l
page 31
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
LA-4971P
LA-4971P
LA-4971P
2 45Wednesday, February 25, 2009
2 45Wednesday, February 25, 2009
2 45Wednesday, February 25, 2009
E
0.1
0.1
0.1
A
Voltage Rails
O : ON
X : OFF
+5VS
1 1
2 2
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
State
S0
S1
S3
S5 S4/AC
power plane
+B
+3VL
+5VL
+RTCVCC
O
O
O
O
O
X
+3VALW
+1.2VALW
+3V_LAN
O
O
O
O
X
X X X
+3VS
+2.5VS
+1.8VS
+1.5VS
+1.1VS
+1.8V+5VALW
+VGA_CORE
+0.9V
+1.2V_HT
+0.9V
+CPU_CORE_NB
+CPU_CORE_0
+CPU_CORE_1
O
X X
X
OO
OO
X
X
I2C / SMBUS ADDRESSING
DEVICE
DDR SO-DIMM 0
3 3
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
HEX
A0
D2
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0
EC SM Bus1 address
Device Address
Smart Battery
HDMI-CEC 34H
EC KB926D2
HEX
16H
0001 011X b
0011 010X b
B
Symbol Note :
: Digital Ground
: Analog Ground
@ : just reserve , no build
DEBUG@ : reserve for debug.
Layout Notes
L
UMA@: means for RS780M.
BTO (Build-To-Order) Option Table
Function
Description
Explain
BTO
Function
Description
Explain
BTO
Express card / PCMCIA
( E / A )
EXPCARD@ / PCMCIA@
FingerPrinter
( F )
FP@
CAMERA & MIC
CAMERA MIC
CAM@ MIC@
SMBUS Control Table
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
I2C_CLK
I2C_DATA
DDC_CLK0
DDC_DATA0
DDC_CLK1
DDC_DATA1
SCL0
SDA0
SCL1
SDA1
SCL2
SDA2
SCL3
SDA3
C
BLUE TOOTH
(X)
( B )
BT@
RJ11
( R )
MDC@
AMD(UMA)
IHDMI@
SOURCE
KB926
KB926
RS780M
RS780M
RS780M
SB700
SB700
SB700
SB700
SSD
( S )
SSD@
HDMI
(Y)
ATI VGA/B
HDMI@
SATA ODD
16" 17"
16inch@
COMMON
H@
BATTINVERTER
VVV
Platform
PUMA@
Platform
TIGRIS@
17inch@
LVDS wireset
Cost down
LVDSSET@
HDMI CEC
D
GM@
GM@
PM@+GPM@
PM@+PM1@ SB700
Item CPU SB
GM@
GM@
PM@+GPM@
PM@+PM1@ SB710
WiFi
( H )
Half - size
WLAN@ WIMAX@
DC-IN
16inch_45@ 17inch_45@
CPU
THERMAL
SENSOR
SODIMM
I / II
NB
S1G2
RS780MC NA
S1G2
RS780MN
S1G2
S1G2
RX781
NB
S1G3
RS880MC NA
S1G3
RS880M
S1G3
S1G3
RX881
G- sensor
First Second
G@ + G_1st@ G@ + G_2nd@
CHIPSET
PUMA@ TIGRIS@
WLAN
LCD DDC ROM
CLK GEN
V
VV
V
VGA
NA
MXMRS780MN
MXM
VGA
NA
MXMRS880M
MXM
HDMI DDC ROM
V
E
SB700
SB700
SB700
SB710
SB710
SB710
3 in 1 card reader
NEW CARD
V
CommentItem CPU SB
Comment
RTS5159
CARD@
MXM Thermal Sensor
V
4 4
EC SM Bus2 address
Device
ADI1032-1 CPU
ADI1032-2 VGA
EC KB926D2
Ext. VGA/B
CS/B
HEX Address
1001 100X b
98H
1001 101X b
9AH
A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
LA-4971P
LA-4971P
LA-4971P
3 45Wednesday, February 25, 2009
3 45Wednesday, February 25, 2009
3 45Wednesday, February 25, 2009
E
0.1
0.1
0.1
A
B
C
D
E
< C1, C2 and C7 must be replaced to 10-uF for Caspian compatibility >
+1.2V_HT
Near CPU SocketVLDT CAP.
250 mil
1
PUMA@
PUMA@
C1
C1
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1 1
2
TIGRIS@
TIGRIS@
C1
C1 10U_0805_10V6K
10U_0805_10V6K
1
PUMA@
PUMA@
C2
C2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
TIGRIS@
TIGRIS@
C2
C2 10U_0805_10V6K
10U_0805_10V6K
1
C3
C3
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C4
C4
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C5
C5
180P_0402_50V8J
180P_0402_50V8J
2
1
C6
C6
180P_0402_50V8J
180P_0402_50V8J
2
H_CADIP[0..15]10
2 2
3 3
H_CADIP[0..15]
H_CADIN[0..15]
VLDT=500mA
H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15
H_CLKIP010 H_CLKIN010 H_CLKIP110 H_CLKIN110
H_CTLIP010 H_CTLIN010 H_CTLIP110 H_CTLIN110
+1.2V_HT
JCPUA
JCPUA
D1 D2 D3 D4
E3 E2 E1
F1 G3 G2 G1 H1
J1 K1 L3 L2 L1
M1 N3 N2
E5 F5 F3 F4
G5 H5 H3 H4
K3 K4 L5
M5 M3 M4 N5
P5
J3
J2
J5 K5
N1
P1 P3 P4
6090022100G_B@
6090022100G_B@
VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3
L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15
L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1
L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1
HT LINK
HT LINK
VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
H_CADOP[0..15]
H_CADON[0..15]
+VLDT_B
AE2 AE3 AE4 AE5
H_CADOP0
AD1
H_CADON0
AC1
H_CADOP1
AC2
H_CADON1
AC3
H_CADOP2
AB1
H_CADON2
AA1
H_CADOP3
AA2
H_CADON3
AA3
H_CADOP4
W2
H_CADON4
W3
H_CADOP5
V1
H_CADON5
U1
H_CADOP6
U2
H_CADON6
U3
H_CADOP7
T1
H_CADON7
R1
H_CADOP8
AD4
H_CADON8
AD3
H_CADOP9
AD5
H_CADON9
AC5
H_CADOP10
AB4
H_CADON10
AB3
H_CADOP11
AB5
H_CADON11
AA5
H_CADOP12
Y5
H_CADON12
W5
H_CADOP13
V4
H_CADON13
V3
H_CADOP14
V5
H_CADON14
U5
H_CADOP15
T4
H_CADON15
T3
Y1 W1 Y4 Y3
R2 R3 T5 R5
1 2
< To NB >< From NB >
H_CLKOP0 10 H_CLKON0 10 H_CLKOP1 10 H_CLKON1 10
H_CTLOP0 10 H_CTLON0 10 H_CTLOP1 10 H_CTLON1 10
H_CADOP[0..15] 10
H_CADON[0..15] 10H_CADIN[0..15]10
PUMA@
PUMA@
C7
C7
4.7U_0805_10V4Z
4.7U_0805_10V4Z
TIGRIS@
TIGRIS@
C7
C7 10U_0805_10V6K
10U_0805_10V6K
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS
1A
12
D1
D1
@
@
GND GND GND GND
C183
C183
2
1
8 7 6 5
B
12
@
@
1SS355_SOD323-2
1SS355_SOD323-2
D2
D2
BAS16_SOT23-3
BAS16_SOT23-3
JFAN
JFAN
+FAN1
1
1
2
2
C
3
3
4
GND
5
GND
ACES_85204-0300N
ACES_85204-0300N
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2
C9
C9
@
@
1000P_0402_25V8J
1000P_0402_25V8J
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+3VS
12
R12
R12
10K_0402_5%
10K_0402_5%
2
C8
C8
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
1
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
FAN_SPEED1 34
D
< To EC >
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
AMD CPU S1G2 HT I/F
AMD CPU S1G2 HT I/F
AMD CPU S1G2 HT I/F
LA-4971P
LA-4971P
LA-4971P
4 45Wednesday, February 25, 2009
4 45Wednesday, February 25, 2009
4 45Wednesday, February 25, 2009
E
0.1
0.1
0.1
+FAN1
1
C192
C192
10U_0805_10V4Z
10U_0805_10V4Z
2
< From EC >
4 4
EN_DFAN134
A
10U_0805_10V4Z
10U_0805_10V4Z
U6
U6
1
EN
2
VIN
3
VOUT
4
VSET
APL5607KI-TRG_SO8
APL5607KI-TRG_SO8
A
< DDR2 VREF is 0.5 ratio >
+1.8V
R1
R1
1K_0402_1%
1K_0402_1%
1 2
R2
R2
1 1
1K_0402_1%
1K_0402_1%
1 2
2 2
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
3 3
< To SO_DIMMA >
< To SO_DIMMA >
+MCH_REF
1
C12
C12
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C13
C13
1000P_0402_25V8J
1000P_0402_25V8J
2
Place them close to CPU within 1"
R4 39.2_0402_1%R4 39.2_0402_1%
1 2
R3 39.2_0402_1%R3 39.2_0402_1%
+1.8V
1 2
T2 PADT2 PAD
DDR_A_ODT09 DDR_A_ODT19
DDR_CS0_DIMMA#9 DDR_CS1_DIMMA#9 DDR_CS0_DIMMB# 8
DDR_CKE0_DIMMA9 DDR_CKE1_DIMMA9
DDR_A_CLK09 DDR_A_CLK#09 DDR_A_CLK19 DDR_A_CLK#19
DDR_A_MA[15..0]9
DDR_A_BS#09 DDR_A_BS#19 DDR_A_BS#29
DDR_A_RAS#9 DDR_A_CAS#9 DDR_A_WE#9
< PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH >
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
MEM_P MEM_N VTT_SENSE
DDR_A_ODT0 DDR_A_ODT1
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB#
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
1
C10
C10
1.5P_0402_50V9C
1.5P_0402_50V9C
2
1
C11
C11
1.5P_0402_50V9C
1.5P_0402_50V9C
2
JCPUB
JCPUB
D10
VTT1
C10
VTT2
B10
VTT3
AD10
VTT4
AF10
MEMZP
AE10
MEMZN
H16
RSVD_M1
T19
MA0_ODT0
V22
MA0_ODT1
U21
MA1_ODT0
V19
MA1_ODT1
T20
MA0_CS_L0
U19
MA0_CS_L1
U20
MA1_CS_L0
V20
MA1_CS_L1
J22
MA_CKE0
J20
MA_CKE1
N19
MA_CLK_H0
N20
MA_CLK_L0
E16
MA_CLK_H1
F16
MA_CLK_L1
Y16
MA_CLK_H2
AA16
MA_CLK_L2
P19
MA_CLK_H3
P20
MA_CLK_L3
N21
MA_ADD0
M20
MA_ADD1
N22
MA_ADD2
M19
MA_ADD3
M22
MA_ADD4
L20
MA_ADD5
M24
MA_ADD6
L21
MA_ADD7
L19
MA_ADD8
K22
MA_ADD9
R21
MA_ADD10
L22
MA_ADD11
K20
MA_ADD12
V24
MA_ADD13
K24
MA_ADD14
K19
MA_ADD15
R20
MA_BANK0
R23
MA_BANK1
J21
MA_BANK2
R19
MA_RAS_L
T22
MA_CAS_L
T24
MA_WE_L
@ 6090022100G_B
@ 6090022100G_B
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
B
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
VTT5 VTT6 VTT7 VTT8 VTT9
VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0 MB0_ODT1 MB1_ODT0
MB0_CS_L0 MB0_CS_L1 MB1_CS_L0
MB_CKE0 MB_CKE1
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8
MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15
MB_BANK0 MB_BANK1 MB_BANK2
MB_RAS_L MB_CAS_L
MB_WE_L
W10 AC10 AB10 AA10 A10
Y10
W17
B18
W26 W23 Y26
V26 W25 U22
J25 H26
P22 R22 A17 A18 AF18 AF17 R26 R25
P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24
R24 U26 J26
U25 U24 U23
1
2
1
2
+0.9V+0.9V
C14
C14
1.5P_0402_50V9C
1.5P_0402_50V9C
C15
C15
1.5P_0402_50V9C
1.5P_0402_50V9C
+MCH_REF
DDR_B_ODT0 DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_CKE0_DIMMB DDR_CKE1_DIMMB
DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1DDR_A_CLK#1
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15
DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2
DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
< VTT regulator voltage >
T1PAD T1PAD
T3PAD T3PAD
DDR_B_ODT0 8 DDR_B_ODT1 8
DDR_CS1_DIMMB# 8
DDR_CKE0_DIMMB 8 DDR_CKE1_DIMMB 8
DDR_B_CLK0 8 DDR_B_CLK#0 8 DDR_B_CLK1 8 DDR_B_CLK#1 8
DDR_B_MA[15..0] 8
DDR_B_BS#0 8 DDR_B_BS#1 8 DDR_B_BS#2 8
DDR_B_RAS# 8 DDR_B_CAS# 8 DDR_B_WE# 8
C
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
D
E
< Processor DDR2 Memory Interface >
JCPUC
AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11
AE14 AF14 AF11 AD11
AB26 AE22 AC16 AD12
AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12
C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24
Y11
A12 B16 A22 E25
C12 B12 D16 C16 A24 A23 F26 E26
JCPUC
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7
MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7
6090022100G_B@
6090022100G_B@
MEM:DATA
MEM:DATA
MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8
MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63
MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12
E12 C15 E19 F24 AC24 Y19 AB16 Y13
G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9
DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7
DDR_A_D[63..0] 9
< From/To SO_DIMMA >
DDR_A_DQS0 9 DDR_A_DQS#0 9 DDR_A_DQS1 9 DDR_A_DQS#1 9 DDR_A_DQS2 9 DDR_A_DQS#2 9 DDR_A_DQS3 9 DDR_A_DQS#3 9 DDR_A_DQS4 9 DDR_A_DQS#4 9 DDR_A_DQS5 9 DDR_A_DQS#5 9 DDR_A_DQS6 9 DDR_A_DQS#6 9 DDR_A_DQS7 9 DDR_A_DQS#7 9
DDR_B_D[63..0]8
< From/To SO_DIMMB >
DDR_B_DM[7..0]8 DDR_A_DM[7..0] 9
< To SO_DIMMB > < To SO_DIMMA >
DDR_B_DQS08 DDR_B_DQS#08 DDR_B_DQS18 DDR_B_DQS#18 DDR_B_DQS28 DDR_B_DQS#28 DDR_B_DQS38 DDR_B_DQS#38 DDR_B_DQS48 DDR_B_DQS#48 DDR_B_DQS58 DDR_B_DQS#58 DDR_B_DQS68 DDR_B_DQS#68 DDR_B_DQS78 DDR_B_DQS#78
< From/To SO_DIMMB > < From/To SO_DIMMA >
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
AMD CPU S1G2 DDRII I/F
AMD CPU S1G2 DDRII I/F
AMD CPU S1G2 DDRII I/F
LA-4971P
LA-4971P
LA-4971P
5 45Wednesday, February 25, 2009
5 45Wednesday, February 25, 2009
5 45Wednesday, February 25, 2009
E
0.1
0.1
0.1
A
+CPU_CORE_0
+CPU_CORE_1
1 1
< Close to CPU >
1 2
1 2
1 2
1 2
R487
R487 10_0402_5%
10_0402_5%
R486
R486 10_0402_5%
10_0402_5%
Un-Mount R489 For Caspian
R489
R489 10_0402_5%PUMA@
10_0402_5%PUMA@
R488
R488 10_0402_5%PUMA@
10_0402_5%PUMA@
CPU_VDD0_RUN_FB_H
CPU_VDD0_RUN_FB_L
CPU_VDD1_RUN_FB_H
CPU_VDD1_RUN_FB_L
Change R488 to 10K For Caspian
< 200-MHz PLL Reference Clock >
CLK_CPU_BCLK15
CLK_CPU_BCLK#15
Address:100_1100 Place close to CPU wihtin 1.5"
< Filtered PLL Supply Voltage >
2 2
L1 FBM_L11_201209_300L_0805L1 FBM_L11_201209_300L_0805
1 2
1
+
C16
@+C16
@
100U_D2_10VM
100U_D2_10VM
2
C20
C20 3900P_0402_50V7K
3900P_0402_50V7K
1 2
C21
C21 3900P_0402_50V7K
3900P_0402_50V7K
1 2
1
C17
C17
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
12
R8
R8
169_0402_1%
169_0402_1%
VDDA=300mA
1
C18
C18
3300P_0402_50V7K
3300P_0402_50V7K
2
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
+2.5VDDA+2.5VS
1
C19
C19
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
+2.5VDDA
B
< Differential feedback for VDDNB >
+VDDNB
12
12
< Sideband-Temperature Sensor Interface Clock & Data>
< Sideband-Temperature Sensor Interface interrupt >
< Compensation Resistor to VSS >
< Compensation Resistor to VLDT >
R484
R484 10_0402_5%
10_0402_5%
R485
R485 10_0402_5%
10_0402_5%
Close to CPU
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
+1.2V_HT
R13 44.2_0402_1%R13 44.2_0402_1%
1 2
R14 44.2_0402_1%R14 44.2_0402_1%
1 2
CPU_VDD0_RUN_FB_H43 CPU_VDD0_RUN_FB_L43
CPU_VDD1_RUN_FB_H43 CPU_VDD1_RUN_FB_L43
< Debug ready >
< JTAG debug port >
T9 PADT9 PAD T10 PADT10 PAD T11 PADT11 PAD T12 PADT12 PAD T19 PADT19 PAD
C
+2.5VDDA
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
LDT_RST# H_PWRGD LDT_STOP# CPU_LDT_REQ_R#
CPU_HTREF0 CPU_HTREF1
CPU_VDD0_RUN_FB_H CPU_VDD0_RUN_FB_L
CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_L
CPU_TEST23_TSTUPD
CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L
CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1
1 2
R25
R25 0_0402_5%
0_0402_5%
F10
C6
AF4 AF5
AE6
R6
AB6
G10 AA9 AC9 AD9 AF9
AD7
H10
G9
AB8 AF7 AE7 AE8 AC8 AF8
C2
AA6
C1
F8 F9
A9 A8
B7 A7
P6
F6 E6
Y6
E9 E8
A3 A5 B3 B5
JCPUD
JCPUD
VDDA1 VDDA2
CLKIN_H CLKIN_L
RESET_L PWROK LDTSTOP_L LDTREQ_L
SIC SID ALERT_L
HT_REF0 HT_REF1
VDD0_FB_H VDD0_FB_L
VDD1_FB_H VDD1_FB_L
DBRDY TMS TCK TRST_L TDI
TEST23
TEST18 TEST19
TEST25_H TEST25_L
TEST21 TEST20 TEST24 TEST22 TEST12 TEST27
TEST9 TEST6
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5
6090022100G_B@
6090022100G_B@
KEY1 KEY2
SVC SVD
THERMTRIP_L
PROCHOT_L
MEMHOT_L
THERMDC
THERMDA
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
DBREQ_L
TDO
TEST28_H
TEST28_L
TEST17 TEST16 TEST15 TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
RSVD10
RSVD9 RSVD8 RSVD7 RSVD6
D
M11 W18
CPU_SVC
A6
CPU_SVD
A4
CPU_THERMTRIP#_R
AF6
CPU_PROCHOT#_1.8
AC7 AA8
THERMDC_CPU
W7
THERMDA_CPU
W8
+1.8V sense no support
W9 Y9
CPU_VDDNB_RUN_FB_H
H6
CPU_VDDNB_RUN_FB_L
G6
CPU_DBREQ#
E10
AE9
CPU_TEST28_H_PLLCHRZ_P
J7
CPU_TEST28_L_PLLCHRZ_N
H8
CPU_TEST17_BP3
D7
CPU_TEST16_BP2
E7 F7 C7
C3
CPU_TEST10_ANALOGOUT
K8
C4
CPU_TEST29_H_FBCLKOUT_P
C9
CPU_TEST29_L_FBCLKOUT_N
C8
H18 H19 AA7 D5 C5
R42
R42
12
300_0402_5%
300_0402_5%
CPU_SVC 43 CPU_SVD 43
+1.8V
T22PAD T22PAD T21PAD T21PAD
CPU_VDDNB_RUN_FB_H 43 CPU_VDDNB_RUN_FB_L 43
T20PAD T20PAD
T5PAD T5PAD T6PAD T6PAD
T7PAD T7PAD T8PAD T8PAD
R32
@R32
@
300_0402_5%
300_0402_5%
12
Add R32 at PVT
T13PAD T13PAD T14PAD T14PAD
E
< Serial VID Interface clock & data >
< Thermal Sensor Trip output > < HTC-active state indication or command >
< Thermal diode cathode & anode >
< Differential feedback for VDDIO > < VDDIO : DDR SDRAM I/O ring power supply> < Differential feedback for VDDNB > < Northbridge power supply >
< Debug request >
route as differential as short as possible testpoint under package
+1.2V_HT
< Serial VID Interface clock & data >
+1.8VS
3 3
LDT_RST#20
H_PWRGD20,43
4 4
CPU_LDT_REQ#11,20
0718 AMD --> 1K ohm
R22
R22 1K_0402_5%
1K_0402_5%
12
R23
R23 1K_0402_5%
1K_0402_5%
12
+1.8VS
R15
R15
300_0402_5%
300_0402_5%
1 2
LDT_RST#
1
C22
C22
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
+1.8VS +1.8VS
R21
R21
300_0402_5%
300_0402_5%
1 2
H_PWRGD LDT_STOP#
1
C23
C23
0.1U_0402_16V7K
0.1U_0402_16V7K
2
300_0402_5%
300_0402_5%
CPU_LDT_REQ#
0.01U_0402_25V7K
0.01U_0402_25V7K
A
CPU_SVC
CPU_SVD
LDT_STOP#11,20
+1.8VS
R30
R30
1 2
1 2
1
C24
C24
@
@
2
R36
R36
300_0402_5%
300_0402_5%
1 2
1
C25
C25
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
PUMA@
PUMA@
R27
R27
CPU_LDT_REQ_R#
0_0402_5%
0_0402_5%
Un-Mount R27 For Caspian
Add R497 and R498 at PVT
R497
R497 510_0402_5%TIGRIS@
510_0402_5%TIGRIS@
R499
R499 510_0402_5%@
510_0402_5%@
R10
R10 10K_0402_5%
10K_0402_5%
R5
R5 300_0402_5%
300_0402_5%
R9
R9 300_0402_5%
300_0402_5%
+1.8V
CPU_THERMTRIP#_R
1 2
+1.8V
CPU_PROCHOT#_1.8
1 2
1 2
1 2
1 2
Add R29 and R31 at PVT
TIGRIS@
TIGRIS@
R31
1 2
1 2
B
R31 300_0402_5%
300_0402_5%
12
TIGRIS@
TIGRIS@
R29
R29 300_0402_5%
300_0402_5%
R26
R26 300_0402_5%
300_0402_5%
12
R28
R28 300_0402_5%
300_0402_5%
CPU_TEST20_SCANCLK2
CPU_TEST23_TSTUPD
CPU_TEST21_SCANEN
CPU_TEST24_SCANCLK1
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
B
B
2
Q3
Q3
E
E
3 1
C
C
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
R11
@ R11
@
0_0402_5%
0_0402_5%
1 2
+1.8V
R498
R498 510_0402_5%@
510_0402_5%@
1 2
R500
R500 510_0402_5%TIGRIS@
510_0402_5%TIGRIS@
1 2
D12
D12 CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
21
< To power circuitry>
ENTRIP2 38,40
< R41 Close to CPU >
C26
C26
CPU_DBREQ#
R41 300_0402_5%R41 300_0402_5%
+1.8V
T23 PADT23 PAD
+1.8V
T24 PADT24 PAD
+3VS
1
1 2
2
< noise filter cap >
D
1 2
R40 220_0402_5%@ R40 220_0402_5%@
1 2
R39 220_0402_5%@ R39 220_0402_5%@
1 2
R38 220_0402_5%@ R38 220_0402_5%@
1 2
R37 220_0402_5%@ R37 220_0402_5%@
1 2
THERMDA_CPU
THERMDC_CPU
C27
C27 2200P_0402_50V7K
2200P_0402_50V7K
D16
D16 CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
21
< To SB700 CPU block>
H_PROCHOT# 20
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
< To SB700 ACPI block>
H_THERMTRIP# 21
0.1U_0402_16V7K
0.1U_0402_16V7K
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
< HDT Connector >
JP3
< R494 Close to CPU >
R494
R494 0_0402_5%@
0_0402_5%@
1 2
+1.8V
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.
< Thermal Sensor >
U2
U2
1
VDD
2
D+
3
D-
THERM#4GND
ADM1032ARM-1 ZREEL_MSOP8
ADM1032ARM-1 ZREEL_MSOP8
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
8
SCLK
7
SDATA
6
ALERT#
5
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
AMD CPU S1G2 CTRL
AMD CPU S1G2 CTRL
AMD CPU S1G2 CTRL
JP3
1 3 5 7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423 26
SAMTEC_ASP-68200-07
@ SAMTEC_ASP-68200-07
@
EC_SMB_CK2
EC_SMB_DA2
LA-4971P
LA-4971P
LA-4971P
E
2 4 6 8
< From EC >
EC_SMB_CK2 19,34,35
EC_SMB_DA2 19,34,35
6 45Wednesday, February 25, 2009
6 45Wednesday, February 25, 2009
6 45Wednesday, February 25, 2009
LDT_RST#
0.1
0.1
0.1
A
VDD decoupling : +CPU_CORE
+CPU_CORE_0
1
+
+
C30
C30
330U_X_2VM_R6M
330U_X_2VM_R6M
2
Near CPU Socket
1 1
+CPU_CORE_1 +CPU_CORE_1 +CPU_CORE_1
1
+
+
C31
C31
330U_X_2VM_R6M
330U_X_2VM_R6M
2
Near CPU Socket
VDDIO decoupling : DDR SDRAM I/O ring power
+1.8V
1
C46
C46
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
+1.8V
2 2
1
C55
C55
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Between CPU Socket and DIMM
+1.8V
1
C60
C60
0.01U_0402_25V7K
0.01U_0402_25V7K
2
Between CPU Socket and DIMM
+1.8V
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
1
C62
C62
180P_0402_50V8J
180P_0402_50V8J
2
Between CPU Socket and DIMM
+1.8V
3 3
1
C74
C74
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Between CPU Socket and DIMM
+0.9V
VTT decoupling.
1
C66
C66
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Right side
+0.9V
1
C79
C79
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Left side
4 4
+VDDNB decoupling : Northbridge power
+VDDNB
1
C52
C52
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
+
+
2
1
+
+
2
1
C47
C47
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C56
C56
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C63
C63
180P_0402_50V8J
180P_0402_50V8J
2
1
C75
C75
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C67
C67
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C80
C80
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C53
C53
22U_0805_6.3V6M
22U_0805_6.3V6M
2
A
C28
C28
330U_X_2VM_R6M
330U_X_2VM_R6M
C29
C29
330U_X_2VM_R6M
330U_X_2VM_R6M
+CPU_CORE_0 +CPU_CORE_0
1
C32
C32
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C33
C33
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket Under CPU Socket
1
C36
C36
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C37
C37
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket Under CPU Socket
1
C48
C48
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C57
C57
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C61
C61
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C64
C64
180P_0402_50V8J
180P_0402_50V8J
2
1
C49
C49
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C58
C58
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C65
C65
180P_0402_50V8J
180P_0402_50V8J
2
1
C50
C50
180P_0402_50V8J
180P_0402_50V8J
2
Change to B2 size
1
C76
C76
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C68
C68
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C81
C81
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
TIGRIS@
TIGRIS@
1
C54
C54
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C77
C77
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C69
C69
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C82
C82
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
@+C78
@
1
C70
C70
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C83
C83 1000P_0402_25V8J
1000P_0402_25V8J
2
1
C34
C34
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C38
C38
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
+
C78 220U_B2_4VM_R45M
220U_B2_4VM_R45M
2
B
1
C51
C51
180P_0402_50V8J
180P_0402_50V8J
2
1
C71
C71
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C84
C84 1000P_0402_25V8J
1000P_0402_25V8J
2
B
1
C35
C35
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C39
C39
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C72
C72
180P_0402_50V8J
180P_0402_50V8J
2
1
C85
C85 180P_0402_50V8J
180P_0402_50V8J
2
1
C40
C40
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C43
C43
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
2
1
2
C
1
C41
C41
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C44
C44
0.01U_0402_25V7K
0.01U_0402_25V7K
2
C73
C73
180P_0402_50V8J
180P_0402_50V8J
C86
C86 180P_0402_50V8J
180P_0402_50V8J
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
2
1
2
+0.9V
1. Near Power Supply
1
2. Change to B2 size
+
+
C59
C59 220U_B2_4VM_R45M
220U_B2_4VM_R45M
2
C
C42
C42
180P_0402_50V8J
180P_0402_50V8J
C45
C45
180P_0402_50V8J
180P_0402_50V8J
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
+CPU_CORE_0
+VDDNB
+1.8V
D
AA11 AA13 AA15 AA17 AA19
AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21
AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23
JCPUE
JCPUE
G4
VDD0_1
H2
VDD0_2
J9
VDD0_3
J11
VDD0_4
J13
VDD0_5
J15
VDD0_6
K6
VDD0_7
K10
VDD0_8
K12
VDD0_9
K14
VDD0_10
L4
VDD0_11
L7
VDD0_12
L9
VDD0_13
L11
VDD0_14
L13
VDD0_15
L15
VDD0_16
M2
VDD0_17
M6
VDD0_18
M8
VDD0_19
M10
VDD0_20
N7
VDD0_21
N9
VDD0_22
N11
VDD0_23
K16
VDDNB_1
M16
VDDNB_2
P16
VDDNB_3
T16
VDDNB_4
V16
VDDNB_5
H25
VDDIO1
J17
VDDIO2
K18
VDDIO3
K21
VDDIO4
K23
VDDIO5
K25
VDDIO6
L17
VDDIO7
M18
VDDIO8
M21
VDDIO9
M23
VDDIO10
M25
VDDIO11
N17
VDDIO12
6090022100G_B@
6090022100G_B@
JCPUF
JCPUF
AA4
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17
AD6
VSS18
AD8
VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
6090022100G_B@
6090022100G_B@
+CPU_CORE_1
P8
VDD1_1
P10
VDD1_2
R4
VDD1_3
R7
VDD1_4
R9
VDD1_5
R11
VDD1_6
T2
VDD1_7
T6
VDD1_8
T8
VDD1_9
T10
VDD1_10
T12
VDD1_11
T14
VDD1_12
U7
VDD1_13
U9
VDD1_14
U11
VDD1_15
U13
VDD1_16
U15
VDD1_17
V6
VDD1_18
V8
VDD1_19
V10
VDD1_20
V12
VDD1_21
V14
VDD1_22
W4
VDD1_23
Y2
VDD1_24
AC4
VDD1_25 VDD1_26
VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13
+1.8V
AD2
Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18
Athlon 64 S1 Processor Socket
J6
VSS66
J8
VSS67
J10
VSS68
J12
VSS69
J14
VSS70
J16
VSS71
J18
VSS72
K2
VSS73
K7
VSS74
K9
VSS75
K11
VSS76
K13
VSS77
K15
VSS78
K17
VSS79
L6
VSS80
L8
VSS81
L10
VSS82
L12
VSS83
L14
VSS84
L16
VSS85
L18
VSS86
M7
VSS87
M9
VSS88
AC6
VSS89
M17
VSS90
N4
VSS91
N8
VSS92
N10
VSS93
N16
VSS94
N18
VSS95
P2
VSS96
P7
VSS97
P9
VSS98
P11
VSS99
P17
VSS100
R8
VSS101
R10
VSS102
R16
VSS103
R18
VSS104
T7
VSS105
T9
VSS106
T11
VSS107
T13
VSS108
T15
VSS109
T17
VSS110
U4
VSS111
U6
VSS112
U8
VSS113
U10
VSS114
U12
VSS115
U14
VSS116
U16
VSS117
U18
VSS118
V2
VSS119
V7
VSS120
V9
VSS121
V11
VSS122
V13
VSS123
V15
VSS124
V17
VSS125
W6
VSS126
Y21
VSS127
Y23
VSS128
N6
VSS129
Athlon 64 S1 Processor Socket
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
AMD CPU S1G2 PWR & GND
AMD CPU S1G2 PWR & GND
AMD CPU S1G2 PWR & GND
E
LA-4971P
LA-4971P
LA-4971P
E
0.1
0.1
7 45Wednesday, February 25, 2009
7 45Wednesday, February 25, 2009
7 45Wednesday, February 25, 2009
0.1
A
B
+1.8V+1.8V
C
D
E
< EMI require >< EMI require >
C1600.1U_0402_16V7K C1600.1U_0402_16V7K
1 2
+V_DDR_MCH_REF9
1 1
2 2
3 3
4 4
A
1
C104
C104 1000P_0402_25V8J
1000P_0402_25V8J
2
DDR_CKE0_DIMMB5
DDR_B_BS#25
DDR_B_BS#05 DDR_B_WE#5
DDR_B_CAS#5 DDR_CS1_DIMMB#5
DDR_B_ODT15
SMB_CK_DAT09,15,21,27
SMB_CK_CLK09,15,21,27
DDR_B_D0 DDR_B_D1
DDR_B_DQS#0 DDR_B_DQS0
DDR_B_D2 DDR_B_D3
DDR_B_D8 DDR_B_D9
DDR_B_DQS#1 DDR_B_DQS1
DDR_B_D10 DDR_B_D11
DDR_B_D16 DDR_B_D17
DDR_B_DQS#2 DDR_B_DQS2
DDR_B_D18 DDR_B_D22 DDR_B_D19
DDR_B_D24 DDR_B_D25
DDR_B_DM3
DDR_B_D26 DDR_B_D27
DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA12 DDR_B_MA9
DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#
DDR_B_CAS# DDR_B_ODT0 DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32 DDR_B_D33
DDR_B_DQS#4 DDR_B_DQS4
DDR_B_D34 DDR_B_D35
DDR_B_D40 DDR_B_D41
DDR_B_DM5
DDR_B_D42 DDR_B_D43 DDR_B_D47
DDR_B_D48 DDR_B_D49 DDR_B_D53
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D50 DDR_B_D51 DDR_B_D55
DDR_B_D56 DDR_B_D57
DDR_B_DM7
DDR_B_D58 DDR_B_D59
+3VS
1
C119
C119
0.1U_0402_16V7K
0.1U_0402_16V7K
2
JDDRH
JDDRH
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
201
VSS
P-TWO_A5692B-A0G16-P@
P-TWO_A5692B-A0G16-P@
DQ12 DQ13
CK0#
DQ14 DQ15
DQ20 DQ21
DQ22 DQ23
DQ28 DQ29
DQS3#
DQS3
DQ30 DQ31
NC/CKE1
NC/A15 NC/A14
RAS#
ODT0
NC/A13
DQ36 DQ37
DQ38 DQ39
DQ44 DQ45
DQS5#
DQS5
DQ46 DQ47
DQ52 DQ53
CK1#
DQ54 DQ55
DQ60 DQ61
DQS7#
DQS7
DQ62 DQ63
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS
VSS DM1 VSS CK0
VSS
VSS
VSS
VSS
DM2 VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD BA1
VDD
VDD
VSS
VSS DM4 VSS
VSS
VSS
VSS
VSS
VSS CK1
VSS DM6 VSS
VSS
VSS
VSS
VSS SAO SA1 VSS
NC
A11
A7 A6
A4 A2 A0
S0#
NC
DIMM0 STD H:9.2mm (Bot)
B
C155 0.1U_0402_16V7KC155 0.1U_0402_16V7K
2
DDR_B_D4
4
DDR_B_D5
6 8
DDR_B_DM0
10 12
DDR_B_D6
14
DDR_B_D7
16 18
DDR_B_D12
20
DDR_B_D13
22 24
DDR_B_DM1
26 28 30 32 34
DDR_B_D14
36
DDR_B_D15
38 40
42
DDR_B_D20
44
DDR_B_D21
46 48 50
DDR_B_DM2
52 54 56
DDR_B_D23
58 60
DDR_B_D28
62
DDR_B_D29
64 66
DDR_B_DQS#3
68
DDR_B_DQS3
70 72
DDR_B_D30
74
DDR_B_D31
76 78
DDR_CKE1_DIMMB
80 82
DDR_B_MA15
84
DDR_B_MA14
86 88
DDR_B_MA11
90
DDR_B_MA7
92
DDR_B_MA6DDR_B_MA8
94 96
DDR_B_MA4
98
DDR_B_MA2
100
DDR_B_MA0
102 104
DDR_B_BS#1
106
DDR_B_RAS#
108
DDR_CS0_DIMMB#
110 112 114
DDR_B_MA13
116 118 120 122
DDR_B_D36
124
DDR_B_D37
126 128
DDR_B_DM4
130 132
DDR_B_D38
134
DDR_B_D39
136 138
DDR_B_D44
140
DDR_B_D45
142 144
DDR_B_DQS#5
146
DDR_B_DQS5
148 150
DDR_B_D46
152 154 156
DDR_B_D52
158 160 162 164 166 168
DDR_B_DM6
170 172
DDR_B_D54
174 176 178
DDR_B_D60
180
DDR_B_D61
182 184
DDR_B_DQS#7
186
DDR_B_DQS7
188 190
DDR_B_D62
192
DDR_B_D63
194 196 198 200 202
12
RP8
DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_RAS#
DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6
DDR_B_CLK0 5 DDR_B_CLK#0 5
DDR_CKE1_DIMMB 5
DDR_B_BS#1 5 DDR_B_RAS# 5 DDR_CS0_DIMMB# 5
DDR_B_ODT0 5
DDR_B_CLK1 5 DDR_B_CLK#1 5
+3VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
DDR_CKE0_DIMMB DDR_B_BS#2 DDR_B_MA15 DDR_CKE1_DIMMB
DDR_B_MA3 DDR_B_MA8 DDR_B_MA12 DDR_B_MA9
DDR_B_BS#0 DDR_B_MA10 DDR_B_MA1 DDR_B_MA5
DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_CAS# DDR_B_WE#
DDR_B_BS#1 DDR_CS0_DIMMB# DDR_B_MA13 DDR_B_ODT0
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
RP8
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP9
RP9
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
RP10
RP10
18 27 36 45
47_0804_8P4R_5%
47_0804_8P4R_5%
RP11
RP11
18 27 36 45
47_0804_8P4R_5%
47_0804_8P4R_5%
RP12
RP12
18 27 36 45
47_0804_8P4R_5%
47_0804_8P4R_5%
RP13
RP13
18 27 36 45
47_0804_8P4R_5%
47_0804_8P4R_5%
RP14
RP14
1 8 2 7 3 6 4 5
47_0804_8P4R_5%
47_0804_8P4R_5%
+0.9V
C105 0.1U_0402_16V7KC105 0.1U_0402_16V7K
C106 0.1U_0402_16V7KC106 0.1U_0402_16V7K
C108 0.1U_0402_16V7KC108 0.1U_0402_16V7K
C107 0.1U_0402_16V7KC107 0.1U_0402_16V7K
C109 0.1U_0402_16V7KC109 0.1U_0402_16V7K
C110 0.1U_0402_16V7KC110 0.1U_0402_16V7K
C111 0.1U_0402_16V7KC111 0.1U_0402_16V7K
C112 0.1U_0402_16V7KC112 0.1U_0402_16V7K
C114 0.1U_0402_16V7KC114 0.1U_0402_16V7K
C113 0.1U_0402_16V7KC113 0.1U_0402_16V7K
C116 0.1U_0402_16V7KC116 0.1U_0402_16V7K
C115 0.1U_0402_16V7KC115 0.1U_0402_16V7K
C118 0.1U_0402_16V7KC118 0.1U_0402_16V7K
C117 0.1U_0402_16V7KC117 0.1U_0402_16V7K
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
D
+1.8V
12
12
12
12
12
12
12
12
12
12
12
12
12
12
DDR_B_D[0..63] 5
DDR_B_DM[0..7] 5
DDR_B_DQS[0..7] 5
DDR_B_MA[0..15] 5
DDR_B_DQS#[0..7] 5
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRII SO-DIMM 0
DDRII SO-DIMM 0
DDRII SO-DIMM 0
LA-4971P
LA-4971P
LA-4971P
E
0.1
0.1
8 45Wednesday, February 25, 2009
8 45Wednesday, February 25, 2009
8 45Wednesday, February 25, 2009
0.1
A
+1.8V
R43
R43 1K_0402_1%
1K_0402_1%
+V_DDR_MCH_REF8
1 1
2 2
3 3
4 4
1 2
R44
R44 1K_0402_1%
1K_0402_1%
1 2
A
1
C96
C96
0.1U_0402_16V7K
0.1U_0402_16V7K
2
DDR_CKE0_DIMMA5
DDR_A_BS#25
DDR_A_BS#05 DDR_A_WE#5
DDR_A_CAS#5 DDR_CS1_DIMMA#5
DDR_A_ODT15
SMB_CK_DAT08,15,21,27
SMB_CK_CLK08,15,21,27
+V_DDR_MCH_REF
1
C95
C95 1000P_0402_25V8J
1000P_0402_25V8J
2
1 2
DDR_A_D0 DDR_A_D1
DDR_A_DQS#0 DDR_A_DQS0
DDR_A_D2 DDR_A_D3
DDR_A_D8 DDR_A_D9
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D10 DDR_A_D11
DDR_A_D16 DDR_A_D20 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_DM3
DDR_A_D26 DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12 DDR_A_MA9 DDR_A_MA8
DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA0
DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#
DDR_A_CAS# DDR_A_ODT0 DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_D32 DDR_A_D33
DDR_A_DQS#4 DDR_A_DQS4
DDR_A_D34 DDR_A_D35
DDR_A_D40 DDR_A_D41
DDR_A_DM5
DDR_A_D42 DDR_A_D43
DDR_A_D48 DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51
DDR_A_D56 DDR_A_D57
DDR_A_DM7
DDR_A_D58 DDR_A_D59
+3VS
1
C103
C103
0.1U_0402_16V7K
0.1U_0402_16V7K
2
B
JDDRL
C1930.1U_0402_16V7K C1930.1U_0402_16V7K
JDDRL
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
203
VSS
PTI_A5652D-A0G16-P@
PTI_A5652D-A0G16-P@
DQ12 DQ13
CK0#
DQ14 DQ15
DQ20 DQ21
DQ22 DQ23
DQ28 DQ29
DQS3#
DQS3
DQ30 DQ31
NC/CKE1
NC/A15 NC/A14
RAS#
ODT0
NC/A13
DQ36 DQ37
DQ38 DQ39
DQ44 DQ45
DQS5#
DQS5
DQ46 DQ47
DQ52 DQ53
CK1#
DQ54 DQ55
DQ60 DQ61
DQS7#
DQS7
DQ62 DQ63
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS
VSS DM1 VSS CK0
VSS
VSS
VSS
VSS
DM2 VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD BA1
VDD
VDD
VSS
VSS DM4 VSS
VSS
VSS
VSS
VSS
VSS CK1
VSS DM6 VSS
VSS
VSS
VSS
VSS SAO SA1 VSS
NC
A11
A7 A6
A4 A2 A0
S0#
NC
DIMM0 STD H:5.2mm (Bot)
B
+1.8V+1.8V
< EMI require >< EMI require >
C161 0.1U_0402_16V7KC161 0.1U_0402_16V7K
2
DDR_A_D4
4
DDR_A_D5
6 8
DDR_A_DM0
10 12
DDR_A_D6
14
DDR_A_D7
16 18
DDR_A_D12
20
DDR_A_D13
22 24
DDR_A_DM1
26 28 30 32 34
DDR_A_D14
36
DDR_A_D15
38 40
42 44
DDR_A_D21
46 48 50
DDR_A_DM2
52 54
DDR_A_D22
56
DDR_A_D23
58 60
DDR_A_D28
62
DDR_A_D29
64 66
DDR_A_DQS#3
68
DDR_A_DQS3
70 72
DDR_A_D30
74
DDR_A_D31
76 78
DDR_CKE1_DIMMA
80 82
DDR_A_MA15
84
DDR_A_MA14
86 88
DDR_A_MA11
90
DDR_A_MA7
92
DDR_A_MA6
94 96
DDR_A_MA4
98
DDR_A_MA2
100 102 104
DDR_A_BS#1
106
DDR_A_RAS#
108
DDR_CS0_DIMMA#
110 112 114
DDR_A_MA13
116 118 120 122
DDR_A_D36
124
DDR_A_D37
126 128
DDR_A_DM4
130 132
DDR_A_D38
134
DDR_A_D39
136 138
DDR_A_D44
140
DDR_A_D45
142 144
DDR_A_DQS#5
146
DDR_A_DQS5
148 150
DDR_A_D46
152
DDR_A_D47
154 156
DDR_A_D52
158
DDR_A_D53
160 162 164 166 168
DDR_A_DM6
170 172
DDR_A_D54
174
DDR_A_D55
176 178
DDR_A_D60
180
DDR_A_D61
182 184
DDR_A_DQS#7
186
DDR_A_DQS7
188 190
DDR_A_D62
192
DDR_A_D63
194 196 198 200 204
C
DDR_A_D[0..63]
DDR_A_DM[0..7]
12
DDR_A_CLK0 5 DDR_A_CLK#0 5
DDR_CKE1_DIMMA 5
DDR_A_BS#1 5 DDR_A_RAS# 5 DDR_CS0_DIMMA# 5
DDR_A_ODT0 5
DDR_A_CLK1 5 DDR_A_CLK#1 5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_MA6 DDR_A_MA14 DDR_A_MA7 DDR_A_MA11
DDR_CKE0_DIMMA DDR_A_BS#2 DDR_CKE1_DIMMA DDR_A_MA15
DDR_A_BS#1 DDR_A_MA2 DDR_A_MA0 DDR_A_MA4
DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12
DDR_A_BS#0 DDR_A_MA10 DDR_A_MA3 DDR_A_MA1
DDR_A_ODT1 DDR_CS1_DIMMA# DDR_A_CAS# DDR_A_WE#
DDR_A_MA13 DDR_A_ODT0 DDR_A_RAS# DDR_CS0_DIMMA#
Deciphered Date
Deciphered Date
Deciphered Date
D
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
D
DDR_A_MA[0..15] 5
1 8 2 7 3 6 4 5
1 8 2 7 3 6 4 5
1 8 2 7 3 6 4 5
DDR_A_D[0..63] 5
DDR_A_DM[0..7] 5
DDR_A_DQS[0..7] 5
DDR_A_DQS#[0..7] 5
RP1
RP1
RP2
RP2
18 27 36 45
RP3
RP3
RP4
RP4
18 27 36 45
RP5
RP5
18 27 36 45
RP6
RP6
18 27 36 45
RP7
RP7
E
+0.9V
C87 0.1U_0402_16V7KC87 0.1U_0402_16V7K
1 2
C88 0.1U_0402_16V7KC88 0.1U_0402_16V7K
1 2
C90 0.1U_0402_16V7KC90 0.1U_0402_16V7K
1 2
C89 0.1U_0402_16V7KC89 0.1U_0402_16V7K
1 2
C91 0.1U_0402_16V7KC91 0.1U_0402_16V7K
1 2
C92 0.1U_0402_16V7KC92 0.1U_0402_16V7K
1 2
C93 0.1U_0402_16V7KC93 0.1U_0402_16V7K
1 2
C94 0.1U_0402_16V7KC94 0.1U_0402_16V7K
1 2
C98 0.1U_0402_16V7KC98 0.1U_0402_16V7K
1 2
C97 0.1U_0402_16V7KC97 0.1U_0402_16V7K
1 2
C100 0.1U_0402_16V7KC100 0.1U_0402_16V7K
1 2
C99 0.1U_0402_16V7KC99 0.1U_0402_16V7K
1 2
C102 0.1U_0402_16V7KC102 0.1U_0402_16V7K
1 2
C101 0.1U_0402_16V7KC101 0.1U_0402_16V7K
1 2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
+1.8V
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDRII SO-DIMM 1
DDRII SO-DIMM 1
DDRII SO-DIMM 1
LA-4971P
LA-4971P
LA-4971P
E
0.1
0.1
9 45Wednesday, February 25, 2009
9 45Wednesday, February 25, 2009
9 45Wednesday, February 25, 2009
0.1
A
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15] 19
PCIE_GTX_C_MRX_N[0..15] 19
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
1 1
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
Polarity inversion
PCIE_PTX_C_IRX_P027
< To New Card >
< To WLAN >
< To LAN >
2 2
H_CADON[0..15]
3 3
4 4
< From S1G2 CPU : x16 HT> < To S1G2 CPU : x16 HT>
H_CADOP[0..15] 4
H_CADON[0..15] 4
PCIE_PTX_C_IRX_N027
PCIE_PTX_C_IRX_P227 PCIE_PTX_C_IRX_N227 PCIE_PTX_C_IRX_P326 PCIE_PTX_C_IRX_N326
0718 Place within 1" layout 1:2
SB_RX0P20 SB_RX0N20 SB_RX1P20 SB_RX1N20 SB_RX2P20 SB_RX2N20 SB_RX3P20 SB_RX3N20
H_CLKOP04
H_CLKON04
H_CLKOP14
H_CLKON14
H_CTLOP04 H_CTLON04
H_CTLON14
1 2
PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N15 PCIE_GTX_C_MRX_P15
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7
H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
R57301_0402_1% R57301_0402_1%
B
RS780MCR3@
RS780MCR3@
H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1
HT_RXCALP HT_RXCALN
U3B
U3B
GM : RS780MN & RS780MC, PM : RX781
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15P
T3
GFX_RX15N
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1P
AD3
GPP_RX1N
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3P
W6
GPP_RX3N
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5P
U7
GPP_RX5N
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1P
Y7
SB_RX1N
AA5
SB_RX2P
AA6
SB_RX2N
W5
SB_RX3P
Y5
SB_RX3N
RS780M_FCBGA528
RS780M_FCBGA528
U3A
U3A
Y25
HT_RXCAD0P
Y24
HT_RXCAD0N
V22
HT_RXCAD1P
V23
HT_RXCAD1N
V25
HT_RXCAD2P
V24
HT_RXCAD2N
U24
HT_RXCAD3P
U25
HT_RXCAD3N
T25
HT_RXCAD4P
T24
HT_RXCAD4N
P22
HT_RXCAD5P
P23
HT_RXCAD5N
P25
HT_RXCAD6P
P24
HT_RXCAD6N
N24
HT_RXCAD7P
N25
HT_RXCAD7N
AC24
HT_RXCAD8P
AC25
HT_RXCAD8N
AB25
HT_RXCAD9P
AB24
HT_RXCAD9N
AA24
HT_RXCAD10P
AA25
HT_RXCAD10N
Y22
HT_RXCAD11P
Y23
HT_RXCAD11N
W21
HT_RXCAD12P
W20
HT_RXCAD12N
V21
HT_RXCAD13P
V20
HT_RXCAD13N
U20
HT_RXCAD14P
U21
HT_RXCAD14N
U19
HT_RXCAD15P
U18
HT_RXCAD15N
T22
HT_RXCLK0P
T23
HT_RXCLK0N
AB23
HT_RXCLK1P
AA22
HT_RXCLK1N
M22
HT_RXCTL0P
M23
HT_RXCTL0N
R21
HT_RXCTL1P
R20
HT_RXCTL1N
C23
HT_RXCALP
A24
HT_RXCALN
RS780M_FCBGA528RS780MCR3@
RS780M_FCBGA528RS780MCR3@
PART 2 OF 6
PART 2 OF 6
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)
PART 1 OF 6
PART 1 OF 6
NEED CHECK R57 & R58 WITH AMD
PCIE I/F GFX
PCIE I/F GFX
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N
HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P
HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N
HT_TXCALP HT_TXCALN
C
PCIE_MTX_GRX_P0
A5
PCIE_MTX_GRX_N0
B5
PCIE_MTX_GRX_P1
A4
PCIE_MTX_GRX_N1
B4
PCIE_MTX_GRX_P2
C3
PCIE_MTX_GRX_N2
B2
PCIE_MTX_GRX_P3
D1 D2
PCIE_MTX_GRX_P4
E2
PCIE_MTX_GRX_N4
E1
PCIE_MTX_GRX_P5
F4 F3
PCIE_MTX_GRX_P6
F1
PCIE_MTX_GRX_N6
F2
PCIE_MTX_GRX_P7
H4
PCIE_MTX_GRX_N7
H3
PCIE_MTX_GRX_P8
H1 H2
PCIE_MTX_GRX_P9
J2
PCIE_MTX_GRX_N9
J1 K4
PCIE_MTX_GRX_N10
K3
PCIE_MTX_GRX_P11
K1
PCIE_MTX_GRX_N11
K2
PCIE_MTX_GRX_P12
M4
PCIE_MTX_GRX_N12
M3
PCIE_MTX_GRX_P13
M1 M2
PCIE_MTX_GRX_P14
N2
PCIE_MTX_GRX_N14
N1
PCIE_MTX_GRX_P15
P1 P2
PCIE_ITX_PRX_P0
AC1
PCIE_ITX_PRX_N0
AC2 AB4 AB3
PCIE_ITX_PRX_P2
AA2
PCIE_ITX_PRX_N2
AA1
PCIE_ITX_PRX_P3
Y1
PCIE_ITX_PRX_N3
Y2 Y4 Y3 V1 V2
SB_TX0P_C
AD7
SB_TX0N_C
AE7
SB_TX1P_C
AE6
SB_TX1N_C
AD6
SB_TX2P_C
AB6
SB_TX2N_C
AC6
SB_TX3P_C
AD5
SB_TX3N_C
AE5
PCIE_CALRP
AC8
PCIE_CALRN
AB8
H_CADIP0
D24
H_CADIN0
D25
H_CADIP1
E24
H_CADIN1
E25
H_CADIP2
F24
H_CADIN2
F25
H_CADIP3
F23
H_CADIN3
F22
H_CADIP4
H23
H_CADIN4
H22
H_CADIP5
J25
H_CADIN5
J24
H_CADIP6
K24
H_CADIN6
K25
H_CADIP7
K23
H_CADIN7
K22
H_CADIP8
F21
H_CADIN8
G21
H_CADIP9
G20
H_CADIN9
H21
H_CADIP10
J20
H_CADIN10
J21
H_CADIP11
J18
H_CADIN11
K17
H_CADIP12
L19
H_CADIN12
J19
H_CADIP13
M19
H_CADIN13
L18
H_CADIP14
M21
H_CADIN14
P21
H_CADIP15
P18
H_CADIN15
M18
H24 H25 L21 L20
H_CTLIP0
M24
H_CTLIN0
M25
H_CTLIP1
P19
H_CTLIN1
R18
HT_TXCALP
B24
HT_TXCALN
B25
0718 Place within 1" layout 1:2
C120 0.1U_0402_16V7KPM@ C120 0.1U_0402_16V7KPM@
1 2
C121 0.1U_0402_16V7KPM@ C121 0.1U_0402_16V7KPM@
1 2
C122 0.1U_0402_16V7KPM@ C122 0.1U_0402_16V7KPM@
1 2
C123 0.1U_0402_16V7KPM@ C123 0.1U_0402_16V7KPM@
1 2
C124 0.1U_0402_16V7KPM@ C124 0.1U_0402_16V7KPM@
1 2
C125 0.1U_0402_16V7KPM@ C125 0.1U_0402_16V7KPM@
1 2
C126 0.1U_0402_16V7KPM@ C126 0.1U_0402_16V7KPM@
1 2
C127 0.1U_0402_16V7KPM@ C127 0.1U_0402_16V7KPM@
1 2
C128 0.1U_0402_16V7KPM@ C128 0.1U_0402_16V7KPM@
1 2
C129 0.1U_0402_16V7KPM@ C129 0.1U_0402_16V7KPM@
1 2
C130 0.1U_0402_16V7KPM@ C130 0.1U_0402_16V7KPM@
1 2
C131 0.1U_0402_16V7KPM@ C131 0.1U_0402_16V7KPM@
1 2
C132 0.1U_0402_16V7KPM@ C132 0.1U_0402_16V7KPM@
1 2
C133 0.1U_0402_16V7KPM@ C133 0.1U_0402_16V7KPM@
1 2
C134 0.1U_0402_16V7KPM@ C134 0.1U_0402_16V7KPM@
1 2
C135 0.1U_0402_16V7KPM@ C135 0.1U_0402_16V7KPM@
1 2
C136 0.1U_0402_16V7KPM@ C136 0.1U_0402_16V7KPM@
1 2
C137 0.1U_0402_16V7KPM@ C137 0.1U_0402_16V7KPM@
1 2
C138 0.1U_0402_16V7KPM@ C138 0.1U_0402_16V7KPM@
1 2
C139 0.1U_0402_16V7KPM@ C139 0.1U_0402_16V7KPM@
1 2
C140 0.1U_0402_16V7KPM@ C140 0.1U_0402_16V7KPM@
1 2
C141 0.1U_0402_16V7KPM@ C141 0.1U_0402_16V7KPM@
1 2
C142 0.1U_0402_16V7KPM@ C142 0.1U_0402_16V7KPM@
1 2
C143 0.1U_0402_16V7KPM@ C143 0.1U_0402_16V7KPM@
1 2
C144 0.1U_0402_16V7KPM@ C144 0.1U_0402_16V7KPM@
1 2
C145 0.1U_0402_16V7KPM@ C145 0.1U_0402_16V7KPM@
1 2
C146 0.1U_0402_16V7KPM@ C146 0.1U_0402_16V7KPM@
1 2
C147 0.1U_0402_16V7KPM@ C147 0.1U_0402_16V7KPM@
1 2
C148 0.1U_0402_16V7KPM@ C148 0.1U_0402_16V7KPM@
1 2
C149 0.1U_0402_16V7KPM@ C149 0.1U_0402_16V7KPM@
1 2
C150 0.1U_0402_16V7KPM@ C150 0.1U_0402_16V7KPM@
1 2
C151 0.1U_0402_16V7KPM@ C151 0.1U_0402_16V7KPM@
1 2
C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K
1 2
C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K
1 2
C156 0.1U_0402_16V7KWLAN@ C156 0.1U_0402_16V7KWLAN@
1 2
C157 0.1U_0402_16V7KWLAN@ C157 0.1U_0402_16V7KWLAN@
1 2
C158 0.1U_0402_16V7KC158 0.1U_0402_16V7K
1 2
C159 0.1U_0402_16V7KC159 0.1U_0402_16V7K
1 2
C162 0.1U_0402_16V7KC162 0.1U_0402_16V7K
1 2
C163 0.1U_0402_16V7KC163 0.1U_0402_16V7K
1 2
C164 0.1U_0402_16V7KC164 0.1U_0402_16V7K
1 2
C165 0.1U_0402_16V7KC165 0.1U_0402_16V7K
1 2
C166 0.1U_0402_16V7KC166 0.1U_0402_16V7K
1 2
C168 0.1U_0402_16V7KC168 0.1U_0402_16V7K
1 2
C169 0.1U_0402_16V7KC169 0.1U_0402_16V7K
1 2
C167 0.1U_0402_16V7KC167 0.1U_0402_16V7K
1 2
R55 1.27K_0402_1%R55 1.27K_0402_1%
1 2
R56 2K_0402_1%R56 2K_0402_1%
1 2
H_CADIP[0..15]H_CADOP[0..15]
H_CADIN[0..15]
H_CLKIP0 4 H_CLKIN0 4 H_CLKIP1 4 H_CLKIN1 4
H_CTLIP0 4
H_CTLIN0 4
H_CTLIP1 4H_CTLOP14
H_CTLIN1 4
R58 301_0402_1%R58 301_0402_1%
1 2
D
PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P3PCIE_MTX_GRX_N3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5PCIE_MTX_GRX_N5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8PCIE_MTX_GRX_N8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P10PCIE_MTX_GRX_P10 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13PCIE_MTX_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15PCIE_MTX_GRX_N15
H_CADIP[0..15] 4
H_CADIN[0..15] 4
< Transmitter Calibration Resistor to HT_TXCALN >
Polarity inversion
Polarity inversion
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
Polarity inversion
< To MXM VGA board >< From MXM VGA board >
Polarity inversion
Polarity inversion
PCIE_ITX_C_PRX_P0 27 PCIE_ITX_C_PRX_N0 27
PCIE_ITX_C_PRX_P2 27 PCIE_ITX_C_PRX_N2 27 PCIE_ITX_C_PRX_P3 26 PCIE_ITX_C_PRX_N3 26
SB_TX0P 20 SB_TX0N 20 SB_TX1P 20 SB_TX1N 20 SB_TX2P 20 SB_TX2N 20 SB_TX3P 20 SB_TX3N 20
+1.1VS
RS780M Display Port Support (muxed on GFX)
DP0 GFX_TX0,TX1,TX2 and TX3
DP1 GFX_TX4,TX5,TX6 and TX7
< If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs >
PCIE_MTX_GRX_P0 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_N3
< To New Card >
< To WLAN >
< To LAN >
< To SB700 : x4 PCEI A-link>< From SB700 : x4 PCIE A-link >
< TX Impedance Calibration. Connect to GND > < RX Impedance Calibration. Connect to VDDPCIE >
R74 0_0402_5%IHDMI@ R74 0_0402_5%IHDMI@
1 2
R75 0_0402_5%IHDMI@ R75 0_0402_5%IHDMI@
1 2
R76 0_0402_5%IHDMI@ R76 0_0402_5%IHDMI@
1 2
R81 0_0402_5%IHDMI@ R81 0_0402_5%IHDMI@
1 2
R82 0_0402_5%IHDMI@ R82 0_0402_5%IHDMI@
1 2
R83 0_0402_5%IHDMI@ R83 0_0402_5%IHDMI@
1 2
R84 0_0402_5%IHDMI@ R84 0_0402_5%IHDMI@
1 2
R85 0_0402_5%IHDMI@ R85 0_0402_5%IHDMI@
1 2
E
PCIE_MTX_C_GRX_P[0..15] 19
PCIE_MTX_C_GRX_N[0..15] 19
AUX0 and HPD0
AUX1 and HPD1
HDMI_TXD2+ 18,19 HDMI_TXD2- 18,19 HDMI_TXD1+ 18,19 HDMI_TXD1- 18,19
HDMI_TXD0+ 18,19 HDMI_TXD0- 18,19 HDMI_CLK0+ 18,19 HDMI_CLK0- 18,19
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
RS780M&RX781-HT/PCIE
RS780M&RX781-HT/PCIE
RS780M&RX781-HT/PCIE
LA-4971P
LA-4971P
LA-4971P
10 45Wednesday, February 25, 2009
10 45Wednesday, February 25, 2009
10 45Wednesday, February 25, 2009
E
0.1Custom
0.1Custom
0.1Custom
A
UMA_CRT_R16
GPM@
GPM@
UMA_LCD_DDC_CLK17
UMA_CRT_HSYNC14,16 UMA_CRT_VSYNC14,16 UMA_CRT_CLK16 UMA_CRT_DATA16
PLT_RST#14,19,20,26,27,33,34
NB_PWRGD21 LDT_STOP#6,20 CPU_LDT_REQ#6,20
NB_OSC_14.318M15
NBGFX_CLK15 NBGFX_CLK#15
CLK_SBLINK_BCLK15 CLK_SBLINK_BCLK#15
UMA_LCD_DDC_DAT17
HDMIDAT_UMA18 HDMICLK_UMA18
1 2
UMA_CRT_G16
UMA_CRT_B16
+VDDA18HTPLL
+VDDA18PCIEPLL
CLK_NBHT15 CLK_NBHT#15
AUX_CAL14
1 1
< DAC internal reference to set full scale DAC current >
+1.1VS
R71
R71
4.7K_0402_5%
4.7K_0402_5%
1 2
12
2 2
R72
R72
4.7K_0402_5%
4.7K_0402_5%
Strap pin
< Dedicated power for the DAC which can affect display quality > < Dedicated power for the DAC which can affect display quality >
+3VS +1.8VS
3 3
+NB_PLLVDD
+NB_HTPVDD
+3VS
L2
L2 0_0603_5%
0_0603_5%
L2
L2 BLM18PG121SN1D_0603GM@
BLM18PG121SN1D_0603GM@
B
+AVDD1
+AVDD2
+AVDDQ
UMA_CRT_R
UMA_CRT_G
UMA_CRT_B
R65 715_0402_1%GPM@ R65 715_0402_1%GPM@ R65 715_0402_1%GM@ R65 715_0402_1%GM@
1 2
R67 0_0402_5%R67 0_0402_5%
1 2
R88 10K_0402_5%@ R88 10K_0402_5%@
PM1@ C170
PM1@
GM@
GM@
AVDD=100mA
UMA_CRT_HSYNC UMA_CRT_VSYNC
12
C170 0_0603_5%
0_0603_5%
1
C170
C170
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
U3C
U3C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
+NB_PLLVDD +NB_HTPVDD
NB_RESET# NB_PWRGD
RS780MCR3@
RS780MCR3@
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS780M_FCBGA528
RS780M_FCBGA528
+AVDD1 +AVDD2
C
PART 3 OF 6
PART 3 OF 6
GPM@ L4
GPM@
TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
LVTM
PM
PM
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
L4 0_0603_5%
0_0603_5%
L4
L4 0_0603_5%GM@
0_0603_5%GM@
TXOUT_U0N(NC)
TXOUT_U2P(NC) TXOUT_U2N(NC)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
PM1@ C172
PM1@
1
GM@
GM@
2
VDDLTP18(NC) VSSLTP18(NC)
VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)
VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)
TMDS_HPD(NC)
HPD(NC)
TESTMODE
C172 0_0603_5%
0_0603_5%
C172
C172
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
A22 B22 A21 B21 B20 A20 A19 B19
B18 A18 A17 B17 D20 D21 D18 D19
B16 A16 D16 D17
+VDDLTP18
A13 B13
+VDDLT18
A15 B15 A14 B14
C14 D15 C16 C18 C20 E20 C22
E9 F7 G12
T17PAD T17PAD
D9 D10
D12
AE8 AD8
R80 1.8K_0402_5%R80 1.8K_0402_5%
D13
PM1@ C198
PM1@
1
C198
C198
GM@
GM@
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1 2
R79 0_0402_5%GM@ R79 0_0402_5%GM@
1 2
R78 0_0402_5%GPM@ R78 0_0402_5%GPM@ R78 0_0402_5%GM@ R78 0_0402_5%GM@
1 2
C198 0_0402_5%
0_0402_5%
D
UMA_LCD_TXOUT0_A0+ 17 UMA_LCD_TXOUT0_A0- 17 UMA_LCD_TXOUT0_A1+ 17 UMA_LCD_TXOUT0_A1- 17 UMA_LCD_TXOUT0_A2+ 17 UMA_LCD_TXOUT0_A2- 17
UMA_LCD_TZOUT0_B0+ 17 UMA_LCD_TZOUT0_B0- 17 UMA_LCD_TZOUT0_B1+ 17 UMA_LCD_TZOUT0_B1- 17 UMA_LCD_TZOUT0_B2+ 17 UMA_LCD_TZOUT0_B2- 17
UMA_LCD_TXCLK_ACLK+ 17 UMA_LCD_TXCLK_ACLK- 17 UMA_LCD_TZCLK_BCLK+ 17 UMA_LCD_TZCLK_BCLK- 17
UMA_ENVDD 17
R73 100K_0402_5%GPM@ R73 100K_0402_5%GPM@ R73 100K_0402_5%GM@ R73 100K_0402_5%GM@
UMA_ENBKL 34
12
HPD 18,19,21
SUS_STAT# 14,21
+1.8VS
< LVDS dual channel : channel 1 >
< LVDS dual channel : channel 2 >
< LVDS digital power enable >
< LVDS backlight enable >
< HDMI hot-plug detection >
< Strap option pin or gate side-port memory IO >
R371 300_0402_5%R371 300_0402_5%
1 2
E
NB_PWRGD
RS780 use 140 ohm, check RS880 use what value
R62 140_0402_1%GM@ R62 140_0402_1%GM@
1 2
R63 150_0402_1%GM@ R63 150_0402_1%GM@
1 2
R64 150_0402_1%GM@ R64 150_0402_1%GM@
1 2
UMA_CRT_R
UMA_CRT_G
UMA_CRT_B
< DAC Bandgap Reference Voltage >
GPM@
GPM@
+1.8VS
1 2
< IO power for HyperTransport PLL >
+1.8VS +VDDA18HTPLL
L10 BLM18PG121SN1D_0603L10 BLM18PG121SN1D_0603
1 2
4 4
A
< 1.8V IO power for PCI-E PLLs >
+1.8VS
L11 BLM18PG121SN1D_0603L11 BLM18PG121SN1D_0603
1 2
L6
L6 0_0603_5%
0_0603_5%
L6
L6 BLM18PG121SN1D_0603GM@
BLM18PG121SN1D_0603GM@
1
C179
C179
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
1
C180
C180
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
B
C175
PM1@ C175
PM1@
0_0603_5%
0_0603_5%
1
C175
C175
GM@
GM@
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+VDDA18PCIEPLL
+AVDDQ
< 1.8V power for system PLLs >
GPM@
GPM@
+1.8VS
1 2
GPM@
GPM@
+1.1VS
1 2
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
L7
L7 0_0603_5%
0_0603_5%
L7
L7 BLM18PG121SN1D_0603GM@
BLM18PG121SN1D_0603GM@
L9
L9 0_0603_5%
0_0603_5%
L9
L9 BLM18PG121SN1D_0603GM@
BLM18PG121SN1D_0603GM@
Compal Secret Data
Compal Secret Data
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
C176
PM1@ C176
PM1@
0_0603_5%
0_0603_5%
1
C176
C176
GM@
GM@
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
C178
PM1@ C178
PM1@
0_0603_5%
0_0603_5%
1
C178
C178
GM@
GM@
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
Deciphered Date
Deciphered Date
Deciphered Date
+NB_HTPVDD
+NB_PLLVDD
< Power for integrated DVI/HDMI PLL macro >
+1.8VS
< 1.8V IO power for the integrated DVI/HDMI interface >< 1.1V Power for system PLLs >
+1.8VS
D
C171
PM1@ C171
C174
C174
4.7U_0805_10V4Z
4.7U_0805_10V4Z
PM1@
1
GM@
GM@
2
LA-4971P
LA-4971P
LA-4971P
E
0_0603_5%
0_0603_5%
C171
C171
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
PM1@ C173
PM1@
GM@
GM@
GPM@
GPM@
GPM@ L5
GPM@
GM@ L5
GM@
12
L3
L3 0_0603_5%
0_0603_5%
L3
L3 BLM18PG121SN1D_0603GM@
BLM18PG121SN1D_0603GM@
12
L5 0_0603_5%
0_0603_5%
L5 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
GM@
GM@
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
RS780 VEDIO/CLK GEN
RS780 VEDIO/CLK GEN
RS780 VEDIO/CLK GEN
C173 0_0402_5%
0_0402_5%
1
C173
C173
0.1U_0402_16V7K
0.1U_0402_16V7K
2
11 45Wednesday, February 25, 2009
11 45Wednesday, February 25, 2009
11 45Wednesday, February 25, 2009
+VDDLTP18
+VDDLT18
0.1
0.1
0.1
2
B B
U3D
AB12 AE16
AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14
AD16 AE17 AD17
W12
AD18 AB13 AB18
W14
AE12 AD12
V11
Y14
Y12
V14
V15
U3D
MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC)
MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)
MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC)
MEM_CKP(NC) MEM_CKN(NC)
MEM_COMPP(NC) MEM_COMPN(NC)
RS780M_FCBGA528RS780MCR3@
RS780M_FCBGA528RS780MCR3@
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC) MEM_DQS1N(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
IOPLLVDD18(NC)
MEM_VREF(NC)
MEM_DQ4(NC)
MEM_DM0(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21
Y17 W18 AD20 AE21
W17 AE19
AE23 AE24
AD23
AE18
+1.8VS +1.1VS
1
A A
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
1
Date: Sheet of
Compal Electronics, Inc.
RS780M&RX781 SIDE PORT
RS780M&RX781 SIDE PORT
RS780M&RX781 SIDE PORT
LA-4971P
LA-4971P
LA-4971P
12 45Wednesday, February 25, 2009
12 45Wednesday, February 25, 2009
12 45Wednesday, February 25, 2009
0.1
0.1
0.1
A
B
C
D
E
U3E
2A
L16 0_0805_5%L16 0_0805_5%
+1.1VS
1 1
+1.2V_HT
+1.8VS
2 2
+1.8VS
1
2
3 3
4 4
12
1
C209
C209
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
2A < IO power for HyperTransport receive interface >
L18 0_0805_5%L18 0_0805_5%
12
C215
C215
10U_0805_10V4Z
10U_0805_10V4Z
2A < IO power for HyperTransport transmit interface >
L19 0_0805_5%L19 0_0805_5%
12
1
C225
C225
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
2A < 1.8V IO power for PCI-E graphics, SB, and GPP interfaces >
L22 0_0805_5%L22 0_0805_5%
12
1
C235
C235
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
C251
C251
1U_0402_6.3V4Z
1U_0402_6.3V4Z
+1.8VS
A
1
C206
C206
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C214
C214
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C226
C226
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C246
C246
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
L89 0_0603_5%GM@ L89 0_0603_5%GM@
1 2
L89 0_0603_5%GPM@ L89 0_0603_5%GPM@
< Digital IO power for HyperTransport interface >
1
C207
C207
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C216
C216
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C227
C227
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C236
C236
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C208
C208
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C217
C217
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C228
C228
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C237
C237
0.1U_0402_16V7K
0.1U_0402_16V7K
2
< 1.8V IO transform power >
< 1.8V power for side-port memory interface >
1
C252
C252
GM@
GM@
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
C252
PM1@ C252
PM1@
0_0402_5%
0_0402_5%
B
1
C210
C210
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C218
C218
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C229
C229
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C238
C238
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C239
C239
0.1U_0402_16V7K
0.1U_0402_16V7K
2
+VDDHT
+VDDHTRX
+VDDHTTX
+VDDA18PCIE
/
/
/
Security Classification
Security Classification
Security Classification
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
J17 K16 L16
M16
P16
R16
T16
H18 G19
F20 E21
D22
B23 A23
AE25 AD24 AC23 AB22 AA21
Y20
W19
V18
U17
T17
R17
P17
M17
J10 P10 K10
M10
L10
W9
H9
T10
R10
Y9 AA9 AB9 AD9 AE9 U10
F9
G9 AE11 AD11
A25
D23
E22 G22 G24 G25 H19
J22 L17 L22 L24 L25
M20 N22
P20
R19 R22 R24 R25 H20 U22
V19
W22 W24 W25
Y21
AD25
L12
M14 N13
P12 P15
R11 R14
T12
U14 U11 U15
V12
W11
W15 AC12 AA14
Y18 AB11 AB15 AB17 AB19 AE20 AB21
K11
Issued Date
Issued Date
Issued Date
U3E
VDDHT_1
PART 5/6
PART 5/6
VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7
VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7
VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13
VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15
VDD18_1 VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC)
RS780M_FCBGA528RS780MCR3@
RS780M_FCBGA528RS780MCR3@
U3F
U3F
VSSAHT1
PART 6/6
PART 6/6
VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27
VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34
RS780M_FCBGA528
RS780M_FCBGA528
RS780MCR3@
RS780MCR3@
C
VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8
VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17
VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8
VDDC_9 VDDC_10 VDDC_11 VDDC_12
POWER
POWER
VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22
VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)
VDD33_1(NC) VDD33_2(NC)
VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8
VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30
GROUND
GROUND
VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9
VSS10
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
< Main IO power for PCI-E graphics, SB, and GPP interfaces >
+VDDA11PCIE
A6 B6 C6
VDDA_12=2.5A
D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9
K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16
AE10 AA11
< Isolated power for side-port memory interface >
Y11 AD10 AB10 AC10
< 3.3V IO power >
H11 H12
A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2
AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
GM@
GM@
C2191U_0402_6.3V4Z C2191U_0402_6.3V4Z
C2201U_0402_6.3V4Z C2201U_0402_6.3V4Z
1
1
2
2
C2400.1U_0402_16V 7K C2400.1U_0402_16V7K
C2470.1U_0402_16V 7K C2470.1U_0402_16V7K
2
2
1
1
1
C250
C250
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1 2
C21110U_0805_10V4Z C21110U_0805_10V 4Z
C2221U_0402_6.3V4Z C2221U_0402_6.3V4Z
1
2
C2230.1U_0402_16V7K C2230.1U_0402_16V7K
C2240.1U_0402_16V7K C2240.1U_0402_16V7K
C2211U_0402_6.3V4Z C2211U_0402_6.3V4Z
2
1
1
2
C21210U_0805_10V4Z C21210U_0805_10V 4Z
2
1
+NB_CORE
VDD_CORE:GM=5A/PM=10A< Core power >
C2420.1U_0402_16V 7K C2420.1U_0402_16V7K
C2430.1U_0402_16V 7K C2430.1U_0402_16V7K
C2410.1U_0402_16V 7K C2410.1U_0402_16V7K
2
2
2
1
1
1
C2320.1U_0402_16V 7K C2320.1U_0402_16V7K
C2300.1U_0402_16V 7K C2300.1U_0402_16V7K
C2310.1U_0402_16V 7K C2310.1U_0402_16V7K
C2440.1U_0402_16V 7K C2440.1U_0402_16V7K
2
2
2
2
1
1
1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
C23310U_0805_10V4Z C23310U_0805_10V4Z
1
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
RS780M&RX781 PWR/GND
RS780M&RX781 PWR/GND
RS780M&RX781 PWR/GND
1
C24510U_0805_10V4Z C24510U_0805_10V4Z
2
GM@
GM@
LA-4971P
LA-4971P
LA-4971P
1
+
+
C234
C234
330U_D2E_2.5VM
330U_D2E_2.5VM
2
DVT change to B size
1
C253
C253
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
E
L17FBMA-L11-201209-221LMA30T_0805 L17FBMA-L11-201209-221LMA30T_0805
PJP9
PJP9
12
PAD-OPEN 4x4m
PAD-OPEN 4x4m
13 45Wednesday, February 25, 2009
13 45Wednesday, February 25, 2009
13 45Wednesday, February 25, 2009
+1.1VS
+1.1VS
+3VS
0.1Custom
0.1Custom
0.1Custom
A
B
C
D
E
< RS780 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K >
SI2: Change to 3K pull high
R101
R101 3K_0402_5%
3K_0402_5%
UMA_CRT_VSYNC11,16
1 1
12
R102
R102 3K_0402_5%@
3K_0402_5%@
12
< RS780 use register to control PCI-E configure >
< RS780 DFT_GPIO1 >
R104
R104 150_0402_1%@
150_0402_1%@
PLT_RST# 11,19,20,26,27,33,34
D4
D4 CH751H-40PT_SOD323-2@
CH751H-40PT_SOD323-2@
1 2
AUX_CAL11
2 2
SUS_STAT#11,21
2 1
< RS780 use HSYNC to enable SIDE PORT (internal pull high) >
< DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb >
Enables the Test Debug Bus using GPIO.
1 : Enable (RX780, RS780)
+3VS
0 : Disable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#
< DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >
These pin straps are used to configure PCI-E GPP mode. 000 : 00001 001 : 00010 010 : 01011 011 : 00100 100 : 01010 101 : 01100 111 : 01011
< DFT_GPIO1 : LOAD_EEPROM_STRAPS >
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
< DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb >
RX780: Enables the Test Debug Bus using PCIE bus
R125
R125 3K_0402_5%
3K_0402_5%
UMA_CRT_HSYNC11,16
12
+3VS
1 : Disable ( Can still be enabled using nbcfg register access ) 0 : Enable
RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS780) 0 : Enable (RS780)
3 3
4 4
/
/
/
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
RS780M&RX781 STRAPS
RS780M&RX781 STRAPS
RS780M&RX781 STRAPS
LA-4971P
LA-4971P
LA-4971P
14 45Wednesday, February 25, 2009
14 45Wednesday, February 25, 2009
14 45Wednesday, February 25, 2009
E
0.1Custom
0.1Custom
0.1Custom
Loading...
+ 32 hidden pages
Privacy Policy Cookie Policy Terms of Use