V02 DA0V02MB6E0
1
PCB STACK UP
2
3
4
5
6
7
8
6L
UMA
V02/R01 UMA BLOCK DIAGRAM
LAYER 1 : TOP
LAYER 2 : GND
A A
LAYER 3 : IN1
LAYER 4 : IN2
DDRIII-SODIMM1
H=4mm
PAGE 16
LAYER 5 : VCC
LAYER6 : BOT
B B
C C
D D
Keyboard Conn.
Touch Pad
DDRIII-SODIMM2
H=8mm
E-SATA
SATA -HDD
ODD
3-axis Fall Sensor
PAGE 42
PAGE 42
PAGE 17
PAGE 28
PAGE 31
PAGE 36
PAGE 31
FAN
&Thermal
PAGE 45
DDRIII 1333 MT/s
DDRIII 1333 MT/s
SATA4 3G /S
SATA0 6G /S
SATA1 6G /S
SMBUS
KBC
ITE 8518
PAGE 32
SPI ROM
PAGE 41
FDI LINK
LPC
CPU
Sandy Bridge 35W
PGA 988
2.5GT /s
Mobile Intel
Series 6 Chipset
PCH
HM67
Couger Point
BGA 989
25 mm X 25 mm
SPI
SPI ROM
4MB512KB
PAGE 41
25MHz
PAGE 4~8
DMI LINK
2.5GT /s
PAGE 9~15
32.768KHz
INT HDMI
INT CRT
INT Single CHANNEL LVDS
iGFX Interfaces
ESATA+USB2.0
USB2.0
PCI-E
USB[0]
PCI-E
IHDA
IHDA
WLAN
PAGE 34
PCIE[5]
LAN
Realtek
RTL8111EL
PAGE 39
Audio Codec
ALC 269
PAGE 38
USB Port x1
PAGE 29PAGE 35
25MHz
RJ45
PAGE 39
USB[2]
USB[5]USB[4]
WWAN
PAGE 35
PCIE[2]PCIE[1]
PCIE[3]
USB3.0 Controller
PAGE 36
USB3.0 Ports x2
PAGE 37
IO Board
PAGE 33
HDMI CONN
PAGE 20
Camera
CRT Board
LCD CONN
1366 x 768 (HD)
USB[11]
PAGE 30
PAGE 26
PAGE 25
USB[8]
Card Reader
RTL5128-GR
Charger
3/5V
1.5V_SUS/0.75V_DDR
1.8V_RUN
1.05V_VTT/PCH
VCCSA
DGFX_CORE
CPU_CORE
PAGE 30
PAGE 49
PAGE 50
PAGE 51
PAGE 52
PAGE 53
PAGE 54
PAGE 55
PAGE 56
MB Side
1
2
3
4
PAGE 38 PAGE 38
5
JackSpeaker Digital-MIC
PAGE 38
X2
6
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
7
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
V02/R01
V02/R01
V02/R01
1 51
1 51
1 51
8
1A
1A
1A
1
2
3
4
5
6
7
8
power
A A
State
S0
S1
B B
S3
S4/S5 AC
S4/S5
DC Only
AC/DC
No Exist
C C
SMBCLK
SMBDATA
SMB_CLK_ME1
SMB_DAT_ME1
AB1A_CLK
AB1A_DATA
D D
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
1
2
3
4
5
6
Wednesday, January 19, 2011
7
PROJECT :
Power Rails
Power Rails
Power Rails
V02/R01
V02/R01
V02/R01
2 51
2 51
2 51
8
1A
1A
1A
5
D D
C C
4
3
2
1
B B
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
5
4
3
2
Wednesday, January 19, 2011
PROJECT :
BLANK
BLANK
BLANK
1
V02/R01
V02/R01
V02/R01
3 51
3 51
3 51
1A
1A
1A
5
4
3
2
1
DP & PEG Compensation
Sandy Bridge Processor (DMI,PEG,FDI)
U13A
D D
DMI_TXN09
DMI_TXN19
DMI_TXN29
DMI_TXN39
DMI_TXP09
DMI_TXP19
DMI_TXP29
DMI_TXP39
DMI_RXN09
DMI_RXN19
DMI_RXN29
DMI_RXN39
DMI_RXP09
DMI_RXP19
DMI_RXP29
DMI_RXP39
FDI_TXN09
FDI_TXN19
FDI_TXN29
C C
eDP_ICOMPO 12mil
B B
eDP_COMPIO 4mil
FDI_TXN39
FDI_TXN49
FDI_TXN59
FDI_TXN69
FDI_TXN79
FDI_TXP09
FDI_TXP19
FDI_TXP29
FDI_TXP39
FDI_TXP49
FDI_TXP59
FDI_TXP69
FDI_TXP79
FDI_FSYNC09
FDI_FSYNC19
FDI_LSYNC09
FDI_LSYNC19
FDI_INT9
eDP_COMP
INT_eDP_HPD
Programing Disable eDP interface(BIOS)
U13A
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
CPU-989P-rPGA
CPU-989P-rPGA
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_TX#[10]
PEG_TX#[11]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_COMP
PEG_ICOMPO 12mil
PEG_ICOMPI, PEG_RCOMPO 4mil,
+1.05V_PCH
R23 24.9/F_4R23 24.9/F_4
eDP_COMPIO and ICOMPO signals should
be shorted near balls and
routed within 500 mils
+1.05V_PCH
R50 24.9/F_4R50 24.9/F_4
PEG_ICOMPI and RCOMPO signals should
be routed within 500 mils
PEG_ICOMPO signals should
be routed within 500 mils
eDP_COMP
PEG_COMP
eDP Hot-plug (Disable)
+1.05V_PCH
R20
R20
*10K_4_NC
*10K_4_NC
INT_eDP_HPD
CAD Note: Place PU resistor within 2 inches
of CPU
This signal can be left as no connect if
entire eDP interface is disabled.
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
5
4
3
2
Wednesday, January 19, 2011
PROJECT :
Sandy Bridge 1/5
Sandy Bridge 1/5
Sandy Bridge 1/5
V02/R01
V02/R01
V02/R01
1
4 51
4 51
4 51
1A
1A
1A
5
4
3
2
1
Sandy Bridge Processor (CLK,MISC,JTAG)
U13B
U13B
SNB_IVB# N.A at SNB EDS #27637 0.7v1
TP4TP4
C314
C314
*0.1U/10V_NC
*0.1U/10V_NC
CPU_PLTRST#CPU_PLTRST#CPU_PLTRST#
H_SNB_IVB#
TP_CATERR#
H_PROCHOT#
SM_DRAMPWROK
CPU_PLTRST#_RCPU_PLTRST#_R
H_SNB_IVB#12
D D
Over 130 degree C will
drive low
C C
CPU_PLTRST
R497,R228
Option1 POP
Option2 NC
B B
PLTRST#12,25,26,28
IN OUT
L L
H
High-Z
H_CPUDET#25
PECI_EC25
IMVP7_PROCHOT#25,37,40
PM_THRMTRIP#14
H_PM_SYNC9
H_PWRGOOD14
+1.05V_PCH
CPU_PLTRST#
U14,C314,R303,R302
NC
POP
U14
U14
1
2
*74LVC1G07GW_NC
R497
R497
1.5K
1.5K
R228
R228
750/F
750/F
*74LVC1G07GW_NC
CPU_PLTRST#_RCPU_PLTRST#_R
R85 43_4R85 43_4
R84 56/J_4R84 56/J_4
R301 10K_4R301 10K_4
R303 *75_4_NCR303 *75_4_NC
R302 *43/J_4_NCR302 *43/J_4_NC
+3.3V_SUS
5
VCC
NC
IN
4
GND3OUT
Change OD part same with PDC
Copy from PDC
A A
PM_DRAM_PWRGD9
SYS_PWROK9
Follow #DG1.0 436735 P105
DDR Power Gating Topology
5
+3.3V_SUS
R136
R136
200_4
200_4
2
1
3 5
74AHC1G09GW
74AHC1G09GW
C105
C105
0.1U/10V
0.1U/10V
U5
U5
4
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
AR33
RESET#
CPU-989P-rPGA
CPU-989P-rPGA
+1.5V_CPU
DRAM_PWRGD
SYS_PWROK
SM_DRAMPWROK
R8239, R8241 change to 5%
+1.5V_CPU
R104 *39_NCR104 *39_NC
4
Boot S3
R102
R102
200/F_4
200/F_4
R103 130/F_4R103 130/F_4
3
Q9 *2N7002K_NCQ9 *2N7002K_NC
1
2
Pin1
L L
H
H
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
Pin2 Pin4
HL
L
H
SM_DRAMPWROKSM_DRAMPWROK_R
PS_S3CNTRL 7,16
CLOCKS
CLOCKS
DDR3
DDR3
JTAG & BPM
JTAG & BPM
S3 RSM
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
MISC
MISC
100 ns after +1.5V_CPU
reaches 80%
L
L
L
H
3
BCLK
BCLK#
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
TDI
A28
A27
CLK_DP_P_R
A16
CLK_DP_N_R
A15
CPU_DRAMRST#
R8
SM_RCOMP_0
AK1
SM_RCOMP_1
A5
SM_RCOMP_2
A4
AP29
AP27
AR26
AR27
AP30
AR28
AP26
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
TP10TP10
TP13TP13
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_DBRST#
TP32TP32
TP12TP12
TP33TP33
TP34TP34
TP7TP7
TP30TP30
TP31TP31
TP8TP8
R289 1K_4R289 1K_4
R287 *0_4_NCR287 *0_4_NC
R286 *0_4_NCR286 *0_4_NC
R288 1K_4R288 1K_4
R71 140/F_4R71 140/F_4
R27 25.5/F_4R27 25.5/F_4
R29 200/F_4R29 200/F_4
R134 51/J_4R134 51/J_4
R294 1K_4R294 1K_4
XDP_DBRST# use a 1k pull-up to 3.3V_S
TRST# use a 51ohm pull down.
When MP, JTAG PU/PD resistor
can be removed?
Need to confirm with Intel
Follow #DG1.0 436735 P107
DRAMRST# Routing Illustration
DDR3_DRAMRST#16,17
DDR_HVREF_RST_PCH13
+1.05V_PCH
+3.3V_RUN
2
CLK_CPU_BCLKP 13
CLK_CPU_BCLKN 13
CLK_DP_P 13
CLK_DP_N 13
Schematic C/L_v1.0, P56 (PU,PD 1k/J)
(Intel and PD3)
Reserve (Intel confirm now)
SM_RCOMP_0, SM_RCOMP_1 20mil
SM_RCOMP_2 15mil,
XDP_TMS
XDP_TDI
XDP_TDO
IMVP7_PROCHOT#
XDP_TCLK
+1.5V_SUS
R41
R41
1K/F_4
1K/F_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
R49
R49
1K/F_4
1K/F_4
R48 *0_4_NCR48 *0_4_NC
Q2
Q2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Sandy Bridge 2/5
Sandy Bridge 2/5
Sandy Bridge 2/5
R106 51/J_4R106 51/J_4
R305 51/J_4R305 51/J_4
R121 51/J_4R121 51/J_4
R83 62/J_4R83 62/J_4
R123 51/J_4R123 51/J_4
2N7002W -7-F
2N7002W -7-F
3 1
2
C26
C26
0.047U/10V
0.047U/10V
1
+1.05V_PCH
CPU_DRAMRST#DDR3_DRAMRST#_R
R47
R47
4.99K/F_4
4.99K/F_4
V02/R01
V02/R01
V02/R01
5 51
5 51
5 51
1A
1A
1A
5
4
Sandy Bridge Processor (DDR3)
U13C
U13C
3
U13D
U13D
2
1
D D
C C
B B
M_A_DQ[63:0]16
M_A_BS016
M_A_BS116
M_A_BS216
M_A_CAS#16
M_A_RAS#16
M_A_WE#16
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33 M_B_DQ34
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
F10
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AE8
AD9
AF9
C5
D5
D3
D2
D6
C6
C2
C3
F8
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N8
N7
M9
N9
M7
V6
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CLK#[0]
SA_CLK#[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
RSVD_TP[7]
RSVD_TP[8]
RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_CLK[0]
SA_CKE[0]
SA_CLK[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_CLKP0 16
M_A_CLKN0 16
M_A_CKE0 16
M_A_CLKP1 16
M_A_CLKN1 16
M_A_CKE1 16
M_A_CS#0 16
M_A_CS#1 16
M_A_ODT0 16
M_A_ODT1 16
M_A_DQSN[7:0] 16
M_A_DQSP[7:0] 16
M_A_A[15:0] 16
M_B_DQ[63:0]17
M_B_BS017
M_B_BS117
M_B_BS217
M_B_CAS#17
M_B_RAS#17
M_B_WE#17
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
D10
K10
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
AA10
AB8
AB9
C9
A7
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
K9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
R6
J7
J8
J9
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_CLK#[0]
SB_CLK#[1]
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
RSVD_TP[17]
RSVD_TP[18]
RSVD_TP[19]
RSVD_TP[20]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_CLK[0]
SB_CKE[0]
SB_CLK[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AE2
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_CLKP0 17
M_B_CLKN0 17
M_B_CKE0 17
M_B_CLKP1 17
M_B_CLKN1 17
M_B_CKE1 17
M_B_CS#0 17
M_B_CS#1 17
M_B_ODT0 17
M_B_ODT1 17
M_B_DQSN[7:0] 17
M_B_DQSP[7:0] 17
M_B_A[15:0] 17
CPU-989P-rPGA
CPU-989P-rPGA
CPU-989P-rPGA
A A
5
4
3
CPU-989P-rPGA
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
2
Wednesday, January 19, 2011
PROJECT :
Sandy Bridge 3/5
Sandy Bridge 3/5
Sandy Bridge 3/5
V02/R01
V02/R01
V02/R01
1
6 51
6 51
6 51
1A
1A
1A
5
Sandy Bridge Processor (POWER)
POWER
POWER
U13F
U13F
+VCC_CORE
AG35
VCC1
AG34
VCC2
C298
C298
10U/10V/0805
10U/10V/0805
C312
C312
*10U/10V/0805_NC
*10U/10V/0805_NC
C38
C38
C290
C290
SVID CLK
Close to VR
R299
R299
54.9/F_4
54.9/F_4
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
CPU-989P-rPGA
CPU-989P-rPGA
VR_SVID_CLK 40
CORE SUPPLY
CORE SUPPLY
SENSE LINES SVID
SENSE LINES SVID
Place PU resistor close to CPU
+1.05V_PCH +1.05V_PCH +1.05V_PCH
D D
CPU Core Power
SNB 35W:55A
10uF x 24
C301
C301
C307
C307
C294
C294
C288
C317
C317
C318
C318
10U/10V/0805
10U/10V/0805
C311
C311
*10U/10V/0805_NC
*10U/10V/0805_NC
C C
B B
A A
10U/10V/0805
10U/10V/0805
*10U/10V/0805_NC
C292
C292
10U/10V/0805
10U/10V/0805
C40
C40
10U/6.3V_6
10U/6.3V_6
C37
C37
10U/6.3V_6
10U/6.3V_6
H_CPU_SVIDCLK
*10U/10V/0805_NC
C297
C297
10U/10V/0805
10U/10V/0805
C304
C304
10U/6.3V_6
10U/6.3V_6
C39
C39
10U/6.3V_6
10U/6.3V_6
10U/10V/0805
10U/10V/0805
C302
C302
10U/10V/0805
10U/10V/0805
Layout note: need routing
together and ALERT need
between CLK and DATA
*10U/10V/0805_NC
*10U/10V/0805_NC
C293
C293
10U/10V/0805
10U/10V/0805
C291
C291
10U/6.3V_6
10U/6.3V_6
C303
C303
10U/6.3V_6
10U/6.3V_6
2
112
5
C288
*10U/10V/0805_NC
*10U/10V/0805_NC
C286
C286
*10U/10V/0805_NC
*10U/10V/0805_NC
C36
C36
10U/6.3V_6
10U/6.3V_6
C308
C308
10U/6.3V_6
10U/6.3V_6
+1.05V_PCH
R297SJ_0402 R297SJ_0402
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
PEG AND DDR
PEG AND DDR
VIDALERT#
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
R293
R293
130_4
130_4
H_CPU_SVIDDAT
4
CPU VTT
SNB 35W:8.5A
10F x12
C44
C44
10U/10V/0805
10U/10V/0805
C32
C32
10U/10V/0805
10U/10V/0805
+1.05V_PCH
C21
C21
10U/10V/0805
10U/10V/0805
C15
C15
10U/10V/0805
10U/10V/0805
+VCC_CORE
VCCIO_SENSE 41
VSSIO_SENSE 41
C283
C283
C295
C295
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
C33
C33
C34
C34
10U/10V/0805
10U/10V/0805
10U/10V/0805
10U/10V/0805
VCCSENSE 40 PS_S3CNTRL 5,16
VSSSENSE 40
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDSCLK
VIDSOUT
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
C287
C287
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
10U/10V/0805
10U/10V/0805
C289
C289
10U/10V/0805
10U/10V/0805
H_CPU_SVIDALRT#
H_CPU_SVIDCLK VCCSA_VID0
H_CPU_SVIDDAT
R72 100_4R72 100_4
R75 100_4R75 100_4
Change R8281,R8285, R8704,R8329 to +/-5%
54.9 ohm has no 5%
SVID DATA
Close to VR
R295
R295
130_4
130_4
R296SJ_0402 R296SJ_0402
2
112
4
3
CPU VGT
SNB 35W:22A
10uF x 12
C296
C296
10U/10V/0805
10U/10V/0805
C300
C300
10U/10V/0805
10U/10V/0805
C17
C17
10U/10V/0805
10U/10V/0805
CPU VCCPL
SNB 35W:3A
10uF x 1
1uF x 2
+1.8V_RUN
C117
C117
10U/10V/0805
10U/10V/0805
SIO_SLP_S3#9,25,39
Place PU resistor close to CPU
R300
R300
75_4
H_CPU_SVIDALRT#
R298 43_4R298 43_4
75_4
3
C101
C101
10U/10V/0805
10U/10V/0805
C18
C18
10U/6.3V_6
10U/6.3V_6
C100
C100
10U/10V/0805
10U/10V/0805
C78
C78
10U/6.3V_6
10U/6.3V_6
Sandy Bridge Processor (GRAPHIC POWER)
2
POWER
POWER
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
VREFMISC
VREFMISC
GRAPHICS
GRAPHICS
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
31
2
VCCSA_VID1
R70
R70
100K_4
100K_4
C64 0.1U/10VC64 0.1U/10V
C35 0.1U/10VC35 0.1U/10V
C57 0.1U/10VC57 0.1U/10V
C42 0.1U/10VC42 0.1U/10V
1.8V RAIL
1.8V RAIL
Q5
Q5
2N7002W-7-F
2N7002W-7-F
+1.5V_SUS +1.5V_CPU
2
+VCC_GFX_CORE
C309
C309
10U/6.3V_6
10U/6.3V_6
C106
C106
10U/10V/0805
10U/10V/0805
C79
C79
10U/6.3V_6
10U/6.3V_6
C20
C20
1U/6.3V
1U/6.3V
VR_SVID_ALERT# 40VR_SVID_DATA 40
U13G
U13G
AT24
VAXG1
AT23
VAXG2
AT21
VAXG3
AT20
VAXG4
AT18
VAXG5
AT17
VAXG6
AR24
VAXG7
AR23
VAXG8
AR21
VAXG9
AR20
VAXG10
AR18
VAXG11
AR17
VAXG12
AP24
AM24
AM23
AM21
AM20
AM18
AM17
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
CPU-989P-rPGA
CPU-989P-rPGA
C310
C310
C99
C99
10U/6.3V_6
10U/6.3V_6
10U/10V/0805
10U/10V/0805
C111
C111
10U/10V/0805
10U/10V/0805
C306
C306
10U/10V/0805
10U/10V/0805
C22
C22
1U/6.3V
1U/6.3V
+5V_ALW +15V_ALW
12
R77
R77
10K_4
10K_4
31
2
Q7
Q7
R86
R86
2N7002W-7-F
2N7002W-7-F
*10K_4_NC
*10K_4_NC
SVID ALERT
AK35
AK34
AL1
SM_VREF
CAD Note: +VDDR_REF_CPU should
have 10 mil trace width
AF7
VDDQ1
AF4
VDDQ2
AF1
VDDQ3
AC7
VDDQ4
AC4
VDDQ5
AC1
VDDQ6
Y7
VDDQ7
Y4
VDDQ8
Y1
VDDQ9
U7
VDDQ10
U4
VDDQ11
U1
VDDQ12
P7
VDDQ13
P4
VDDQ14
P1
VDDQ15
M27
VCCSA1
M26
VCCSA2
L26
VCCSA3
J26
VCCSA4
J25
VCCSA5
J24
VCCSA6
H26
VCCSA7
H25
VCCSA8
H23
C22
FC_C22
VCCSA_VID1
C24
VCCSA_VID0
VCCSA_VID1
S3 Power reduce
PS_S3CNTRL_S
C80
C80
*0.01U/25V/X7R_4_NC
*0.01U/25V/X7R_4_NC
1
TP2TP2
TP3TP3
+VDDR_REF_CPU
C72
C72
10U/6.3V_6
10U/6.3V_6
C54
C54
10U/6.3V_6
10U/6.3V_6
C27
C27
10U/6.3V_6
10U/6.3V_6
VCCSA_SENSE 42
R76 100_4R76 100_4
R78 100_4R78 100_4
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
R19 10K/F_4R19 10K/F_4
R12 *10K/F_4_NCR12 *10K/F_4_NC
R11 10K/F_4R11 10K/F_4
+VCC_GFX_CORE
+VDDR_REF_CPU
CPU MCH
SNB 35W: 5A
10uF x 6
C28
C28
C76
C76
10U/6.3V_6
10U/6.3V_6
C83
C83
C285
C285
C31
C31
10U/6.3V_6
10U/6.3V_6
VCCSA_VID1 42
1 2
1 2
1 2
+1.5V_SUS +1.5V_CPU
10A
FDMS7670Q3FDMS7670
9
8
762
5
C55
C55
4700P/25V
4700P/25V
4
PS_S3CNTRL_S
VCC_AXG_SENSE 40
VSS_AXG_SENSE 40
C47
C47
10U/6.3V_6
10U/6.3V_6
+VCCSA_CORE
CPU SA
SNB35W: 6A
10uF x 3
Q3
3
1
R69
R69
*220_NC
*220_NC
31
Take care Q3509 Vgs(MAX)=2.5
R81 *0_8_NCR 81 *0_8_NC
3 1
Q6
Q6
*2N7002W-7-F_NC
*2N7002W-7-F_NC
PS_S3CNTRL_S
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Sandy Bridge 4/5
Sandy Bridge 4/5
Sandy Bridge 4/5
1
+1.5V_CPU
+1.05V_PCH
PS_S3CNTRL
2
Q4
Q4
*2N7002W-7-F_NC
*2N7002W-7-F_NC
+VDDR_REF_CPU+DDR_VTTREF
R80
R80
1K/F_4
1K/F_4
V02/R01
V02/R01
V02/R01
+1.5V_CPU
7 51
7 51
7 51
R501
R501
1K/F_4
1K/F_4
C94
C94
0.1U/10V
0.1U/10V
1A
1A
1A
5
Sandy Bridge Processor (GND)
U13H
U13H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
VSS6
AT19
VSS7
AT16
VSS8
D D
C C
B B
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
CPU-989P-rPGA
CPU-989P-rPGA
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
4
U13I
U13I
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
CPU-989P-rPGA
CPU-989P-rPGA
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
3
SMDDR_VREF_DQ0_M316
SMDDR_VREF_DQ1_M317
+3.3V_RUN
check pull high voltage
#439028 PDDG p127
2
1
Sandy Bridge Processor (RESERVED, CFG)
U13E
U13E
L7
RSVD28
AG7
RSVD29
AE7
RSVD30
AK2
RSVD31
W8
RSVD32
AT26
RSVD33
AM33
RSVD34
AJ27
RSVD35
T8
RSVD37
J16
RSVD38
H16
RSVD39
G16
RSVD40
AR35
RSVD41
AT34
RSVD42
AT33
RSVD43
AP35
RSVD44
AR34
RSVD45
B34
RSVD46
A33
RSVD47
A34
RSVD48
B35
RSVD49
C35
RSVD50
AJ32
RSVD51
AK32
RSVD52
RSVD54
RSVD55
AH27
AN35
AM35
VCC_DIE_SENSE
#27636 SNB EDS0.7v1 no function.
AT2
RSVD56
AT1
RSVD57
AR1
RSVD58
B1
KEY
For rPGA socket, RSVD59 pin should be left NC
TP29TP29
TP27TP27
TP9TP9
TP1TP1
TP6TP6
TP5TP5
R32
R32
*1K/J_4_NC
*1K/J_4_NC
R15 *10K_4_NCR15 *10K_4_NC
12
CFG2
R42
R42
*1K/J_4_NC
*1K/J_4_NC
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
B4
RSVD6
D1
RSVD7
F25
RSVD8
F24
RSVD9
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
J20
B18
A19
J15
CPU-989P-rPGA
CPU-989P-rPGA
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
VCCIO_SEL
RSVD27
RESERVED
RESERVED
CFG[6:5] (PCIE Port Bifurcation Straps)
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Processor Strapping
A A
5
CFG2
(PCI-E Static x16 Lane Reversal)
CFG3
(PCI-E Static x4 Lane Reversal)
CFG4
(DP Presence Strap)
4
Normal Operation Lane Reversed
Normal Operation Lane Reversed
Disable; No physical DP attached to eDP
The CFG signals have a default value of '1' if not terminated on the board.
1 0
Enable; An ext DP device is connected to eDP
3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CFG2
R92 1K/F_4R92 1K/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Sandy Bridge 5/5
Sandy Bridge 5/5
Sandy Bridge 5/5
Wednesday, January 19, 2011
Wednesday, January 19, 2011
Wednesday, January 19, 2011
V02/R01
V02/R01
V02/R01
1
8 51
8 51
8 51
1A
1A
1A
5
DMI_RXN04
DMI_RXN14
DMI_RXN24
DMI_RXN34
D D
DMI_ZCOMP, DMI_IRCOMP 4mil
C C
Take care of timing
B B
DMI_RXP04
DMI_RXP14
DMI_RXP24
DMI_RXP34
DMI_TXN04
DMI_TXN14
DMI_TXN24
DMI_TXN34
DMI_TXP04
DMI_TXP14
DMI_TXP24
DMI_TXP34
112
112
112
2
2
2
DMI_COMP
DMI2RBIAS
ME_SUS_PWR_ACK
SYS_RESET#
SYS_PWROK_R
PWROK_R
APWROK_R
RSMRST#
ME_SUS_PWR_ACK
AC_PRESENT
PM_BATLOW#
PM_RI#
+1.05V_PCH
SYS_PWROK
EC_PWROK25
HWPG25,33,34
PM_DRAM_PWRGD5
RSMRST#25
ME_SUS_PWR_ACK25
SIO_PWRBTN#25
AC_PRESENT25
R197 49.9/F_4R197 49.9/F_4
R194 750/F_4R194 750/F_4
R115 SJ_0402R115 SJ_0402
R100 SJ_0402R100 SJ_0402
R113 SJ_0402R113 SJ_0402
4
3
Cougar Point (DMI,FDI,PM)
U15C
U15C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
H20
E10
A10
CougarPoint_R1P0
CougarPoint_R1P0
DSW
PWRBTN#
ACPRESENT / GPIO31
BATLOW# / GPIO72
RI#
+3V_S5
+3V_S5
+3V_S5
DSW
+3V_S5
+3V_S5
DMI
FDI
DMI
FDI
+3V
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
System Power Management
+3V_S5
SLP_LAN# / GPIO29
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
DPWROK
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
DSWVRMEN
A18
RSMRST#
E22
PCIE_WAKE#
B9
CLKRUN#
N3
G8
SUSCLK
N14
D10
SLP_S4#
H4
F4
G10
W/O support iAMT
G16
W/O support Deep Sx
AP14
SIO_SLP_LAN#
K14
FDI_TXN0 4
FDI_TXN1 4
FDI_TXN2 4
FDI_TXN3 4
FDI_TXN4 4
FDI_TXN5 4
FDI_TXN6 4
FDI_TXN7 4
FDI_TXP0 4
FDI_TXP1 4
FDI_TXP2 4
FDI_TXP3 4
FDI_TXP4 4
FDI_TXP5 4
FDI_TXP6 4
FDI_TXP7 4
FDI_INT 4
FDI_FSYNC0 4
FDI_FSYNC1 4
FDI_LSYNC0 4
FDI_LSYNC1 4
PCIE_WAKE# 26,28
CLKRUN# 25
TP17TP17
SIO_SLP_S5# 25
T1T1
W/O support
SIO_SLP_S3# 7,25,39
H_PM_SYNC 5
T2T2
W/O support iAMT
2
1
PCH Pull-high/low(CLG)
+3.3V_SUS
PM_RI#
PM_BATLOW#
PCIE_WAKE#
10k, Follow HR_DG_v1.0 P200(Intel)
ME_SUS_PWR_ACK
AC_PRESENT
SIO_SLP_LAN#
CLKRUN#
SYS_RESET#
RSMRST#
SYS_PWROK_R
On Die DSW VR Enable
High = Enable (Default)
Low = Disable
R338 10K_4R338 10K_4
R156 8.2K/J_4R156 8.2K/J_4
R336 10K_4R336 10K_4
R176 10K_4R176 10K_4
R196 10K_4R196 10K_4
R158 10K_4R158 10K_4
DSWVRMEN
R128 8.2K/J_4R128 8.2K/J_4
R319 8.2K/J_4R319 8.2K/J_4
R195 10K_4R195 10K_4
R114 10K_4R114 10K_4
+RTC_CELL
R189
R189
330K_4
330K_4
R183
R183
*330K/J_4_NC
*330K/J_4_NC
+3.3V_RUN
U4
U4
4
TC7SH08FU
TC7SH08FU
+3.3V_SUS
3 5
2
1
C109
C109
0.1U/10V
0.1U/10V
EC_PWROK
R94
R94
100K_4
100K_4
2
IMVP_PWRGD 25,40
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
PROJECT :
Cougar Point 1/7
Cougar Point 1/7
Cougar Point 1/7
V02/R01
V02/R01
V02/R01
1
9 51
9 51
9 51
1A
1A
1A
System PWR_OK(CLG)
A A
5
4
SYS_PWROK5
3
SYS_PWROK
5
4
3
2
1
Cougar Point (LVDS,DDI)
U15D
U15D
LVDS_IBG
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
R357 20/F_4R357 20/F_4
R356 20/F_4R356 20/F_4
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
CougarPoint_R1P0
CougarPoint_R1P0
LVDS
LVDS
CRT
CRT
INT_CRT_HSYNC_R
INT_CRT_VSYNC_R
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
PANEL_BKEN25
ENVDD25
BIA_PWM18
D D
LCD_DDCCLK18
LCD_DDCDAT18
R224 2.37K/F_4R224 2.37K/F_4
T3T3
INT_TXLCLKOUTN18
INT_TXLCLKOUTP18
INT_TXLOUTN018
INT_TXLOUTN118
INT_TXLOUTN218
INT_TXLOUTP018
INT_TXLOUTP118
INT_TXLOUTP218
C C
INT_CRT_BLU19
INT_CRT_GRE19
INT_CRT_RED19
INT_DDCCLK19
INT_DDCDAT19
B B
INT_CRT_HSYNC19
INT_CRT_VSYNC19
LCD_DDCCLK
LCD_DDCDAT
DIS_L_CTRL_CLK
DIS_L_CTRL_DATA
LVDS_VBG
INT_CRT_BLU
INT_CRT_GRE
INT_CRT_RED
INT_CRT_HSYNC_R
INT_CRT_VSYNC_R
DAC_IREF
R229
R229
1K_4
1K_4
R place close to PCH
R237 150/F_4R237 150/F_4
C345 22PC345 22P
R240 150/F_4R240 150/F_4
C346 22PC346 22P
R238 150/F_4R238 150/F_4
C347 22PC347 22P
LCD_DDCDAT
A A
LCD_DDCCLK
DIS_L_CTRL_CLK
DIS_L_CTRL_DATA
ENVDD
R358 2.2K_4R358 2.2K_4
R219 2.2K_4R219 2.2K_4
R232 2.2K_4R232 2.2K_4
R211 2.2K_4R211 2.2K_4
R236 100K_4R236 100K_4
INT_CRT_BLU
INT_CRT_GRE
INT_CRT_RED
+3.3V_RUN
12
5
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
4
HDMI_SCL 20
HDMI_SDA 20
INT_DP_HPD 20
INT_HDMI_TXN2 20
INT_HDMI_TXP2 20
INT_HDMI_TXN1 20
INT_HDMI_TXP1 20
INT_HDMI_TXN0 20
INT_HDMI_TXP0 20
INT_HDMI_TXCN 20
INT_HDMI_TXCP 20
INT. HDMI
3
Cougar Point (GND)
U15I
U15I
AY4
VSS[159]
AY42
VSS[160]
AY46
VSS[161]
AY8
VSS[162]
B11
VSS[163]
B15
VSS[164]
B19
VSS[165]
B23
VSS[166]
B27
VSS[167]
B31
VSS[168]
B35
VSS[169]
B39
VSS[170]
B7
VSS[171]
F45
VSS[172]
BB12
VSS[173]
BB16
VSS[174]
BB20
VSS[175]
BB22
VSS[176]
BB24
VSS[177]
BB28
VSS[178]
BB30
VSS[179]
BB38
VSS[180]
BB4
VSS[181]
BB46
VSS[182]
BC14
VSS[183]
BC18
VSS[184]
BC2
VSS[185]
BC22
VSS[186]
BC26
VSS[187]
BC32
VSS[188]
BC34
VSS[189]
BC36
VSS[190]
BC40
VSS[191]
BC42
VSS[192]
BC48
VSS[193]
BD46
VSS[194]
BD5
VSS[195]
BE22
VSS[196]
BE26
VSS[197]
BE40
VSS[198]
BF10
VSS[199]
BF12
VSS[200]
BF16
VSS[201]
BF20
VSS[202]
BF22
VSS[203]
BF24
VSS[204]
BF26
VSS[205]
BF28
VSS[206]
BD3
VSS[207]
BF30
VSS[208]
BF38
VSS[209]
BF40
VSS[210]
BF8
VSS[211]
BG17
VSS[212]
BG21
VSS[213]
BG33
VSS[214]
BG44
VSS[215]
BG8
VSS[216]
BH11
VSS[217]
BH15
VSS[218]
BH17
VSS[219]
BH19
VSS[220]
H10
VSS[221]
BH27
VSS[222]
BH31
VSS[223]
BH33
VSS[224]
BH35
VSS[225]
BH39
VSS[226]
BH43
VSS[227]
BH7
VSS[228]
D3
VSS[229]
D12
VSS[230]
D16
VSS[231]
D18
VSS[232]
D22
VSS[233]
D24
VSS[234]
D26
VSS[235]
D30
VSS[236]
D32
VSS[237]
D34
VSS[238]
D38
VSS[239]
D42
VSS[240]
D8
VSS[241]
E18
VSS[242]
E26
VSS[243]
G18
VSS[244]
G20
VSS[245]
G26
VSS[246]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
CougarPoint_R1P0
CougarPoint_R1P0
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
2
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
U15H
U15H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
VSS[19]
AD10
VSS[20]
AD11
VSS[21]
AD12
VSS[22]
AD13
VSS[23]
AD19
VSS[24]
AD24
VSS[25]
AD26
VSS[26]
AD27
VSS[27]
AD33
VSS[28]
AD34
VSS[29]
AD36
VSS[30]
AD37
VSS[31]
AD38
VSS[32]
AD39
VSS[33]
AD4
VSS[34]
AD40
VSS[35]
AD42
VSS[36]
AD43
VSS[37]
AD45
VSS[38]
AD46
VSS[39]
AD8
VSS[40]
AE2
VSS[41]
AE3
VSS[42]
AF10
VSS[43]
AF12
VSS[44]
AD14
VSS[45]
AD16
VSS[46]
AF16
VSS[47]
AF19
VSS[48]
AF24
VSS[49]
AF26
VSS[50]
AF27
VSS[51]
AF29
VSS[52]
AF31
VSS[53]
AF38
VSS[54]
AF4
VSS[55]
AF42
VSS[56]
AF46
VSS[57]
AF5
VSS[58]
AF7
VSS[59]
AF8
VSS[60]
AG19
VSS[61]
AG2
VSS[62]
AG31
VSS[63]
AG48
VSS[64]
AH11
VSS[65]
AH3
VSS[66]
AH36
VSS[67]
AH39
VSS[68]
AH40
VSS[69]
AH42
VSS[70]
AH46
VSS[71]
AH7
VSS[72]
AJ19
VSS[73]
AJ21
VSS[74]
AJ24
VSS[75]
AJ33
VSS[76]
AJ34
VSS[77]
AK12
VSS[78]
AK3
VSS[79]
CougarPoint_R1P0
CougarPoint_R1P0
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
PROJECT :
Cougar Point 2/7
Cougar Point 2/7
Cougar Point 2/7
V02/R01
V02/R01
V02/R01
1
AK38
VSS[80]
AK4
VSS[81]
AK42
VSS[82]
AK46
VSS[83]
AK8
VSS[84]
AL16
VSS[85]
AL17
VSS[86]
AL19
VSS[87]
AL2
VSS[88]
AL21
VSS[89]
AL23
VSS[90]
AL26
VSS[91]
AL27
VSS[92]
AL31
VSS[93]
AL33
VSS[94]
AL34
VSS[95]
AL48
VSS[96]
AM11
VSS[97]
AM14
VSS[98]
AM36
VSS[99]
AM39
VSS[100]
AM43
VSS[101]
AM45
VSS[102]
AM46
VSS[103]
AM7
VSS[104]
AN2
VSS[105]
AN29
VSS[106]
AN3
VSS[107]
AN31
VSS[108]
AP12
VSS[109]
AP19
VSS[110]
AP28
VSS[111]
AP30
VSS[112]
AP32
VSS[113]
AP38
VSS[114]
AP4
VSS[115]
AP42
VSS[116]
AP46
VSS[117]
AP8
VSS[118]
AR2
VSS[119]
AR48
VSS[120]
AT11
VSS[121]
AT13
VSS[122]
AT18
VSS[123]
AT22
VSS[124]
AT26
VSS[125]
AT28
VSS[126]
AT30
VSS[127]
AT32
VSS[128]
AT34
VSS[129]
AT39
VSS[130]
AT42
VSS[131]
AT46
VSS[132]
AT7
VSS[133]
AU24
VSS[134]
AU30
VSS[135]
AV16
VSS[136]
AV20
VSS[137]
AV24
VSS[138]
AV30
VSS[139]
AV38
VSS[140]
AV4
VSS[141]
AV43
VSS[142]
AV8
VSS[143]
AW14
VSS[144]
AW18
VSS[145]
AW2
VSS[146]
AW22
VSS[147]
AW26
VSS[148]
AW28
VSS[149]
AW32
VSS[150]
AW34
VSS[151]
AW36
VSS[152]
AW40
VSS[153]
AW48
VSS[154]
AV11
VSS[155]
AY12
VSS[156]
AY22
VSS[157]
AY28
VSS[158]
10 51
10 51
10 51
1A
1A
1A
5
Cougar Point (HDA,JTAG,SATA)
C324 18P/50V/C0G_4C324 18P/50V/C0G_4
R342
Y1
Y1
32.786KHz
32.786KHz
PCH_MELOCK25
PCH_SPI_CLK29
PCH_SPI_CS0#29
PCH_SPI_SI29
2 1
+RTC_CELL
ACZ_SPKR26
ACZ_SDIN026
SMIB26
PCH_SPI_CLK
C98
C98
*22P_NC
*22P_NC
50
50
NPO
NPO
PCH_SPI_SO29
D D
C C
B B
C323 18P/50V/C0G_4C323 18P/50V/C0G_4
ACZ_BITCLK_AUDIO26
ACZ_SYNC_AUDIO26
ACZ_RST#_AUDIO25,26
ACZ_SDOUT_AUDIO26
R342
10M/J_4
10M/J_4
R198 1M/J_4R198 1M/J_4
C326 27P
C326 27P
R344 33_4R344 33_4
R217 33_4R217 33_4
R209 33_4R209 33_4
R346 1K_4R346 1K_4
R348 33_4R348 33_4
TP16TP16
TP14TP14
TP11TP11
TP35TP35
PCH_SPI_CLK
RTC_X1
RTC_X2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INTVRMEN
50
50
ACZ_BITCLK_R
ACZ_SYNC_R
ACZ_SPKR
ACZ_RST#_R
TP19TP19
ACZ_SDOUT
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
112
R95 SJ_0402R95 SJ_0402
TP15TP15
PCH_SPI_SO
2
4
U15A
U15A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
CougarPoint_R1P0
CougarPoint_R1P0
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
+3V
+3V
+3V_S5
+3V
+3V
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
LPC
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA 6G
SATA 6G
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
C38
A38
B37
C37
D36
LPC_LDRQ0#
E36
LPC_LDRQ1#
K36
IRQ_SERIRQ
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
SATA_COMP
Y10
AB12
SATA3_COMP
AB13
SATA3_RBIAS
AH1
PCH_SATA_LED#
P3
V14
P1
Move to Page12
3
TP21TP21
TP20TP20
Move Caps to CONN side
R170 37.4/F_4R170 37.4/F_4
R177 49.9/F_4R177 49.9/F_4
R329 750/F_4R329 750/F_4
SATA0GPPCH_SPI_SI
LPC_LAD0 25,26
LPC_LAD1 25,26
LPC_LAD2 25,26
LPC_LAD3 25,26
LPC_LFRAME# 25,26
IRQ_SERIRQ 25
SATA_RXN0 24
SATA_RXP0 24
SATA_TXN0 24
SATA_TXP0 24
SATA_RXN1 24
SATA_RXP1 24
SATA_TXN1 24
SATA_TXP1 24
SATA_RXN4 21
SATA_RXP4 21
SATA_TXN4 21
SATA_TXP4 21
+1.05V_PCH
PCH_SATA_LED# 31
BBS_BIT0 12
SATA HDD/SSD
SATA ODD
ESATA
Take care while using
GPIO19 for Hot Plug
function
2
IRQ_SERIRQ
SATA0GP
1
R312 10K_4R312 10K_4
1 2
R118 10K_4R118 10K_4
1 2
+3.3V_RUN
PCH JTAG Debug (CLG)
5% fine (Intel), 210->200 (PDDG, Intel)
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TCK
R8356 change 4.7kohm
to 51ohm 5/3 (Intel)
+RTC_CELL
MP remove(Intel)
R108 200_4R108 200_4
R109 200_4R109 200_4
R321 200_4R321 200_4
R159 100_4R159 100_4
1 2
R110 100_4R110 100_4
1 2
R322 100_4R322 100_4
1 2
R147 51_4R147 51_4
R182 20KR182 20K
R192 20KR192 20K
+3.3V_SUS
RTC_RST#
SRTC_RST#
C162
C162
1U/6.3V
1U/6.3V
C173
C173
1U/6.3V
1U/6.3V
PCH Strap Table
Pin Name Strap description
SPKR
HDA_SDO
A A
Del 0510
INTVRMEN
HDA_SYNC
No reboot mode setting PWROK
Integrated 1.05V VRM enable ALWAYS
On-Die PLL VR Volatge Select RSMRST
5
Sampled
PWROKFlash Descriptor Security
Configuration
0 = Default (weak pull-down 20K)
1 = Setting to No-Reboot mode
0 = Default (weak pull-down 20K)
1 = Override
Remove SPI_MOSI from PCH strapping, HR_C/L_v0.91
Should be always pull-up
0 = Support by 1.8V (weak PD)
1 = Support by 1.5V
4
+3.3V_SUS
+3.3V_SUS
+RTC_CELL
+3.3V_SUS
note
R146 *1K_4_NCR146 *1K_4_NC
R349 *1K_4_NCR349 *1K_4_NC
R181 330K_4R181 330K_4
R212 1K_4R212 1K_4
3
ACZ_SPKR
ACZ_SDOUT
PCH_INTVRMEN
ACZ_SYNC_R
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
2
Wednesday, January 19, 2011
PROJECT :
Cougar Point 3/7
Cougar Point 3/7
Cougar Point 3/7
V02/R01
V02/R01
V02/R01
1
11 51
11 51
11 51
1A
1A
1A
5
PCI/USBOC# Pull-up(CLG)
+3.3V_RUN
R2308.2K/J_4 R2308.2K/J_4
R2158.2K/J_4 R2158.2K/J_4
R2228.2K/J_4 R2228.2K/J_4
R2168.2K/J_4 R2168.2K/J_4
R22510K_4 R22510K_4
R3528.2K/J_4 R3528.2K/J_4
R36410K_4 R36410K_4
D D
USB_OC1#
USB_OC4#
USB_OC2#
C C
PCIE_MCARD2_DET#26
B B
PCH_IRQH_GPIO224
SATA_ODD_MD#24
KB_LED_DET30
WWAN_RADIO_DIS#26
Check with BIOS program
or not? (have to be not)
CLK_33M_LPC26
CLK_33M_KBC25
CLK_PCI_FB13
R22610K_4 R22610K_4
R249*10K_4_NC R249*10K_4_NC
R250*10K_4_NC R250*10K_4_NC
R354*10K_4_NC R354*10K_4_NC
+3.3V_SUS
10
9
8
7 4
R340
R340
10KX8
10KX8
R37310K_4 R37310K_4
R37410K_4 R37410K_4
R37510K_4 R37510K_4
Check CLKOUT if Skew requirement?
A A
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCIE_MCARD2_DET#
PCH_IRQH_GPIO2
SATA_ODD_MD#
WWAN_RADIO_DIS#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
USB_OC0#
1
SIO_EXT_W AKE#
2
USB_OC5#USB_OC6#
3
USB_OC3#
56
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCIE_MCARD2_DET#
TP18TP18
R360 22_4R360 22_4
R359 22_4R359 22_4
R221 22_4R221 22_4
CLK_33M_LPC
C335*10P/50V/C0G_4_NC C335*10P/50V/C0G_4_NC
CLK_33M_KBC
C33418P C33418P
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
BBS_BIT1
TP36TP36
PCH_IRQH_GPIO2
SATA_ODD_MD#
KB_LED_DET
WWAN_RADIO_DIS#
PCI_PME#
PCI_PLTRST#
CLK_33M_LPC_R
CLK_33M_KBC_R
Cougar Point-M (PCI,USB,NVRAM)
U15E
U15E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
TP25
BC30
TP26
BE32
TP27
BJ32
TP28
BC28
TP29
BE30
TP30
BF32
TP31
BG32
TP32
AV26
TP33
BB26
TP34
AU28
TP35
AY30
TP36
AU26
TP37
AY26
TP38
AV28
TP39
AW30
TP40
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
CougarPoint_R1P0
CougarPoint_R1P0
4
RSVD
RSVD
+5V
+5V
+5V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
PCI
PCI
USB
USB
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
USB_BIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
SIO_EXT_W AKE#CLK_PCI_FB_R
3
USBP1N 21
USBP1P 21
USBP2N 22
USBP2P 22
USBP4N 26
USBP4P 26
USBP5N 26
USBP5P 26
USBP8N 23
USBP8P 23
USBP9N 28
USBP9P 28
USBP10N 30
USBP10P 30
USBP11N 18
USBP11P 18
R207 22.6/F_4R207 22.6/F_4
USB_OC0# 21
USB_OC1# 22
SIO_EXT_W AKE# 25
USB2.0 &ESATA LEFT
USB2.0 LEFT
WLAN
WWAN
CARD READER
Express card
Biometric
Camera
2
PLTRST#(CLG)
PCI_PLTRST#
Pin Name Strap description
GNT2# / GPIO53
GNT3# / GPIO55
GNT1# / GPIO51
GPIO19
BBS_BIT1
BBS_BIT011
DF_TVS
ESI strap (Server only) PWROK
Top-Block Swap Override
Boot BIOS Selection 1 [bit-1]
Boot BIOS Selection 0 [bit-0]
R233 *1K_4_NCR233 *1K_4_NC
R315 *1K_4_NCR315 *1K_4_NC
DMI and FDI Tx/Rx
Termination Voltage
R327 2.2K_4R327 2.2K_4
R326 SJ_0402R326 SJ_0402
2
112
+3.3V_SUS
2
1
U7
U7
3 5
*TC7SH08FU_NC
*TC7SH08FU_NC
112
R120 SJ_0402R120 SJ_0402
+1.8V_RUN
DF_TVS 14
H_SNB_IVB# 5
4
2
Sampled
PWROK
PWROK
PWROK
PWROK
1
C118
C118
*0.1U/10V_NC
*0.1U/10V_NC
PLTRST#
10K_4
10K_4
R119
R119
PLTRST# 5,25,26,28
Configuration
Should not be pull-down
(weak pull-up 20K)
0 = "top-block swap" mode
1 = Default (weak pull-up 20K)
Bit 1Bit 0
Default weak pull-up on GNT0/1#
[Need external pull-down for LPC
BIOS]
weak pull-down 20kohm
CheckList_1.0 p58; HR_v1.0 p450
11
00
Boot Location
SPI
LPC
*
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, January 20, 2011
Date: Sheet of
Thursday, January 20, 2011
Date: Sheet of
5
4
3
2
Thursday, January 20, 2011
PROJECT :
Cougar Point 4/7
Cougar Point 4/7
Cougar Point 4/7
V02/R01
V02/R01
V02/R01
1
12 51
12 51
12 51
1A
1A
1A
5
Cougar Point-M (PCI-E,SMBUS,CLK)
WLAN
WWAN
D D
USB 3.0
LAN
Express card
PCIE_RXN126
PCIE_RXP126
PCIE_TXN126
PCIE_TXP126
PCIE_RXN226
PCIE_RXP226
PCIE_TXN226
PCIE_TXP226
PCIE_RXN326
PCIE_RXP326
PCIE_TXN326
PCIE_TXP326
PCIE_RXN526
PCIE_RXP526
PCIE_TXN526
PCIE_TXP526
PCIE_RXN628
PCIE_RXP628
PCIE_TXN628
PCIE_TXP628
C194 0.1U/10VC194 0.1U/10V
C188 0.1U/10VC188 0.1U/10V
C200 0.1U/10VC200 0.1U/10V
C196 0.1U/10VC196 0.1U/10V
C208 0.1U/10VC208 0.1U/10V
C202 0.1U/10VC202 0.1U/10V
C216 0.1U/10VC216 0.1U/10V
C211 0.1U/10VC211 0.1U/10V
C217 0.1U/10VC217 0.1U/10V
C215 0.1U/10VC215 0.1U/10V
PCIE_TXN1_C
PCIE_TXP1_C
PCIE_TXN2_C
PCIE_TXP2_C
PCIE_TXN3_C
PCIE_TXP3_C
PCIE_TXN5_C
PCIE_TXP5_C
PCIE_TXN6_C
PCIE_TXP6_C
Card reader
C C
WLAN
WWAN
USB3.0
B B
LAN
CLK_PCIE_WLANN26
CLK_PCIE_WLANP26
PCIE_CLK_REQ0#26
CLK_PCIE_WWANN26
CLK_PCIE_WWANP26
PCIE_CLK_REQ1#26
CLK_PCIE_USB30N26
CLK_PCIE_USB30P26
PCIE_CLK_REQ2#26
CLK_PCIE_LANN26
CLK_PCIE_LANP26
PCIE_CLK_REQ4#26
CLK_PCIE_EXPN28
CLK_PCIE_EXPP28
PCIE_CLK_REQ5#28
PCIE_CLK_REQ0#
PCIE_CLK_REQ1#
PCIE_CLK_REQ2#
PCIE_CLK_REQ3#
PCIE_CLK_REQ4#
PCIE_CLK_REQ5#
Express card
PEG_B_CLKRQ#
PCIE_CLK_REQ6#
PCIE_CLK_REQ7#
CLK_PCIE_XDPN
XDP
A A
5
CLK_PCIE_XDPP
BG34
BJ34
AV32
AU32
BE34
BF34
BB32
AY32
BG36
BJ36
AV34
AU34
BF36
BE36
AY34
BB34
BG37
BH37
AY36
BB36
BJ38
BG38
AU36
AV36
BG40
BJ40
AY40
BB40
BE38
BC38
AW38
AY38
Y40
Y39
AB49
AB47
AA48
AA47
V10
Y37
Y36
Y43
Y45
V45
V46
AB42
AB40
V40
V42
T13
V38
V37
K12
AK14
AK13
L12
L14
4
U15B
U15B
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
CLKOUT_PCIE0N
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P
PCIECLKRQ5# / GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
CLKOUT_PCIE6N
CLKOUT_PCIE6P
PCIECLKRQ6# / GPIO45
CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CougarPoint_R1P0
CougarPoint_R1P0
CLKOUTFLEX0 /GPIO64
CLKOUTFLEX1 /GPIO65
CLKOUTFLEX2 /GPIO66
CLKOUTFLEX3 /GPIO67
4
+3V_S5
PCI-E*
PCI-E*
+3V_S5
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
3
PCH_SMB_ALERT#
SMBCLK
SMBDATA
SML0CLK
CL_CLK1
CL_DATA1
CL_RST1#
XTAL25_IN
E12
SMBCLK
H14
SMBDATA
C9
A12
SML0CLK
C8
SML0DATA
G12
PCH_GPIO74
C13
SMB_CLK_ME1
E14
SMB_DATA_ME1
M16
M7
T11
P10
PEG_A_CLKRQ#
M10
AB37
AB38
AV22
AU22
AM12
AM13
CLK_DMIN
BF18
CLK_DMIP
BE18
BJ30
BG30
CLK_BUF_DREFCLKN
G24
CLK_BUF_DREFCLKP
E24
CLK_BUF_DREFSSCLKN
AK7
CLK_BUF_DREFSSCLKP
AK5
CLK_PCH_14M
K45
CLK_PCI_FB
H45
XTAL25_IN
V47
XTAL25_OUT
V49
XCLK_RCOMP
Y47
CLK_48M_CARD_R
K43
CLK_VGA_27M_R
F47
CLK_FLEX2
H47
CLK_VGA_27M_SS
K49
SMBCLK 28
R3391K_4 R3391K_4
R345 10K_4R345 10K_4
R239 90.9/F_4R239 90.9/F_4
SMBDATA 28
+3.3V_SUS
DDR_HVREF_RST_PCH 5
CLK_CPU_BCLKN 5
CLK_CPU_BCLKP 5
CLK_DP_N 5
CLK_DP_P 5
1 2
C225 *10P_NCC225 *10P_NC
CLK_PCI_FB 12
C224 *10P_NCC224 *10P_NC
1 2
R234 22_4R234 22_4
T4T4
T8T8
T7T7
1 2
10k -> 1k ohm (CRB,Dell)
R355
R355
1M/J_4
1M/J_4
1 2
C332 33P
+1.05V_PCH
C332 33P
CLK_48M_CARD 23
+3V_S5
+3V_S5
+3V_S5
CLOCKS
CLOCKS
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
+3V_S5
+3V_S5
Link
Link
PEG_A_CLKRQ# / GPIO47
+3V
+3V
+3V
+3V
FLEX CLOCKS
FLEX CLOCKS
Configurable as a GPIO or as a programmable output clock
which can be configured as one of the following:
33 /27 /48/ 14.318 MHz / DC Output logic ‘0’
‧
SML0DATA
SML1CLK / GPIO58
SML1DATA / GPIO75
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
unsupported clock output value (Default) / 27/ 14.318 MHz output to SIO/EC /48/24 MHz
33/25/27/48/24/14.318 MHz / DC Output logic ‘0’
‧
27/14.318 output to SIO/48/24 MHz (Default)
‧
3
2
C331 27P
C331 27P
50
50
Y2
25MHzY225MHz
1 2
50
50
2
1
SMBCLK
SMBDATA
+3.3V_RUN
Q14
Q14
2N7002W -7-F
2N7002W -7-F
3 1
Q16
Q16
2N7002W -7-F
2N7002W -7-F
SMB_CLK_ME1
+3.3V_SUS
SMB_DATA_ME1
2
3 1
Q20
Q20
2N7002W -7-F
2N7002W -7-F
SMBus/Pull-up(CLG)
R151
R151
R140
R140
2.2K_4
2.2K_4
2.2K_4
2.2K_4
2
31
2
Q17
Q17
2
2N7002W -7-F
2N7002W -7-F
31
WLAN_SCLK 16,17,24,26
WLAN_SDATA 16,17,24,26
SMBCLK1 25
SMBDAT1 25
Stuff for Integrated CLK Gen Mode
CLK_DMIN
CLK_DMIP
CLK_BUF_DREFCLKN
CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP
CLK_PCH_14M
R185 10K_4R185 10K_4
R186 10K_4R186 10K_4
R200 10K_4R200 10K_4
R199 10K_4R199 10K_4
R164 10K_4R164 10K_4
R152 10K_4R152 10K_4
R235 10K_4R235 10K_4
CLK_REQ/Strap Pin(CLG)
+3.3V_SUS
PCIE_CLK_REQ0#
PCIE_CLK_REQ3#
PCIE_CLK_REQ4#
PCIE_CLK_REQ5#
PCIE_CLK_REQ6#
PCIE_CLK_REQ7#
PEG_B_CLKRQ#
PCIE_CLK_REQ1#
PCIE_CLK_REQ2#
PEG_A_CLKRQ#
PCH_GPIO74
PCH_SMB_ALERT#
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SMB_CLK_ME1
SMB_DATA_ME1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
PROJECT :
Cougar Point 5/7
Cougar Point 5/7
Cougar Point 5/7
R144 2.2K_4R144 2.2K_4
R161 2.2K_4R161 2.2K_4
R331 2.2K_4R331 2.2K_4
R172 2.2K_4R172 2.2K_4
R180 2.2K_4R180 2.2K_4
R175 2.2K_4R175 2.2K_4
V02/R01
V02/R01
V02/R01
1
R32010K_4 R32010K_4
R33310K_4 R33310K_4
R16910K_4 R16910K_4
R15710K_4 R15710K_4
R13010K_4 R13010K_4
R15310K_4 R15310K_4
R32410K_4 R32410K_4
+3.3V_RUN
R31710K_4 R31710K_4
R13210K_4 R13210K_4
+3.3V_SUS
R12510K_4 R12510K_4
+3.3V_SUS
R17310K_4 R17310K_4
R17910K_4 R17910K_4
13 51
13 51
13 51
1A
1A
1A
5
BMBUSY#
SIO_EXT_SMI#25
D D
PCIE_MCARD1_DET#26
SIO_EXT_SCI#25
USB_MCARD2_DET#26
USB_MCARD1_DET#26
DO NOT program this pin (BIOS)
C C
B B
WLAN_RADIO_DIS#26
BT_RADIO_DIS#26
FFS_INT224
MODC_EN24
SIO_EXT_SMI#
PCIE_MCARD1_DET#
SIO_EXT_SCI#
ICC_EN#
LAN_PHY_PWR_CTRL
HOST_ALERT#1
SATA4GP
TACH0
GPIO22
ROUSH_PAID_TS_DET#
PLL_ODVR_EN
USB_MCARD2_DET#
USB_MCARD1_DET#
GPIO36
GPIO37
WLAN_RADIO_DIS#
BT_RADIO_DIS#
FFS_INT2
SV_DET
4
3
Cougar Point (GPIO,VSS_NCTF,RSVD)
U15F
U15F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
D40
E16
V13
A44
A45
A46
B47
BD1
BD49
BE1
BE49
BF1
BF49
+3V_S5
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
+3V_S5
GPIO15
U2
SATA4GP / GPIO16
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24 / MEM_LED
DSW
GPIO27
P8
K1
K4
V8
M5
N2
M3
V3
D6
A4
A5
A6
B3
+3V_S5
GPIO28
STP_PCI# / GPIO34
+3V
GPIO35
SATA2GP / GPIO36
SATA3GP / GPIO37
SLOAD / GPIO38
SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48
SATA5GP / GPIO49
+3V_S5
GPIO57
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
CougarPoint_R1P0
CougarPoint_R1P0
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V_S5
+3V
+3V
+3V
+3V
+3V
+3V
+3V
GPIO
GPIO
+3V
+3V
+3V
+3V
+3V_S5
NCTF
NCTF
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#
DF_TVS
CPU/MISC
CPU/MISC
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
T37T37
T36T36
T34T34
T35T35
SIO_A20GATE
SIO_RCIN#
PCH_THRMTRIP#
Pin Name Strap description
GPIO28
R171 390/J_4R171 390/J_4
DF_TVS 12
Chack When Symbol Update (OK)
2
On-die PLL Voltage Regulator RSMRST#
R174 *1K_4_NCR174 *1K_4_NC
Ask Intel, what's
SIO_A20GATE 25
SIO_RCIN# 25
H_PWRGOOD 5
PM_THRMTRIP# 5
the function?
Add Description
in EC GPIO table
(keyboard
controller reset)
+3.3V_SUS
1
Sampled
PLL_ODVR_EN
Configuration
0 = Disable
1 = Enable (Default)
GPIO Pull-up/Pull-down(CLG)
ICC_EN#
LAN_PHY_PWR_CTRL
FFS_INT2
SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_A20GATE
SIO_RCIN#
USB_MCARD2_DET#
USB_MCARD1_DET#
BT_RADIO_DIS#
GPIO22
SATA4GP
PCIE_MCARD1_DET#
GPIO37
TACH0
FFS_INT2
ROUSH_PAID_TS_DET#
R337 10K_4R337 10K_4
R325 10K_4R325 10K_4
R131 *10K_4_NCR131 *10K_4_NC
R227 10K_4R227 10K_4
R218 10K_4R218 10K_4
R129 10K_4R129 10K_4
R148 10K_4R148 10K_4
R318 10K_4R318 10K_4
R112 10K_4R112 10K_4
R127 10K_4R127 10K_4
R143 10K_4R143 10K_4
R116 10K_4R116 10K_4
R347 10K_4R347 10K_4
R111 *10K_4_NCR111 *10K_4_NC
R220 10K_4R220 10K_4
R244 *10K_4_NCR244 *10K_4_NC
R187 10K_4R187 10K_4
Can be del
R149 *10K_4_NCR149 *10K_4_NC
SV_DET
+3.3V_SUS
+3.3V_RUN
R150 100K_4R150 100K_4
Have to Reserve
HOST_ALERT#1
Intel ME Crypto Transport Layer
Security (TLS) cipher suite
A A
SGPIO
4
Confirm with Intel
BMBUSY#
R117 10K_4R117 10K_4
+3.3V_RUN
GPIO36
DMI TERMINATION
VOLTAGE OVERRIDE
R133 200KR133 200K
1 2
Low = Tx, Rx terminated to
same voltage (DC Coupling Mode)
(DEFAULT)
5
+3.3V_RUN
BMBUSY#:(Intel feedback)
Follow CRB checklist, 1K is
for intel BIOS validation purpose.
BMBUSY#:
If not used, require a weak pull-up
(8.2- KΩ to 10 kΩ) to Vcc3_3.
CRB(V1.0)P28: it has 1K PU and
100 ohm on this net for validation purpose.
3
Low = Disable (Default)
High = Enable
MFG-TEST
WLAN_RADIO_DIS#
R323 1K_4R323 1K_4
R316 10K_4R316 10K_4
2
+3.3V_SUS
Quanta Computer Inc.
Quanta Computer Inc.
+3.3V_RUN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Date: Sheet of
Wednesday, January 19, 2011
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Cougar Point 6/7
Cougar Point 6/7
Cougar Point 6/7
1
V02/R01
V02/R01
V02/R01
14 51
14 51
14 51
1A
1A
1A
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