SERVICE GUIDE
ORDER NO.
RRV2055
COMPACT DISC RECORDER
PDR-555RW
PDR-V500
PDR-19RW PDR-509
PIONEER CORPORATION 4-1, Meguro 1-chome, Meguro-ku, Tokyo 153-8654, Japan PIONEER ELECTRONICS SERVICE, INC. P.O. Box 1760, Long Beach, CA 90801-1760, U.S.A. PIONEER ELECTRONIC (EUROPE) N.V. Haven 1087, Keetberglaan 1, 9120 Melsele, Belgium PIONEER ELECTRONICS ASIACENTRE PTE. LTD. 253 Alexandra Road, #04-01, Singapore 159936 c PIONEER CORPORATION 1999
T – IZK AUG. 1999 Printed in Japan
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
CONTENTS
1. BLOCK DIAGRAM ........................................................................................................... |
4 |
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1.1 |
PDR-555RW, PDR-V500 AND PDR-19RW ............................................................................. |
4 |
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1.2 |
PDR-509 ................................................................................................................................... |
6 |
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2. PRODUCT DESCRIPTIONS ........................................................................................... |
8 |
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3. PORT TABLE OF MICROCOMPUTER ........................................................................... |
9 |
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3.1 |
MODE CONTROL OF PDR-555RW, PDR-V500 AND PDR-19RW ......................................... |
9 |
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3.2 |
MECHANISM CONTROL OF PDR-555RW, PDR-V500 AND PDR-19RW ............................ |
11 |
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3.3 |
MODE CONTROL OF PDR-509 ............................................................................................ |
14 |
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3.4 |
MECHANISM CONTROL OF PDR-509 ................................................................................. |
16 |
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4. PIN FUNCTION OF PRINCIPAL IC ............................................................................... |
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4.1 |
AD1893JST ............................................................................................................................ |
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4.2 |
BR93LC46AF ......................................................................................................................... |
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4.3 |
LC89585 ................................................................................................................................. |
20 |
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4.4 |
LH64256CK-70 ....................................................................................................................... |
22 |
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4.5 |
PA9004A ................................................................................................................................ |
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4.6 |
PDJ014A ................................................................................................................................ |
23 |
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4.7 |
PDK033A or PDK041A ........................................................................................................... |
24 |
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4.8 |
AK5340-VS ............................................................................................................................. |
25 |
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4.9 |
PD0236AD .............................................................................................................................. |
26 |
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4.10 PCM1800-1 .......................................................................................................................... |
26 |
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5. RECORDING MECHANISM FOR CD-Rs AND CD-RWs .............................................. |
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5.1 |
DISC ....................................................................................................................................... |
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5.2 |
OVERWRITE RECORDING OF CD-RW ............................................................................... |
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6. PICKUP (KRS-200A) ..................................................................................................... |
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7. CIRCUIT DESCRIPTIONS ............................................................................................ |
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7.1 |
SERVO CIRCUITS ................................................................................................................. |
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7.1.1 |
Control Circuit for the Laser Diode .................................................................................. |
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7.1.2 |
Error Signal Generation Circuit ....................................................................................... |
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7.1.3 Focus Servo .................................................................................................................... |
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7.1.4 |
Tracking Thread Servo ................................................................................................... |
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7.1.5 |
Spindle Servo .................................................................................................................. |
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7.2 |
DEFECT CIRCUIT .................................................................................................................. |
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7.3 |
EFM-DIGITAL PLL ................................................................................................................. |
30 |
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7.4 |
RF DETECTION ..................................................................................................................... |
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7.5 |
MIRROR CIRCUIT ................................................................................................................. |
30 |
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7.6 |
AUDIO CIRCUITS .................................................................................................................. |
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7.6.1 |
Analog Audio Input .......................................................................................................... |
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7.6.2 |
A/D Converter ................................................................................................................. |
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7.6.3 |
Hi-bit IC (PDR-19RW Only) ............................................................................................ |
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7.6.4 |
D/A Converter ................................................................................................................. |
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7.6.5 |
Analog Audio Output Block ............................................................................................. |
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7.7 DIGITAL CIRCUITS ................................................................................................................. |
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7.7.1 |
Digital Audio Interface Input Block .................................................................................. |
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7.7.2 |
Sampling Rate Converter ................................................................................................ |
31 |
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7.7.3 |
Clock-jitter Suppressor Circuit (PDR-509 Only) .............................................................. |
31 |
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7.7.4 |
Data Selector .................................................................................................................. |
31 |
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7.7.5 |
Digital Fader, Level Meter, Mute Blocks ......................................................................... |
31 |
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7.7.6 Memory Control .............................................................................................................. |
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7.7.7 EFM Encoding ................................................................................................................ |
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7.7.8 |
Strategy Control .............................................................................................................. |
32 |
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7.7.9 |
Digital Audio Interface Modulation .................................................................................. |
32 |
2
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
8. DETAILED DESCRIPTIONS OF OUTPUT TERMINAL CONTROL .............................. |
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8.1 |
DGAI (microcomputer,pin 48)and D8CM (microcomputer,pin 53)TERMINAL CONTROL ..... |
32 |
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8.2 |
AGCON (ATIP decoder, pin 52) TERMINAL CONTROL ....................................................... |
32 |
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8.3 |
XCD (ATIP decoder, pin 69) TERMINAL CONTROL ............................................................. |
33 |
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8.4 |
GAINUP1 (ATIP decoder, pin 45) RW/XR (ATIP decoder, pin 66) TERMINAL CONTROL ... |
33 |
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8.5 |
CDROPC (ATIP decoder, pin 46) TERMINAL CONTROL ..................................................... |
33 |
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8.6 |
GAINUP3 (ATIP decoder, pin 47) TERMINAL CONTROL ..................................................... |
33 |
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8.7 |
PHYERS (ATIP decoder, pin 52) TERMINAL CONTROL ...................................................... |
33 |
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8.8 |
SSEL (ATIP decoder, pin 51) TERMINAL CONTROL ........................................................... |
33 |
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8.9 |
ENBL (ATIP decoder, pin 70) TERMINAL CONTROL ........................................................... |
33 |
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9. OPERATION DESCRIPTIONS ...................................................................................... |
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9.1 |
ABOUT POWER ON/OFF ...................................................................................................... |
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9.1.1 |
Power-up (When the power outlet is active) ................................................................... |
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9.1.2 |
Power Down (When the power outlet is not active or power failure occurs) ................... |
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9.2 |
ABOUT SERVO CONTROL ................................................................................................... |
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9.2.1 Seek Track 0 ................................................................................................................... |
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9.2.2 Focus ON ........................................................................................................................ |
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9.2.3 One-Track Jump (Direct Sequence) ............................................................................... |
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9.2.4 One-Track Jump (Auto Sequence) ................................................................................. |
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9.2.5 Ten-Track Jump .............................................................................................................. |
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9.2.6 2N-Track Jump ............................................................................................................... |
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9.2.7 M-Track Move ................................................................................................................. |
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9.2.8 |
Fine Search ..................................................................................................................... |
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9.2.9 |
Loading Control ............................................................................................................... |
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9.2.10 |
Spindle Control ............................................................................................................. |
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9.3 |
ERASING (CD-RW ONLY) ..................................................................................................... |
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9.3.1 |
Last-Track-Erase Operation ............................................................................................ |
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9.3.2 |
All-Track-Erase Operation .............................................................................................. |
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9.3.3 TOC-Erase Operation ..................................................................................................... |
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9.3.4 |
ALL-Disc-Erase Operation .............................................................................................. |
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9.3.5 PCA-Erase Operation ..................................................................................................... |
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9.4 |
RID CODES ............................................................................................................................ |
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9.5 |
DISC JUDGMENT .................................................................................................................. |
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9.5.1 Tentative Judgment Using FZC (Distinguishing Between CD/CD-R and CD-RW) ......... |
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9.5.2 Disc Judgment with Each Type of Disc ........................................................................... |
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9.6 |
SETUP (FLOW) ...................................................................................................................... |
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9.6.1 |
Verification of Disc Judgments ........................................................................................ |
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9.6.2 |
Auto-Adjustments ............................................................................................................ |
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9.6.3 Tracking Error Level Adjustment and Disc Determination .............................................. |
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9.6.4 Recording Power Sweep Mode for Recording Power Calibration .................................. |
41 |
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9.6.5 |
Playback RF Estimating Mode for Recording Power Calibration .................................... |
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10. ABOUT TEST MODE OPERATIONS ......................................................................... |
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11. ERROR CODES ......................................................................................................... |
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11.1 ERROR CODE DISPLAY FOR SERVICE ............................................................................ |
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11.2 ABOUT FULL ERROR CODES ............................................................................................ |
47 |
3
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
1. BLOCK DIAGRAM
1.1 PDR-555RW, PDR-V500 AND PDR-19RW
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IC316 |
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PDK033A |
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RF AMP CIRCUIT |
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STRATEGY |
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IC102, IC101 |
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CONTROL IC |
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A–D |
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RFDC |
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HF |
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Disc (CD, CD-R, CD-RW) |
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RUNNING OPC |
RFOPC |
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WRF |
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CIRCUIT BLOCK |
AOUT |
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A–H |
68–71 |
IC103 |
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RFDC |
IC353 |
PICKUP ASSY |
73–76 |
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FE |
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AK8563 |
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CXD2585Q |
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KRS-200A |
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RF PROCESSOR |
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CD DECODER |
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RFAC |
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FG |
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LD CONTROL |
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SPDL MOTOR |
CIRCUIT |
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SLD MOTOR |
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TE |
IC247 |
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HF |
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PA9004A |
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RFWBL |
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IC205 |
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SERVO AMP |
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PDJ014A |
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ATIP DECODER |
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IC |
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IC351 |
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LOADING |
BA5912AFP-Y |
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MOTOR |
SLD DRIVER |
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SPDL DRIVER |
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IC352
BA5932FP
FCS DRIVER
TRK DRIVER
LOADING DRIVER
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RESET IC |
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IC705 |
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IC701 |
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S-806E |
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PYY1196 |
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PD4968A |
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MODE CONTROL |
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EEPROM |
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MICROCOMPUTER |
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FL DISPLAY |
KEY MATRIX |
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PEL1097 |
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4
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
INPUT
Lch Rch
REC VR
34.5744MHz
17.2872MHz
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IC801 |
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IC401 |
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AK5340-VS |
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PE8001A |
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AD CONVERTER |
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DA CONVERTER |
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ADLRCK |
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DALRCK |
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DADATA |
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ADBCK |
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DABCK |
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ADDATA |
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IC451 |
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PD0236AD |
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IC309 |
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IC301 |
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Hi-Bit |
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BA7082F |
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LH64256CK-70 |
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VCO IC |
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D-RAM |
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PDR-19RW ONLY |
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ADDRESS |
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DATA |
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16.9344MHz |
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CDLRCK, CDBCK |
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IC308 |
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CDDATA, CDTX |
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LC89585 |
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WAVEFORM |
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EFM ENCODER IC |
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SHAPING CIRCUIT |
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RFOPC(60 pin) |
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DIRBCK |
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AOUT(61 pin) |
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DIRLRCK |
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DIRDATA |
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AD0-AD7 |
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IC204 |
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IC311 |
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PD4956A |
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AD1893JST |
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MECH. CONTROL |
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ADDRESS |
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Fs CONVERTER |
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MICROCOMPUTER |
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TEMPERATURE
SENSOR IC
TK11041M
L ch
IC405 OUTPUT
R ch
HP IC406 OUTPUT
Digital in
COAXIAL
Digital in
OPTICAL
Digital out
COAXIAL
Digital out
OPTICAL
MODE DISPLAY LED
D707, D708
IC704
BU2092F
LED DRIVER IC
5
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
1.2 PDR-509
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IC431 |
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PDK041A |
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RF AMP CIRCUIT |
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STRATEGY |
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IC181 |
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CONTROL IC |
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A–D |
RFDC |
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HF |
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Disc (CD, CD-R, CD-RW) |
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RUNNING OPC |
RFOPC |
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WRF |
CIRCUIT BLOCK |
AOUT |
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A–H |
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68–71 |
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RFDC |
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IC101 |
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IC401 |
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PICKUP ASSY |
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73–76 |
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FE |
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AK8563 |
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CXD2585Q |
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KRS-200A |
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TE |
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RF PROCESSOR |
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RFAC CD DECODER |
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FG |
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SPDL MOTOR |
LD CONTROL |
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CIRCUIT |
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TE |
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IC201 |
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SLD MOTOR |
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HF |
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PA9007A |
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RFWBL |
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IC351 |
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SERVO AMP IC |
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PDJ014A |
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ATIP DECODER |
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IC |
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IC451
LOADING M56788FP
MOTOR
TRK DRIVER
FCS DRIVER
SLD DRIVER
SPDL DRIVER
LOADING DRIVER
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RESET IC |
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IC303 |
IC701 |
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S-806E |
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PE5110B |
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PYY1196 |
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MODE CONTROL |
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EEPROM |
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MICROCOMPUTER |
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FL DISPLAY |
KEY MATRIX |
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PEL1097 |
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6
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
INPUT
Lch Rch
REC VR
34.5744MHz
17.2872MHz
IC802
PCM1800-1
AD CONVERTER
ADLRCK
ADBCK
ADDATA
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IC561 |
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IC503 |
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BA7082F |
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LH64256CK-70 |
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VCO IC |
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D-RAM |
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ADDRESS |
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DATA |
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CDLRCK, CDBCK |
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IC501 |
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CDDATA, CDTX |
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LC89585 |
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EFM ENCODER IC |
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RFOPC(60 pin) |
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AOUT(61 pin) |
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DIRBCK |
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IC301 |
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DIRLRCK |
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16.9344MHz |
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AD0-AD7 |
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DIRDATA |
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PE5109A |
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||||||||||
ADDRESS |
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MECH. CONTROL |
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IC502 |
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MICROCOMPUTER |
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AD1893JST |
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Fs CONVERTER |
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TEMPERATURE |
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SENSOR IC |
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TK11041M |
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MODE
DISPLAY LED
D704
D701
D702
L ch IC401
IC405 OUTPUT
DA CONVERTER
R ch
MY, MV TYPES
: PE8001A
KU/CA TYPE
DALRCK : PCM1718
DADATA
DABCK
HP
IC406 OUTPUT
16.9344MHz
Digital in
COAXIAL
Digital in
OPTICAL
Digital out
COAXIAL
Digital out
OPTICAL
7
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
2. PRODUCT DESCRIPTIONS
The PDR-555RW series (PDR-555RW, PDR-V500 and PDR19RW) is the first series of CD recorders from PIONEER that supports recording and erasing of CD-RW discs. Basic operations with CDs and CD-Rs with this series are based on those of the CD recorders of the PDR-05 series.
The main differences from the PDR-05 series concerning the circuits are:
•The pickup is changed.
•The circuit in RF amplifier is changed.
•The LD drive circuit (including the strategy control circuit) is changed.
•A running OPC circuit is added.
•The focus servo, tracking servo and sled servo are digitized.
•The driver IC is changed.
•The CD decoder IC is changed.
•The sampling rate converter IC is changed.
•The DA converter is changed.
Also, the circuits of the CD recorders of the PDR-509 series are based on those of the PDR-555RW series. So the main circuits used in the PDR-509 series are equivalent to those of the PDR555RW series. But as an exception, AD converter is changed to the AK5340-VS from the PCM1800-1.
8
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
3. PORT TABLE OF MICROCOMPUTER
• The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.
3.1 MODE CONTROL OF PDR-555RW, PDR-V500 AND PDR-19RW
PD4968A (FUNCTION ASSY : IC701)
• Mode Control IC
No. |
Mark |
Pin Name |
I/O |
Pin Function |
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1 |
FIP6 |
GRID 6 |
O |
FL grid output 5 |
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2 |
FIP5 |
GRID 5 |
O |
FL grid output 6 |
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3 |
FIP4 |
GRID 4 |
O |
FL grid output 7 |
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4 |
FIP3 |
GRID 3 |
O |
FL grid output 8 |
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5 |
FIP2 |
GRID 2 |
O |
FL grid output 9 |
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6 |
FIP1 |
GRID 1 |
O |
FL grid output 10 |
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7 |
FIP0 |
GRID 0 |
O |
FL grid output 11 |
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8 |
VDD |
− |
- |
Connect to VDD |
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9 |
SCOK |
RSCK |
O |
Serial clock for JIG communication |
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10 |
SO0 |
RSO |
O |
Serial output for JIG communication |
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11 |
SI0 |
RSI |
I |
Serial input for JIG communication |
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12 |
P24 |
XTAL |
O |
XTAL ON/OFF (At digital selection without FS converter : L) |
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13 |
P23 |
XEVCO |
O |
Encoder VCO ON/OFF (At CD : H) |
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14 |
SCK1 |
FSCK |
I/O |
Serial clock of the mechanism controller LSI |
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15 |
SO1 |
FSO |
O |
Serial output of the mechanism controller LSI |
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16 |
SI |
FSI |
I |
Serial input of the mechanism controller LSI |
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17 |
RESET |
XRESET |
O |
Reset input of the mode controller |
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18 |
P74 |
LDATA |
O |
Communication data output for LED driver |
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|
19 |
P73 |
LCLOCK |
O |
Communication data input for LED driver |
|
|
|
|
|
|
|
20 |
AVSS |
GND |
I |
Connect to VDD |
|
|
|
|
|
|
|
21 |
P17 |
XFUSE |
O |
During use the serial communication between the mode controller and LC89585 (During use : L) |
|
|
|
|
|
|
|
22 |
P16 |
LCK |
O |
Communication latch output for LED driver |
|
|
|
|
|
|
|
23 |
P15 |
XVCO |
O |
PLL ON/OFF (For SRC ON/OFF SRC OFF: L) |
|
|
|
|
|
|
|
24 |
P14 |
FS_THR |
O |
SRC through output |
|
|
|
|
|
|
|
25 |
P13 |
DACLAT |
O |
Communication latch output for D/A converter |
|
|
|
|
|
|
|
26 |
P12 |
XRST |
O |
Reset output for mechanism controller and ATIP decoder (H: release the reset) |
|
|
|
|
|
|
|
27 |
P11 |
XOPT |
O |
Optical input selection ( At optical input selection : L) |
|
|
|
|
|
|
|
28 |
P10 |
− |
O |
Not used (A/D input) |
|
|
|
|
|
|
|
29 |
AVDD |
VDD |
− |
Connect to VDD |
|
|
|
|
|
|
|
30 |
AVREF |
VDD |
− |
Connect to VDD |
|
|
|
|
|
|
|
31 |
P04 |
ROT_DI |
I |
For judgement of the rotary encoder SW direction |
|
|
|
|
|
|
|
32 |
XT2 |
− |
O |
Not used |
|
|
|
|
|
|
|
33 |
VSS |
GND |
− |
Connect to GND |
|
|
|
|
|
|
|
34 |
X1 |
− |
I |
System oscillation 4.19MHz |
|
|
|
|
|
||
35 |
X2 |
− |
O |
||
|
|||||
|
|
|
|
|
|
36 |
P37 |
SW1 |
I |
Demo mode ON/OFF L: Demo display exist |
|
|
|
|
|
|
|
37 |
P36 |
MODEL_0 |
I |
|
|
|
|
|
|
|
|
38 |
P35 |
MODEL_1 |
I |
Model switching pin |
|
|
|
|
|
|
|
39 |
P34 |
MODEL_2 |
I |
|
|
|
|
|
|
|
|
40 |
P33 |
RREQ |
O |
CE output for JIG communication |
|
|
|
|
|
|
9
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
No. |
Mark |
Pin Name |
I/O |
Pin Function |
|
|
|
|
|
41 |
P32 |
MACK |
O |
Communication response for mechanism controller |
|
|
|
|
|
42 |
P31 |
LREQ |
O |
CE signal for LC89585 |
|
|
|
|
|
43 |
P30 |
UNLOCK |
I |
Digital unlock detection |
|
|
|
|
|
44 |
INTP3 |
POT_INT |
I |
Rotary encoder SW operation detection ( ↓ interrupt) |
|
|
|
|
|
45 |
INTP2 |
XPFAIL |
I |
Power down detection |
|
|
|
|
|
46 |
INTP1 |
MREQ |
I |
Mechanism controller communication request (interrupt) |
|
|
|
|
|
47 |
INTP0 |
REMIN |
I |
Remote control input (interrupt) |
|
|
|
|
|
48 |
IC |
VPP |
I |
Connect to GND |
|
|
|
|
|
49 |
P72 |
ISEL3 |
I |
Input selector rotary SW input 3 (H: Analog selection) |
|
|
|
|
|
50 |
P71 |
ISEL2 |
I |
Input selector rotary SW input 2 (H: Optical selection) |
|
|
|
|
|
51 |
P70 |
ISEL1 |
I |
Input selector rotary SW input 1 (H: Coaxial selection) |
|
|
|
|
|
52 |
VDD |
VDD |
− |
Connect to VDD |
|
|
|
|
|
53 |
P127 |
SCAN4 |
O |
Key matrix output 4 |
|
|
|
|
|
54 |
P126 |
SCAN3 |
O |
Key matrix output 3 |
|
|
|
|
|
55 |
P125 |
SCAN2 |
O |
Key matrix output 2 |
|
|
|
|
|
56 |
P124 |
SCAN1 |
O |
Key matrix output 1 |
|
|
|
|
|
57 |
P123 |
SCAN0 |
O |
Key matrix output 0 |
|
|
|
|
|
58 |
P122 |
KEYIN3 |
I |
Key matrix input 3 |
|
|
|
|
|
59 |
P121 |
KEYIN2 |
I |
Key matrix input 2 |
|
|
|
|
|
60 |
P120 |
KEYIN1 |
I |
Key matrix input 1 |
|
|
|
|
|
61 |
P117 |
KEYIN0 |
I |
Key matrix input 0 |
|
|
|
|
|
62 |
P116 |
ATT_0V |
I |
|
|
|
|
|
|
63 |
P115 |
AATLAT |
O |
|
|
|
|
|
|
64 |
P114 |
FINL_SEG |
O |
"FINALIZE" segment output (At lights up: H) |
|
|
|
|
|
65 |
P113 |
SEG 10 |
O |
FL segment output 10 |
|
|
|
|
|
66 |
P112 |
SEG 9 |
O |
FL segment output 9 |
|
|
|
|
|
67 |
P111 |
SEG 8 |
O |
FL segment output 8 |
|
|
|
|
|
68 |
P110 |
SEG 7 |
O |
FL segment output 7 |
|
|
|
|
|
69 |
P107 |
SEG 6 |
O |
FL segment output 6 |
|
|
|
|
|
70 |
P106 |
SEG 5 |
O |
FL segment output 5 |
|
|
|
|
|
71 |
VLOAD |
VLOAD |
− |
VLOAD |
|
|
|
|
|
72 |
P105 |
SEG 4 |
O |
FL segment output 4 |
|
|
|
|
|
73 |
P104 |
SEG 3 |
O |
FL segment output 3 |
|
|
|
|
|
74 |
P103 |
SEG 2 |
O |
FL segment output 2 |
|
|
|
|
|
75 |
P102 |
SEG 1 |
O |
FL segment output 1 |
|
|
|
|
|
76 |
P101 |
SEG 0 |
O |
FL segment output 0 |
|
|
|
|
|
77 |
P100 |
GRID10 |
O |
FL grid output 10 |
|
|
|
|
|
78 |
FIP9 |
GRID 9 |
O |
FL grid output 9 |
|
|
|
|
|
79 |
FIP8 |
GRID 8 |
O |
FL grid output 8 |
|
|
|
|
|
80 |
FIP7 |
GRID 7 |
O |
FL grid output 7 |
|
|
|
|
|
10
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
3.2 MECHANISM CONTROL OF PDR-555RW, PDR-V500 AND PDR-19RW
PD4956B (SERVO DIGITAL ASSY : IC204)
• Mechanism Control IC
No. |
Mark |
Pin Name |
I/O |
|
Pin Function |
|
|
|
|
|
|
||
1 |
P32/XCLK0/SCL |
MSCK |
O(I) |
Serial transfer clock output of clock synchronous system |
||
|
|
|
|
|
||
2 |
P33/SO0/SDA |
MSO |
O(I) |
Serial transfer data output of clock synchronous system |
||
|
|
|
|
|
|
|
3 |
P34/TO0 |
− |
O |
Not used |
|
|
|
|
|
|
|
||
4 |
P35/TO1 |
STCN0 |
O |
Outputs for strategy adjustment (3T delay + 30 nsec) |
||
|
|
|
|
|
||
5 |
P36/TO2 |
FOK |
I |
FOCUS OK input (H: FOCUS OK) |
||
|
|
|
|
|
||
6 |
P37/TO3 |
LRST |
O |
RESET output for the servo and digital system ICs (L: Reset) |
||
|
|
|
|
|
||
7 |
XRESET |
XRESET |
I |
RESET input (L: Reset) |
||
|
|
|
|
|
||
8 |
VDD1 |
+V5 |
− |
Positive power supply excepting port section |
||
|
|
|
|
|
||
9 |
X2 |
CLOCK |
I |
Crystal input for system clock (32MHz) |
||
|
|
|
|
|
||
10 |
X1 |
CLOCK |
− |
Crystal output for system clock (32MHz) |
||
|
|
|
|
|
||
11 |
VSS1 |
GND |
− |
GND excepting port section |
||
|
|
|
|
|
||
12 |
P00 |
XECE |
O |
Enable output for reading the jig for test |
||
|
|
|
|
|
||
13 |
P01 |
RECE |
O |
Laser diode recording power ON/OFF ON: H |
||
|
|
|
|
|
|
|
14 |
P02 |
NC |
O |
Not used |
|
|
|
|
|
|
|
|
|
15 |
P03 |
NC |
O |
Not used |
|
|
|
|
|
|
|
||
16 |
P04 |
IT5SEL |
O |
Input switch of INTP5 pin (H: SENS, L: TOCP) |
||
|
|
|
|
|
||
17 |
P05 |
XENCE |
O |
External sync enable output of LC89585 |
||
|
|
|
|
|
||
18 |
P06 |
XASYNC |
O |
ATIP frame sync |
||
|
|
|
|
|
||
19 |
P07 |
XENCE |
O(I) |
Serial enable output of LC89585 |
||
|
|
|
|
|
|
|
20 |
P67/XREFRQ/ |
CLV |
O |
Spindle servo |
CLV/CAV mode |
|
HLDAK |
||||||
|
|
|
|
|
||
|
|
|
|
|
|
|
21 |
P66/XWAIT/ |
ECLV |
O |
Spindle servo |
EFM/Wobble mode |
|
HLDRQ |
||||||
|
|
|
|
|
||
|
|
|
|
|
||
22 |
P65/XWR |
XWR |
O |
Strobe signal output for READ operation of the external memory |
||
|
|
|
|
|
||
23 |
P64/XRD |
XRD |
O |
Strobe signal output for WRITE operation of the external memory |
||
|
|
|
|
|
||
24 |
P63/A19 |
XLT |
O |
Latch output of CXD2585Q command |
||
|
|
|
|
|
||
25 |
P62/A18 |
SSCK |
O |
Serial clock output for CXD2585Q command |
||
|
|
|
|
|
||
26 |
P61/A17 |
SSO |
O |
Serial data output for CXD2585Q command |
||
|
|
|
|
|
||
27 |
P60/A16 |
ALAT |
O |
Latch output for AK8563 command |
||
|
|
|
|
|
||
28 |
P57/A15 |
SCLK |
O |
Serial clock output for serial readout of CXD2585Q |
||
|
|
|
|
|
|
|
29 |
P56/A14 |
TP_2P |
O |
Test pin |
|
|
|
|
|
|
|||
30 |
P55/A13 |
TP_1P |
|
|||
|
|
|
||||
|
|
|
|
|
|
|
31 |
P54/A12 |
LDPW4 |
|
|
|
|
|
|
|
|
|
|
|
32 |
P53/A11 |
LDPW3 |
|
|
|
|
|
|
|
|
|
||
33 |
P52/A10 |
LDPW2 |
O |
Recording laser power output setting |
||
|
|
|
|
|
|
|
34 |
P51/A9 |
LDPW1 |
|
|
|
|
|
|
|
|
|
|
|
35 |
P50/A8 |
LDPW0 |
|
|
|
|
|
|
|
|
|
|
|
36 |
P47/AD7 |
AD7 |
|
|
|
|
|
|
|
|
|
|
|
37 |
P46/AD6 |
AD6 |
|
|
|
|
|
|
|
|
|
||
38 |
P45/AD5 |
AD5 |
O |
Data address line |
||
|
|
|
|
|
|
|
39 |
P44/AD4 |
AD4 |
|
|
|
|
|
|
|
|
|
|
|
40 |
P43/AD3 |
AD3 |
|
|
|
|
|
|
|
|
|
|
11
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
No. |
Mark |
Pin Name |
I/O |
Pin Function |
|
|
|
|
|
|
|
41 |
P42/AD2 |
AD2 |
|
|
|
|
|
|
|
|
|
42 |
P41/AD1 |
AD1 |
O |
Data address line |
|
|
|
|
|
|
|
43 |
P40/AD0 |
AD0 |
|
|
|
|
|
|
|
|
|
44 |
ASTB/CLKOUT |
ASTB |
O |
External latch signal of lower address signal for external memory access |
|
|
|
|
|
|
|
45 |
Vss0 |
GND |
− |
GND of port section |
|
|
|
|
|
|
|
46 |
TEST |
GND |
− |
Connect to Vss0 |
|
|
|
|
|
|
|
47 |
P10/PWM0 |
SPSP |
O |
Spindle drive PWM output in the Spindle CAV |
|
|
|
|
|
|
|
48 |
P11/PWM1 |
DGAI |
O |
In the PLAY or REC mode, it becomes "L" for outer periphery from 18 minutes of the CD and |
|
12cm CD-R, and "H" for outer periphery from 9 minutes of the 8cm CD-R. |
|||||
|
|
|
|
||
|
|
|
|
|
|
49 |
P12/ASCK2/XSCK2 |
SQCK |
O |
Serial clock output for sub-Q of CXD2585Q |
|
|
|
|
|
|
|
50 |
P13/RXD2/SI2 |
SQSI |
I |
Serial data input for sub-Q of CXD2585Q |
|
|
|
|
|
|
|
51 |
P14/TXD2/SO2 |
SO2 |
O |
Serial data output |
|
|
|
|
|
|
|
52 |
P15 |
MREQ |
O |
Serial hand shake output to the mode controller |
|
|
|
|
|
|
|
53 |
P16 |
D8CM |
O |
8cm CD-R disc 8cm: H |
|
|
|
|
|
|
|
54 |
P17 |
NC |
O |
Not used |
|
|
|
|
|
|
|
55 |
VDD0 |
+5V |
− |
Positive power supply of port section |
|
|
|
|
|
|
|
56 |
P70/ANI0 |
TEPP |
I(A) |
Tracking error peak to peak (for tracking gain adjustment) |
|
|
|
|
|
|
|
57 |
P71/ANI1 |
RFT |
I(A) |
A/D input of upper side envelope of Playback RF |
|
|
|
|
|
|
|
58 |
P72/ANI2 |
RFB |
I(A) |
A/D input of lower side envelope of Playback RF |
|
|
|
|
|
|
|
59 |
P73/ANI3 |
TEMP |
I(A) |
A/D input of temperature sensor |
|
|
|
|
|
|
|
60 |
P74/ANI4 |
RFOPC |
I(A) |
A/D input of RFOPC/MPXOUT |
|
|
|
|
|
|
|
61 |
P75/ANI5 |
VWDC2 |
I(A) |
A/D input for strategy adjustment |
|
|
|
|
|
|
|
62 |
P76/ANI6 |
TRAY |
I(A) |
A/D input of loading position |
|
|
|
|
|
|
|
63 |
P77/ANI7 |
AD7 |
I(A) |
Not used |
|
|
|
|
|
|
|
64 |
AVDD |
+5V |
− |
Positive power supply for A/D converter |
|
|
|
|
|
|
|
65 |
AVREF1 |
+5V |
− |
Reference voltage input for A/D converter |
|
|
|
|
|
|
|
66 |
AVSS |
GND |
− |
GND for A/D converter |
|
|
|
|
|
|
|
67 |
ANO0 |
WREF |
O(A) |
D/A output for recording APC reference |
|
|
|
|
|
|
|
68 |
ANO1 |
VWDC2R |
O(A) |
D/A output for strategy adjustment |
|
|
|
|
|
|
|
69 |
AVREF2 |
+5V |
− |
Reference voltage for D/A converter |
|
|
|
|
|
|
|
70 |
AVREF3 |
GND |
− |
Reference voltage for D/A converter |
|
|
|
|
|
|
|
71 |
P20/NMI |
XPFAIL |
I |
Power failure detection AT power failure: falling edge |
|
|
|
|
|
|
|
72 |
P21/INTP0 |
FG |
I |
Spindle FG input |
|
|
|
|
|
|
|
73 |
P22/INTP1 |
ATIP |
I |
ATIP SYNC input |
|
|
|
|
|
|
|
74 |
P23/INTP2/C1 |
SCOR |
I |
Frame sync of CXD2585Q |
|
|
|
|
|
|
|
75 |
P24/INTP3 |
SUBSYNC |
I |
Frame sync of LC89585 |
|
|
|
|
|
|
|
76 |
P25/INTP4/ASCK/ |
XRFDT |
I |
EFM playback RF detection |
|
XSCK1 |
|||||
|
|
|
|
||
|
|
|
|
|
|
77 |
P26/INTP5 |
IT5IN |
I |
TOC position sensor (TOC position: L), SENS signal input of CXD2585Q |
|
|
|
|
|
|
|
78 |
P27/SI0 |
MSI |
I |
Serial transfer data input of the clock sync. system |
|
|
|
|
|
|
|
79 |
P30/RXD/SI1 |
MACK |
I |
Serial hand shake input to the mode controller |
|
|
|
|
|
|
|
80 |
P31/TXD/SO1 |
XFUSE |
I |
Signal which is during communication between LC89585 and the mode controller |
|
|
|
|
|
|
|
|
|
|
|
Note: (A) in item I/O shows "ANALOG". |
12
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
PDJ014A (SERVO DIGITAL ASSY: IC205)
External port (External RAM domain (2C000H to 2C0FFH) )
No. |
Mark |
Pin Name |
I/O |
Pin Function |
|
|
|
|
|
|
|
45 |
POA0 |
GAINUP1 |
O |
Gain switch for CD-RW (CD-RW: H) |
|
|
|
|
|
|
|
46 |
POA1 |
GAINUP2 |
O |
APC circuit control signal for CD-R running OPC |
|
|
|
|
|
|
|
47 |
POA2 |
GAINUP3 |
O |
|
|
|
|
|
|
|
|
48 |
GND |
− |
− |
GND |
|
|
|
|
|
|
|
49 |
POA3 |
ROPC |
O |
ANI4 input switch (H: RFOPC, L: MPXOUT) |
|
|
|
|
|
|
|
50 |
POA4 |
PHYERS |
O |
Physical Erase |
|
|
|
|
|
|
|
51 |
POA5 |
SSEL |
O |
Tracking envelope detecting reset signal |
|
|
|
|
|
|
|
52 |
POA6 |
AGCON |
O |
AGC circuit ON/OFF for Wobble extraction |
|
|
|
|
|
|
|
53 |
POA7 |
LJUNP |
O |
N track jump |
|
|
|
|
|
|
|
54 |
POB0 |
LOUT |
O |
Loading open |
|
|
|
|
|
|
|
55 |
POB1 |
LIN |
O |
Loading close |
|
|
|
|
|
|
|
56 |
POB2 |
KOJK |
O |
Optical axis switching circuit ON/OFF |
|
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57 |
POB3 |
EECS |
O |
Enable output for writing and reading the EEPROM data |
|
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|
|
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58 |
Vcc |
− |
− |
+5V |
|
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59 |
POB4 |
STCN4 |
O |
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60 |
POB5 |
STCN3 |
O |
Strategy control output |
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61 |
POB6 |
STCN2 |
O |
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|||||
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62 |
POB7 |
STCN1 |
O |
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63 |
POC0 |
TEG2 |
O |
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64 |
POC1 |
TEG1 |
O |
Tracking error amplifier gain adjustment |
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65 |
POC2 |
TEG0 |
O |
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66 |
POC3 |
RW/XR |
O |
Switch the CD-RW/Other |
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67 |
POC4 |
− |
− |
Not used |
|
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68 |
GND |
− |
− |
GND |
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69 |
POC5 |
XCD |
O |
Switch the CD/Other |
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70 |
POC6 |
ENBL |
O |
LD ON/OFF output |
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71 |
POC7 |
XAMUTE |
O |
Audio last stage mute |
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13
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
3.3 MODE CONTROL OF PDR-509
PE5110B (FUNCTION ASSY : IC701)
• Mode Control IC
No. |
Mark |
Pin Name |
I/O |
|
|
Pin Function |
|
|
|
|
|
|
|
1 |
FIP6 |
GRID 6 |
O |
FL grid output 5 |
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2 |
FIP5 |
GRID 5 |
O |
FL grid output 6 |
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3 |
FIP4 |
GRID 4 |
O |
FL grid output 7 |
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4 |
FIP3 |
GRID 3 |
O |
FL grid output 8 |
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5 |
FIP2 |
GRID 2 |
O |
FL grid output 9 |
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6 |
FIP1 |
GRID 1 |
O |
FL grid output 10 |
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7 |
FIP0 |
GRID 0 |
O |
FL grid output 11 |
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8 |
VDD |
− |
− |
Connect to VDD |
|
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9 |
SCOK |
− |
O |
Not used |
"L" outputs |
|
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10 |
SO0 |
− |
O |
Not used |
"L" outputs |
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11 |
SI0 |
− |
O |
Not used |
"L" outputs |
|
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||
12 |
P24 |
XTAL |
O |
XTAL ON/OFF (At digital selection without FS converter : L) |
||
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||
13 |
P23 |
XEVCO |
O |
Encoder VCO ON/OFF (At CD : H) |
||
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||
14 |
SCK1 |
FSCK |
I/O |
Serial clock of the mechanism controller LSI |
||
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15 |
SO1 |
FSO |
O |
Serial output of the mechanism controller LSI |
||
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||
16 |
SI |
FSI |
I |
Serial input of the mechanism controller LSI |
||
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17 |
RESET |
XRESET |
I |
Reset input of the mode controller |
(L : Reset) |
|
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|
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18 |
P74 |
DISP_L |
O |
"DISP OFF" LED lights up output |
(L: lights up) |
|
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|
|
|
|
||
19 |
P73 |
LCLOCK |
O |
"AUTO/MANUAL" LED lights up output (L: lights up) |
||
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|
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20 |
AVSS |
GND |
I |
Connect to GND |
|
|
|
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|
||
21 |
P17 |
XFUSE |
O |
During use the serial communication between the mode controller and LC89585 (During use : L) |
||
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|
|
||
22 |
P16 |
CENT_L |
O |
"CENTER" LED lights up output (L : lights up) |
||
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||
23 |
P15 |
XVCO |
O |
PLL ON/OFF (At digital selection without FS converter : L (PLL oscillation)) |
||
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||
24 |
P14 |
FS_THR |
O |
FS through output (Digital input at FS through ON and 44.1kHz : L) |
||
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|
||
25 |
P13 |
DACLAT |
O |
Communication latch output for D/A converter |
||
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||
26 |
P12 |
XRST |
O |
Reset output for mechanism controller and ATIP decoder (L: reset) |
||
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||
27 |
P11 |
XOPT |
O |
Optical input selection ( At optical input selection : L) |
||
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|
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|
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28 |
P10 |
− |
O |
Not used |
"L" outputs (prepare the parallel remote control key inpu) |
|
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|
|
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29 |
AVDD |
VDD |
− |
Connect to VDD |
|
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30 |
AVREF |
VDD |
− |
Connect to VDD |
|
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31 |
P04 |
− |
− |
|
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32 |
XT2 |
− |
O |
Not used |
|
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33 |
VSS |
GND |
− |
Connect to VDD |
|
|
|
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|
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34 |
X1 |
− |
I |
System oscillation 4.19MHz |
|
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|
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35 |
X2 |
− |
O |
|
||
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||||
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36 |
P37 |
SW1 |
I |
Demo mode ON/OFF (H fixed: No demo mode) |
||
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|
||
37 |
P36 |
FS_SW |
I |
FS through ON/OFF switching input (H: FS through) |
||
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|
||
38 |
P35 |
HIB_SW |
I |
Hi-bit mode ON/OFF switching input (H: Hi-bit) |
||
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|
||
39 |
P34 |
LGT_SW |
I |
LEGATO ON/OFF switching input (H: LEGATO ON) |
||
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40 |
P33 |
RREQ |
O |
CE output for jig communication |
|
|
|
|
|
|
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|
|
14
PDR-555RW, PDR-V500, PDR-19RW, PDR-509
No. |
Mark |
Pin Name |
I/O |
Pin Function |
|
|
|
|
|
|
|
41 |
P32 |
MACK |
O |
Communication response for mechanism controller (H to L: communication permission) |
|
(L to H: Communication end) |
|||||
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||
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|
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42 |
P31 |
LREQ |
O |
CE signal for LC89585 (L: Enable) |
|
|
|
|
|
|
|
43 |
P30 |
UNLOCK |
I |
Digital unlock detection |
|
|
|
|
|
|
|
44 |
INTP3 |
POT_INT |
I |
Rotary encoder SW operation detection ( ↓ interrupt) |
|
|
|
|
|
|
|
45 |
INTP2 |
XPFAIL |
I |
Power down detection (L: power down) |
|
|
|
|
|
|
|
46 |
INTP1 |
MREQ |
I |
Mechanism controller communication request (interrupt) |
|
|
|
|
|
|
|
47 |
INTP0 |
REMIN |
I |
Remote control input (interrupt) |
|
|
|
|
|
|
|
48 |
IC |
VPP |
I |
Connect to GND |
|
|
|
|
|
|
|
49 |
P72 |
ROT3 |
I |
Not used "L" outputs |
|
|
|
|
|
|
|
50 |
P71 |
ROT2 |
I |
"H" outputs when playing the CD/CD-R/CD-RW discs in the Hi-bit mode |
|
|
|
|
|
|
|
51 |
P70 |
ROT1 |
I |
Rotary encoder SW direction judgment input |
|
|
|
|
|
|
|
52 |
VDD |
VDD |
− |
Connect to VDD |
|
|
|
|
|
|
|
53 |
P127 |
SCAN4 |
O |
Key matrix output 4 |
|
|
|
|
|
|
|
54 |
P126 |
SCAN3 |
O |
Key matrix output 3 |
|
|
|
|
|
|
|
55 |
P125 |
SCAN2 |
O |
Key matrix output 2 |
|
|
|
|
|
|
|
56 |
P124 |
SCAN1 |
O |
Key matrix output 1 |
|
|
|
|
|
|
|
57 |
P123 |
SCAN0 |
O |
Key matrix output 0 |
|
|
|
|
|
|
|
58 |
P122 |
KEYIN3 |
I |
Key matrix input 3 |
|
|
|
|
|
|
|
59 |
P121 |
KEYIN2 |
I |
Key matrix input 2 |
|
|
|
|
|
|
|
60 |
P120 |
KEYIN1 |
I |
Key matrix input 1 |
|
|
|
|
|
|
|
61 |
P117 |
KEYIN0 |
I |
Key matrix input 0 |
|
|
|
|
|
|
|
62 |
P116 |
− |
O |
Not used "L" outputs |
|
|
|
|
|
|
|
63 |
P115 |
SCMS |
O |
Prepare the mode switch ("L" outputs) |
|
|
|
|
|
|
|
64 |
P114 |
FINL_SEG |
O |
FINALIZE-segment output (At lights up: H) |
|
|
|
|
|
|
|
65 |
P113 |
SEG 10 |
O |
FL segment output 10 |
|
|
|
|
|
|
|
66 |
P112 |
SEG 9 |
O |
FL segment output 9 |
|
|
|
|
|
|
|
67 |
P111 |
SEG 8 |
O |
FL segment output 8 |
|
|
|
|
|
|
|
68 |
P110 |
SEG 7 |
O |
FL segment output 7 |
|
|
|
|
|
|
|
69 |
P107 |
SEG 6 |
O |
FL segment output 6 |
|
|
|
|
|
|
|
70 |
P106 |
SEG 5 |
O |
FL segment output 5 |
|
|
|
|
|
|
|
71 |
VLOAD |
− |
− |
VLOAD |
|
|
|
|
|
|
|
72 |
P105 |
SEG 4 |
O |
FL segment output 4 |
|
|
|
|
|
|
|
73 |
P104 |
SEG 3 |
O |
FL segment output 3 |
|
|
|
|
|
|
|
74 |
P103 |
SEG 2 |
O |
FL segment output 2 |
|
|
|
|
|
|
|
75 |
P102 |
SEG 1 |
O |
FL segment output 1 |
|
|
|
|
|
|
|
76 |
P101 |
SEG 0 |
O |
FL segment output 0 |
|
|
|
|
|
|
|
77 |
P100 |
GRID10 |
O |
FL grid output 10 |
|
|
|
|
|
|
|
78 |
FIP9 |
GRID 9 |
O |
FL grid output 9 |
|
|
|
|
|
|
|
79 |
FIP8 |
GRID 8 |
O |
FL grid output 8 |
|
|
|
|
|
|
|
80 |
FIP7 |
GRID 7 |
O |
FL grid output 7 |
|
|
|
|
|
|
15