Philips ADC0803LCN, ADC0803LCD, ADC0803CN, ADC0804LCD, ADC0804CD Datasheet

Philips Semiconductors Linear Products	Product specification
CMOS 8-bit A/D converters	ADC0803/4-1

DESCRIPTION

The ADC0803 family is a series of three CMOS 8-bit successive approximation A/D converters using a resistive ladder and capacitive array together with an auto-zero comparator. These converters are designed to operate with microprocessor-controlled buses using a minimum of external circuitry. The 3-State output data lines can be connected directly to the data bus.

The differential analog voltage input allows for increased common-mode rejection and provides a means to adjust the zero-scale offset. Additionally, the voltage reference input provides a means of encoding small analog voltages to the full 8 bits of resolution.

FEATURES

•Compatible with most microprocessors

•Differential inputs

•3-State outputs

•Logic levels TTL and MOS compatible

•Can be used with internal or external clock

•Analog input range 0V to VCC

•Single 5V supply

•Guaranteed specification with 1MHz clock

PIN CONFIGURATION

									D1, N PACKAGES
			CS					1				20	VCC
			RD					2				19	CLK R
		WR						3				18	D0
CLK IN								4				17	D1
	INTR							5				16	D2
													D3
VIN(+)								6				15
VIN(±)								7				14	D4
													D5
A GND								8				13
VREF/2								9				12	D6
													D7
D GND								10				11

TOP VIEW

NOTE:

SOL Ð Released in large SO package only.

APPLICATIONS

•Transducer-to-microprocessor interface

•Digital thermometer

•Digitally-controlled thermostat

•Microprocessor-based monitoring and control systems

ORDERING INFORMATION

DESCRIPTION	TEMPERATURE RANGE	ORDER CODE	DWG #
20-Pin Plastic Dual In-Line Package (DIP)	-40 to +85°C	ADC0803/04-1 LCN	0408B
20-Pin Plastic Dual In-Line Package (DIP)	0 to 70°C	ADC0803/04-1 CN	0408B
20-Pin Plastic Small Outline (SO) Package	0 to 70°C	ADC0803/04-1 CD	1021B
20-Pin Plastic Small Outline (SO) Package	-40 to 85°C	ADC0803/04-1 LCD	1021B

ABSOLUTE MAXIMUM RATINGS

SYMBOL		PARAMETER	RATING	UNIT
VCC	Supply voltage		6.5	V
	Logic control input voltages		-0.3 to +16	V
	All other input voltages		-0.3 to	V
			(VCC +0.3)
TA	Operating temperature range
	ADC0803/04-1 LCD		-40 to +85	°C
	ADC0803/04-1 LCN		-40 to +85	°C
	ADC0803/04-1 CD		0 to +70	°C
	ADC0803/04-1 CN		0 to +70	°C
TSTG	Storage temperature		-65 to +150	°C
TSOLD	Lead soldering temperature (10 seconds)		300	°C
PD	Maximum power dissipation
	T	1
		=25°C (still air)
	A
	N package		1690	mW
	D package		1390	mW

NOTES:

1. Derate above 25°C, at the following rates: N package at 13.5mW/°C; D package at 11.1mW/°C

August 31, 1994

555

853-0034 13721

Philips Semiconductors Linear Products	Product specification
CMOS 8-bit A/D converters	ADC0803/4-1

BLOCK DIAGRAM

			VIN (+)	VIN (±)
			6	7
			+	±
				M
VREF/2	9				+
		LADDER AND			AUTO ZERO
	8	DECODER			COMPARATOR
A GND
					±
VCC	20						D7	(MSB)	(11)
							D6		(12)
							D5		(13)
						OUTPUT	D4		(14)
						LATCHES	D3		(15)
		SAR					D2		(16)
							D1		(17)
	10						D0	(LSB)	(18)
D GND					LE	OE
WR	3
		8±BIT		CLOCK
		SHIFT REGISTER
	1
CS
		S
		INTR
		FF
	2	R	Q
RD
			5	4	19
			INTR	CLK IN	CLK R

August 31, 1994

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Philips Semiconductors Linear Products	Product specification
CMOS 8-bit A/D converters	ADC0803/4-1

DC ELECTRICAL CHARACTERISTICS

VCC = 5.0V, fCLK = 1MHz, TMIN ≤ TA ≤ TMAX, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

ADC0803/4

UNIT

Min

Typ

Max

ADC0803 relative accuracy error (adjusted)

Full-Scale adjusted

0.50

LSB

ADC0804 relative accuracy error (unadjusted)

VREF/2 = 2.500VDC

1

LSB

R

IN

V

REF

/2 input resistance3

V = 0V2

400

680

Ω

CC

Analog input voltage range3

±0.05

V

CC

+0.05

V

DC common-mode error

Over analog input voltage

1/16

1/8

LSB

range

Power supply sensitivity

VCC = 5V ±10%1

1/16

LSB

Control inputs

VIH

Logical ª1º input voltage

VCC = 5.25VDC

2.0

15

VDC

VIL

Logical ª0º input voltage

VCC = 4.75VDC

0.8

VDC

IIH

Logical ª1º input current

VIN = 5VDC

0.005

1

μADC

IIL

Logical ª0º input current

VIN = 0VDC

±1

±0.005

μADC

Clock in and clock R

VT+

Clock in positive-going threshold voltage

2.7

3.1

3.5

VDC

VT±

Clock in negative-going threshold voltage

1.5

1.8

2.1

VDC

VH

Clock in hysteresis (VT+)±(VT±)

0.6

1.3

2.0

VDC

VOL

Logical ª0º clock R output voltage

IOL = 360μA, VCC = 4.75VDC

0.4

VDC

VOH

Logical ª1º clock R output voltage

IOH = ±360μA, VCC = 4.75VDC

2.4

VDC

Data output and

INTR

VOL

Logical ª0º output voltage

Data outputs

IOL = 1.6mA, VCC = 4.75VDC

0.4

VDC

outputs

IOL = 1.0mA, VCC = 4.75VDC

0.4

VDC

INTR

VOH

Logical ª1º output voltage

IOH = ±360μA, VCC = 4.75VDC

2.4

VDC

IOH = ±10μA, VCC = 4.75VDC

4.5

IOZL

3-state output leakage

VOUT = 0VDC,

= logical ª1º

±3

μADC

CS

IOZH

3-state output leakage

VOUT = 5VDC,

= logical ª1º

3

μADC

CS

ISC

+Output short-circuit current

VOUT = 0V, TA = 25°C

4.5

12

mADC

ISC

±Output short-circuit current

VOUT = VCC, TA = 25°C

9.0

30

mADC

ICC

Power supply current

fCLK = 1MHz, VREF/2 = OPEN,

3.0

3.5

mA

CS

= Logical ª1º, T = 25°C

A

NOTES:

1.Analog inputs must remain within the range: ±0.05 ≤ VIN ≤ VCC + 0.05V.

2.See typical performance characteristics for input resistance at VCC = 5V.

3.VREF/2 and VIN must be applied after the VCC has been turned on to prevent the possibility of latching.

August 31, 1994

557

Philips Semiconductors Linear Products	Product specification
CMOS 8-bit A/D converters	ADC0803/4-1

AC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

TO

FROM

TEST CONDITIONS

ADC0803/4

UNIT

Min

Typ

Max

Conversion time

f =1MHz1

66

73

μs

CLK

f

Clock frequency1

0.1

1.0

3.0

MHz

CLK

Clock duty cycle1

40

60

%

CR

Free-running conversion rate

CS=0, fCLK=1MHz

13690

conv/s

INTR tied to WR

tW(

Start pulse width

30

ns

WR)L

CS=0

tACC

Access time

Output

75

100

ns

RD

CS=0, CL=100pF

CL=10pF, RL=10kΩ

t1H, t0H

3-State control

Output

RD

70

100

ns

See 3-State test circuit

WD

tW1, tR1

INTR delay

INTR

100

150

ns

or

RD

CIN

Logic input=capacitance

5

7.5

pF

COUT

3-State output capacitance

5

7.5

pF

NOTES:

1. Accuracy is guaranteed at fCLK=1MHz. Accuracy may degrade at higher clock frequencies.

FUNCTIONAL DESCRIPTION

These devices operate on the Successive Approximation principle. Analog switches are closed sequentially by successive approximation logic until the input to the auto-zero comparator

[ VIN(+)-VIN(-) ] matches the voltage from the decoder. After all bits are tested and determined, the 8-bit binary code corresponding to the input voltage is transferred to an output latch. Conversion begins with the arrival of a pulse at the WR input if the CS input is low. On the High-to-Low transition of the signal at the WR or the CS input, the SAR is initialized, the shift register is reset, and the INTR output is set high. The A/D will remain in the reset state as long as the CS and WR inputs remain low. Conversion will start from one to eight clock periods after one or both of these inputs makes a Low-to-High transition. After the conversion is complete, the INTR pin will make a High-to-Low transition. This can be used to interrupt a processor, or otherwise signal the availability of a new conversion result. A read (RD) operation (with CS low) will clear the INTR line and enable the output latches. The device may be run in the free-running mode as described later. A conversion in progress can be interrupted by issuing another start command.

Digital Control Inputs

The digital control inputs (CS, WR, RD) are compatible with standard TTL logic voltage levels. The required signals at these inputs correspond to Chip Select, START Conversion, and Output Enable control signals, respectively. They are active-Low for easy interface to microprocessor and microcontroller control buses. For applications not using microprocessors, the CS input (Pin 1) can be grounded and the A/D START function is achieved by a negative-going pulse to the WR input (Pin 3). The Output Enable function is achieved by a logic low signal at the RD input (Pin 2), which may be grounded to constantly have the latest conversion present at the output.

ANALOG OPERATION

Analog Input Current

The analog comparisons are performed by a capacitive charge summing circuit. The input capacitor is switched between VIN(+)4 and VIN(-), while reference capacitors are switched between taps on the reference voltage divider string. The net charge corresponds to the weighted difference between the input and the most recent total value set by the successive approximation register.

The internal switching action causes displacement currents to flow at the analog inputs. The voltage on the on-chip capacitance is switched through the analog differential input voltage, resulting in

proportional currents entering the VIN(+) input and leaving the VIN(-) input. These transient currents occur at the leading edge of the

internal clock pulses. They decay rapidly so do not inherently cause errors as the on-chip comparator is strobed at the end of the clock period.

Input Bypass Capacitors and Source Resistance

Bypass capacitors at the input will average the charges mentioned above, causing a DC and an AC current to flow through the output resistance of the analog signal sources. This charge pumping action

is worse for continuous conversions with the VIN(+) input at full scale. This current can be a few microamps, so bypass capacitors

should NOT be used at the analog inputs of the VREF/2 input for high resistance sources (> 1kΩ). If input bypass capacitors are

desired for noise filtering and a high source resistance is desired to minimize capacitor size, detrimental effects of the voltage drop across the input resistance can be eliminated by adjusting the full scale with both the input resistance and the input bypass capacitor in place. This is possible because the magnitude of the input current is a precise linear function of the differential voltage.

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