Philips 10H20EV8-4F, 10020EV8-4F, 10020EV8-4A Datasheet

Philips Semiconductors Programmable Logic Devices	Product specification
ECL programmable array logic	10H20EV8/10020EV8

DESCRIPTION

The 10H20EV8/10020EV8 is an ultra high-speed universal ECL PAL device. Combining versatile output macrocells with a standard AND/OR single programmable array, this device is ideal in implementing a user's custom logic. The use of Philips

Semiconductors state-of-the-art bipolar oxide isolation process enables the 10H20EV8/10020EV8 to achieve optimum speed in any design. The SNAP design software package from Philips Semiconductors simplifies design entry based upon Boolean or state equations.

The 10H20EV8/10020EV8 is a two-level logic element comprised of 11 fixed inputs, an input pin that can either be used as a clock or

12th input, 90 AND gates, and 8 Output Logic Macrocells. Each Output Macrocell can be individually configured as a dedicated input, dedicated output with polarity control, a bidirectional I/O, or as a registered output that has both output polarity control and feedback to the AND array. This gives the part the capability of having up to 20 inputs and eight outputs.

The 10H20EV8/10020EV8 has a variable number of product terms that can be OR'd per output. Four of the outputs have 12 AND terms available and the other four have 8 terms per output. This allows the designer the extra flexibility to implement those functions that he couldn't in a standard PAL device.

Asynchronous Preset and Reset product terms are also included for system design ease. Each output has a separate output enable product term. Another feature added for the system designer is a power-up Reset on all registered outputs.

The 10H20EV8/10020EV8 also features the ability to Preload the registers to any desired state during testing. The Preload is not affected by the pattern within the device, so can be performed at any step in the testing sequence. This permits full logical verification even after the device has been patterned.

FEATURES

•Ultra high speed ECL device

±tPD = 4.5ns (max)

±tIS = 2.6ns (max)

±tCKO = 2.3ns (max)

±fMAX = 208MHz

•Universal ECL Programmable Array Logic

±8 user programmable output macrocells

±Up to 20 inputs and 8 outputs

±Individual user programmable output polarity

•Variable product term distribution allows increased design capability

•Asynchronous Preset and Reset capability

•10KH and 100K options

•Power-up Reset and Preload function to enhance state machine design and testing

•Design support provided via SNAP and other CAD tools

•Security fuse for preventing design duplication

•Available in 24-Pin 300mil-wide DIP and 28-Pin PLCC.

PIN CONFIGURATIONS

F Package

	I1	1				24	VCC
	I2	2				23	I11
CLK/I12		3				22	I10
	F1	4				21	F8
	F2	5				20	F7
VCO1		6				19	VCO2
	F3	7				18	F6
	F4	8				17	F5
	I3	9				16	I9
	I4	10				15	I8
	I5	11				14	I7
V		12				13	I
	EE						6

F = Ceramic DIP (300mil-wide)

A Package

	CLK/I12			I2	I1	NC VCC I11 I10
			4	3	2	1	28	27	26
F1	5									25	F8
F2	6									24	F7
VCO1	7									23	VCO2
NC	8									22	NC
F3	9									21	F6
F4	10									20	F5
I3	11									19	I9
		12		13	14	15	16	17	18
			I4	I5 VEE NC I6				I7	I8

A = Plastic Leaded Chip Carrier

ORDERING INFORMATION

	DESCRIPTION	ORDER CODE	DRAWING NUMBER
	24-Pin Ceramic Dual In-Line (300mil-wide)	10H20EV8±4F	0586B
		10020EV8±4F
	28-Pin Plastic Leaded Chip Carrier	10H20EV8±4A	0401F
		10020EV8±4A

PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.

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853±1423 11164

Philips Semiconductors Programmable Logic Devices	Product specification
ECL programmable array logic	10H20EV8/10020EV8

LOGIC DIAGRAM

INPUT LINES

3
0	4	8	12	16	20	24	28	32	36
D
0
									OUTPUT	4
7									LOGIC
									MACRO
									CELL
D
0
									OUTPUT	21
7									LOGIC
									MACRO
									CELL
1
D
0
									OUTPUT	5
									LOGIC
11									MACRO
									CELL
2
D
0
									OUTPUT	20
									LOGIC
11									MACRO
									CELL
9
D
0
									OUTPUT	7
									LOGIC
11									MACRO
									CELL
10
D
0
									OUTPUT	18
									LOGIC
11									MACRO
									CELL
11
D
0
									OUTPUT	8
7									LOGIC
									MACRO
									CELL
13
D
0
									OUTPUT	17
7									LOGIC
									MACRO
14
									CELL
15										23
16										22
									ASYNCHRONOUS RESET
									ASYNCHRONOUS PRESET

NOTES:

1.All unprogrammed or virgin ªANDº gate locations are pulled to logic ª0º

2.Programmable connections

3.Pinout for F Package

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Philips Semiconductors Programmable Logic Devices	Product specification
ECL programmable array logic	10H20EV8/10020EV8

FUNCTIONAL DIAGRAM

		CLK/I					I
		1					11
				PROGRAMMABLE AND ARRAY
					(90 × 40)
	12	12	8	8	8	8	12	12
RESET	OUTPUT	OUTPUT	OUTPUT	OUTPUT	OUTPUT	OUTPUT	OUTPUT	OUTPUT
	LOGIC	LOGIC	LOGIC	LOGIC	LOGIC	LOGIC	LOGIC	LOGIC	PRESET
	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
	F	F	F	F	F	F	F	F

FUNCTIONAL DESCRIPTION

The 10H20EV8/10020EV8 is an ultra high-speed universal ECL PAL-type device.

Combining versatile Output Macrocells with a standard AND/OR single programmable array, this device is ideal in implementing a user's custom logic.

As can be seen in the Logic Diagram, the device is a two-level logic element with a programmable AND array. The 20EV8 can have up to 20 inputs and 8 outputs. Each output has a versatile Macrocell whereby the output can either be configured as a dedicated input, a dedicated combinatorial output with polarity control, a bidirectional I/O, or as a registered output that has both output polarity control and feedback into the AND array.

				Fn
	AP
		OUTPUT
D	Q	SELECT
			MUX
CLK	Q	S1	S0	VCC
	AR
FEEDBACK
	MUX
VCC	S1
Figure 1. Output Logic Macrocell
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The device also features 90 product terms.

Two of the product terms can be used for a global asynchronous preset and/or reset.

Eight of the product terms can be used for individual output enable control of each

Macrocell. The other 80 product terms are distributed among the outputs. Four of the outputs have eight product terms, while the other four have 12. This arrangement allows the utmost in flexibility when implementing user patterns.

Output Logic Macrocell

The 10H20EV8/10020EV8 incorporates an extremely versatile Output Logic Macrocell that allows the user complete flexibility when configuring outputs.

As seen in Figure 1, the 10H20EV8/ 10020EV8 Output Logic Macrocell consists of an edge-triggered D-type flip-flop, an output select MUX, and a feedback select MUX. Fuses S0 and S1 allow the user to select between the various cells. S1 controls whether the output will be either registered with internal feedback or combinatorial I/O. S0 controls the polarity of the output (ActiveHIGH or Active-LOW). This allows the user to achieve the following configurations: Registered Active-HIGH output, Registered

Active-LOW output, Combinatorial ActiveHIGH output, and Combinatorial Active-LOW output. With the output enable product term, this list can be extended by adding the configurations of a Combinatorial I/O with Polarity or another input.

Philips Semiconductors Programmable Logic Devices	Product specification
ECL programmable array logic	10H20EV8/10020EV8

ABSOLUTE MAXIMUM RATINGS1

SYMBOL	PARAMETER			RATING	UNIT
VEE	Supply voltage			±8.0	V
VIN	Input voltage (VIN should never be more negative than VEE)			0 to VEE	V
IO	Output source current			±50	mA
TS	Operating Temperature range			±55 to +150	°C
TJ	Storage Temperature range		Ceramic Package	+165	°C
			Plastic Package	+150	°C

NOTE:

1.Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

DC OPERATING CONDITIONS 10H20EV8

		TEST		LIMITS
SYMBOL	PARAMETER	CONDITIONS	MIN	NOM	MAX	UNIT
VCC, VCO1, VCO2	Circuit ground		0	0	0	V
VEE	Supply voltage (negative)			±5.2		V
		Tamb = 0°C	±1170		±840	mV
VIH	High level input voltage	Tamb = +25°C	±1130		±810	mV
		Tamb = +75°C	±1070		±735	mV
		Tamb = 0°C	±1950		±1480	mV
VIL	Low level input voltage	Tamb = +25°C	±1950		±1480	mV
		Tamb = +75°C	±1980		±1450	mV
Tamb	Operating ambient temperature range		0	+25	+75	°C

NOTE:

When operating at other than the specified VEE voltage (±5.2V), the DC and AC Electrical Characteristics will vary slightly from specified values.

DC OPERATING CONDITIONS 10020EV8

		TEST		LIMITS
SYMBOL	PARAMETER	CONDITIONS	MIN	NOM	MAX	UNIT
VCC, VCO1, VCO2	Circuit ground		0	0	0	V
VEE	Supply voltage		±4.8	±4.5	±4.2	V
VEE	Supply voltage when opetating with the 10K		±5.7			V
	or 10KH ECL family
		VEE = ±4.2V	±1150
VIH	High level input voltage	VEE = ±4.5V	±1165		±880	mV
		VEE = ±4.8V	±1165
		VEE = ±4.2V			±1475	mV
VIL	Low level input voltage	VEE = ±4.5V	±1810		±1475	mV
		VEE = ±4.8V			±1490	mV
Tamb	Operating ambient temperature range		0	+25	+85	°C

NOTE:

When operating at other than the specified VEE voltages (±4.2V, ±4.5V, ±4.8V), the DC and AC Electrical Characteristics will vary slightly from their specified values.

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Philips Semiconductors Programmable Logic Devices	Product specification
ECL programmable array logic	10H20EV8/10020EV8

D		D
	AP		AP
D	Q	D	Q
CK	Q	CK	Q
	AR		AR
Registered Active-HIGH		Registered Active-LOW
D		D
Combinatorial Active-HIGH		Combinatorial Active-LOW
	Figure 2.	Output Macro Cell Configurations

OUTPUT MACRO CELL CONFIGURATION

Shown in Figure 2 are the four possible configurations of the output macrocell using fuses S0 and S1. As seen, the output can either be registered Active-HIGH/LOW with feedback or combinatorial Active-HIGH/LOW with feedback. If the registered mode is chosen, the feedback from the Q output to the AND array enables one to make state machines or shift registers without having to tie the output to one of the inputs. If a combinatorial output is chosen, the feedback gate is enabled from the pin and allows one to create permanent outputs, permanent inputs, or I/O pins through the use of the output enable (D) product term.

OUTPUT ENABLE

Each output on the 10H20EV8/10020EV8 has its own individual product term for output enable. The use of the D product term

(direction control) allows the user three possible configurations of the outputs. They are: always enabled, always disabled, and

controlled by a programmed pattern. A HIGH on the D term enables the output, while a LOW performs the disable function. Output enable control can be achieved by programming a pattern on the D term.

The output enable control can also be used to expand a designer's possibilities once a combinatorial output has been chosen. If the

D term is always HIGH, the pin becomes a permanent Active-HIGH/LOW output. If the

D term is always LOW (all fuses left intact), the pin now becomes an extra input.

PRESET AND RESET

The 10H20EV8/10020EV8 also includes a separate product term for asynchronous Preset and asynchronous Reset. These lines are common for all registers and are asserted when the specific product term goes HIGH.

Being asynchronous, they are independent of the clock. It should be noted that the actual state of the output is dependent on how the polarity of the particular output has been chosen. If the outputs are a mix of

Active-HIGH and Active-LOW, a Preset signal will force the Active-HIGH outputs

HIGH while the Active-LOW outputs would go

LOW, even though the Q output of all flip-flops would go HIGH. A Reset signal would force the opposite conditions.

PRELOAD

To simplify testing, the 10H20EV8/10020EV8 has also included PRELOAD circuitry. This allows a user to load any particular data desired into the registers regardless of the programmed pattern. This means that the

PRELOAD can be done on a blank part and after that same part has been programmed to facilitate any post-fuse testing desired.

It can also be used by a designer to help debug a circuit. This could be important if a state machine was implemented in the

10H20EV8/ 10020EV8. The PRELOAD would allow the entry of any state in the sequence desired and start clocking from that particular point. Any or all transitions could be verified.

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Philips Semiconductors Programmable Logic Devices	Product specification
ECL programmable array logic	10H20EV8/10020EV8

DC ELECTRICAL CHARACTERISTICS 10H20EV8

0°C ≤ Tamb ≤ +75°C, VEE = ±5.2V ± 5%, VCC = VCO1 = VCO2 = GND

				LIMITS4
SYMBOL	PARAMETER1	TEST CONDITIONS2	T	MIN	MAX	UNITS
			amb
VOH	High level output voltage	VIN = VIH MIN or VIL MAX	0°C	±1020	±840
			+25°C	±980	±810	mV
			+75°C	±920	±735
VOL	Low level output voltage	VIN = VIH MIN or VIL MAX	0°C	±1950	±1630
			+25°C	±1950	±1630	mV
			+75°C	±1950	±1600
IIH	High level input current	VIN = VIH MAX	0°C
			+75°C		220	μA
IIL	Low level input current	VIN = VIL MIN	0°C
		Except I/O Pins	+75°C	0.3		μA
±IEE	Supply current	VEE = MAX	0°C to +75°C
		All inputs = VIH MAX			250	mA

DC ELECTRICAL CHARACTERISTICS 10020EV8

0°C ≤ Tamb ≤ +85°C, ±4.8V ≤ VEE ≤ ±4.2V, VCC = VCO1 = VCO2 = GND

						LIMITS4
SYMBOL	PARAMETER1		TEST CONDITIONS2		MIN	TYP	MAX	UNITS
				VEE = ±4.2V	±1020		±870	mV
VOH	High level output voltage		VIN = VIH MAX or VIL MIN	VEE = ±4.5V	±1025	±955	±880	mV
				VEE = ±4.8V	±1035		±880	mV
		Outputs	Apply VIHMIN or VILMAX to	VEE = ±4.2V	±1030			mV
VOHT	High level output threshold voltage	Loaded	one input at a time, other	VEE = ±4.5V	±1035			mV
		with 50Ω	inuts at VIHMAX or VILMIN.	VEE = ±4.8V	±1045			mV
		to ±2.0V	Apply VIHMIN or VILMAX to	VEE = ±4.2V			±1595	mV
VOLT	Low level output threshold voltage	± 0.010V	one input at a time, other	VEE = ±4.5V			±1610	mV
			inuts at VIHMAX or VILMIN.	VEE = ±4.8V			±1610	mV
				VEE = ±4.2V	±1810		±1605	mV
VOL	Low level output voltage		Inuts at VIHMAX or VILMIN.	VEE = ±4.5V	±1810	±1705	±1620	mV
				VEE = ±4.8V	±1830		±1620	mV
IIH	High level input current	One input under test at VIHMAX. Other inputs at					220	μA
		VILMIN.
IIL	Low level input current	One input under test at VILMIN. Other inputs at			0.5			μA
		VIHMAX.
±IEE	VEE supply current	All inputs at VIHMAX.					230	mA

NOTES:

1.All voltage measurements are referenced to the ground terminal.

2.Each ECL 10KH/100K series device has been designed to meet the DC specification after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes, while maintaining transverse airflow of 2.5 meters/sec (500 linear feet/min.) over the device, mounted either in a test socket or on a printed circuit board. Test voltage values are given in the DC operating conditions table. Conditions for testing shown in the tables are not necessarily worst case. For worst case testing guidelines, refer to DC Testing, Chapter 1, Section 3, of the Philips Semiconductors 10/100K ECL Data Handbook.

3.Terminals not specifically referenced can be left electrically open. Open inputs assume a logic LOW state. Any unused pins can be

terminated to ±2V. If tied to VEE, it must be through a resistor > 10K. It is recommended that pins that have been programmed as RESET,

PRESET, or CLOCK inputs not be left open due to the possibility of false triggering from internally and externally generated switching transients.

4.The specified limits represent the worst case values for the parameter. Since these worst case values normally occur at the supply voltage and temperature extremes, additional noise immunity can be achieved by decreasing the allowable operating condition ranges.

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