查询PI6C103-05L供应商
PI6C103
Precision Clock Synthesizer
for Mobile PCs
Features
Two copies of CPU clock
100 MHz or 66.6 MHz operation
Six copies of PCI clock, (synchronous with CPU clock)
Two copies of REF clock @ 14.31818 MHz
One copy of 48 MHz
One copy of selectable 48/24 MHz
Power management control input pins
Isolated core VDD, VSS pins for noise reduction
28-pin SSOP (H) and TSSOP (L) packages
SSC Options:
Device 66 MHz 100 MHz
PI6C103 0.67% 0.65%
PI6C103-05 1.35% 1.35%
PI6C103-06 1.79% 1.79%
Block Diagram
XTAL_IN
XTAL_OUT
SPREAD#
SEL100/66#
SEL48#
REF
OSC
PLL1
PWR_DWN#
TS#
PLL2
DIV
CPU_STOP#
PCI_STOP#
÷2
MUX
2
2
5
PCICLK_F
48 MHz
48/24 MHz
REF
[0:1]
CPUCLK
[0:1]
PCICLK
[1:5]
Description
The PI6C103 is a high-speed, low-noise clock generator designed
to work with the PI6C18X clock buffer to meet all clock needs
for Mobile Intel Architecture platforms. System clock frequencies
of 66.6 MHz and 100 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers everything except the CPU clock. The 2.5V power supply is
used to power the CPUCLK outputs. 2.5V signaling follows JEDEC
standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is
not required.
An asynchronous PWR_DWN# signal may be used to orderly
power down (or up) the system. CPU and PCI clocks may also be
stopped by the CPU_STOP# and PCI_STOP# signals.
The PI6C103 contains the Spread Spectrum function for only those
clocks that synchronize to the CPU clocks (CPU and PCI clocks).
Pin Configuration
V
SS
XTAL_IN
XTAL_OUT
PCICLK_F
PCICLK1
PCICLK2
V
SS
V
DD
PCICLK3
PCICLK4
PCICLK5
V
DD
48 MHz
48-24MHz/TS#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-Pin
H, L
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
REF1/SEL48#
REF0/Spread#
V
DD
2
CPUCLK0
CPUCLK1
V
SS
2
V
SS
PCI_STOP#
V
DD
CPU_STOP#
PWR_DWN#
SEL100/66#
V
SS
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PS8315-2 04/08/99
Pin Description
PI6C103
Precision Clock Synthesizer for Mobile PCs
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411tuptuO#ST/zHM42-84
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82,91,21,81rewoPV
12,51,7,1rewoPV
521rewoPV
221rewoPV
Notes:
1. V
and VSS names in the above table reflect a likely internal power and ground partition to reduce the effects of internal noise on the performance
DD
of the device. In reality, the platform will be configured with the same voltage VDD pins tied to a common supply and all VSS pins being common.
The VDD/VSS naming convention above is done to show how the pinout is dominated by the need to isolate all the signals.
2. The output frequency at this pin is dependent on the power on strapping option at pin 27. A 48 MHz output when power-on strapped LOW,
and 24 MHz output when strapped HIGH. This pin also serves as Hi-Z state strapping option during power-on configuration. During power-on,
the PI6C103 will sample the value at this pin. Strapped LOW for Hi-Z state mode and HIGH for normal operation.
3. This is a dual function pin. During power-on, all clock outputs are disabled, and the PI6C103 will sample the spread spectrum enable/disable strapping
option. After the strapped value latches, all clock outputs will be enabled simultaneously and this pin will become a 14.318 MHz reference clock
output. The Power-on latency needs to be less than 3ms after the supply voltage stabilized.
4. This is a dual function pin. During power-on, all clocks are disabled, and PI6C103 will sample the SEL48# strapping option. After the strapped
value latches, all clock outputs will be enabled simultaneously and this pin will become another 14.318 MHz reference clock output. The poweron latency needs to be less than 3ms after the supply voltage stabilized.
5. Internally pulled up with resistor min.value of 50kΩ.
DD
SS
2DD
2SS
rewoPV3.3
dnuorGV3.3
rewoPV5.2
dnuorGV5.2
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2
PI6C103
234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901
Precision Clock Synthesizer for Mobile PCs
Select Functions
#66/001LES]1:0[KLCUPC
0zHM66
1zHM001
Function Description
#ST
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1lamroNzHM66/001zHM33zHM813.41zHM42/84zHM84
Clock Enable Configuration
#POTS_UPC#POTS_ICP#NWD_RWP
KLCUPC
]1:0[
XX 0 wolwolwoldeppotsffoffoffo
001wolwolzHM33gninnurgninnurgninnurgninnur
011wolzHM33zHM33gninnurgninnurgninnurgninnur
10 1 zHM66/001wolzHM33gninnurgninnurgninnurgninnur
111 zHM66/001zHM33zHM33gninnurgninnurgninnurgninnur
KLCICP
]5:1[
F_KLCICP
rehtO
skcolC
latsyrCs'OCVzHM84
224
PS8315-2 04/08/99
Power Management Timing
PI6C103
Precision Clock Synthesizer for Mobile PCs
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#POTS_UPC)delbasid(01
)delbane(11
#POTS_ICP)delbasid(01
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#NWD_RWP)noitarepolamron(1sm3
)nwodrewop(0.xam2
Notes:
1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs
between when the clock disable goes low/high to when the first valid clock comes out of
the device.
2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid
clocks are driven from the device.
CPU_STOP# is an input signal used to turn off the CPU clocks for low power operation. CPU_STOP# is asserted asynchronously
by the external clock control logic with the rising edge of free running PCI clock and is internally synchronized to the external
PCICLK_Foutput. All other clocks continue to run while the CPU clocks are disabled. The CPU clocks are always stopped in a low
state and started guaranteeing that the high pulse width is a full pulse. CPU clock on latency is 2 or 3 CPU clocks and CPU clock
off latency is 2 or 3 CPU clocks.
CPUCLK
(Internal)
CPUCLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
(External)
CPU_STOP# Timing Diagram
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only. This in fact may not be the way that the
control is designed.
3 CPU_STOP# is an input signal that must be made synchronous to the free running PCI_F.
4. ON/OFF latency shown in the diagram is 2 CPU clocks.
5. All other clocks continue to run undisturbed.
6. PWR_DWN# , PCI_STOP# are shown in a high state.
7. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
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PI6C103
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Precision Clock Synthesizer for Mobile PCs
PCI_STOP# is an input signal used to turn off PCI clocks for low
power operation. PCI clocks are stopped in the low state and started
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
PCICLK
(External)
Notes:
PCI_STOP# Timing Diagram
with a guaranteed full high pulse width. There is ONLY one rising
edge of external PCICLK after the clock control logic.
1. All timing is referenced to the CPUCLK.
2. PCI_STOP# signal is an input signal which must be made synchronous to PCI_F output.
3 Internal means inside the chip.
4. All other clocks continiue to run undisturbed.
5. PWR_DWN# CPU_STOP# are shown in a high state.
6. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
The PWR_DWN# is used to place the device in a very low power
state. PWR_DWN# is an asynchronous active low input. Internal
clocks are stopped after the device is put in power-down mode.
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN#
CPUCLK
(External)
PCICLK
(External)
VCO
Crystal
Notes:
PWR_DWN# Timing Diagram
The power-on latency is less than 3ms. PCI_STOP# and
CPU_STOP# are dont cares during the power-down operations.
The REF clock is stopped in the LOW state as soon as possible.
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part.
4. The Shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown wth respect to 66 MHz. Similar operations as CPU = 100 MHz.
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PS8315-2 04/08/99
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................65°C to +150°C
Ambient Temperature with Power Applied ............................. 0°C to +70°C
3.3V Supply Voltage to Ground Potential ............................. 0.5V to +4.6V
2.5V Supply Voltage to Ground Potential ............................. 0.5V to +3.6V
DC Input Voltage ................................................................... 0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics
(V
= +3.3V ± 5%, V
DDQ3
= +2.5V ± 5%, TA = 0°C to +70°C)
DDQ2
PI6C103
Precision Clock Synthesizer for Mobile PCs
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SS
227
PS8315-2 04/08/99
2
PI6C103
234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901
Precision Clock Synthesizer for Mobile PCs
DC Operating Specifications
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V
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228
PS8315-2 04/08/99
Buffer Specifications
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FER/ICP564.3-531.355-215epyT
Type 1: CPU Clock Buffers (2.5V)
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PI6C103
Precision Clock Synthesizer for Mobile PCs
I
NIMHO
I
XAMHO
I
NIMLO
I
XAMLO
t
HR
t
HF
tnerrucpu-lluPV
tnerrucpu-lluPV
tnerrucnwod-lluPV
tnerrucnwod-lluPV
Type 3: REF Buffers (3.3V)
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t
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t
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tnerrucpu-lluPV
tnerrucpu-lluPV
tnerrucnwod-lluPV
tnerrucnwod-lluPV
V0.1=87-
TUO
TUO
TUO
TUO
V573.2=76-
Am
V2.1=18
V3.0=06
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sn/V
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TUO
TUO
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Am
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V3.0=72
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sn/V
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Type 5: PCI Clock Buffers (3.3V)
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TUO
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V59.1=03
V4.0=83
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sn/V
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229
PS8315-2 04/08/99
2
PI6C103
234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901
Precision Clock Synthesizer for Mobile PCs
AC Timing
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230
PS8315-2 04/08/99
Host CLK
Host CLK
t
HPOFFSET
PCI CLK
PCI CLK
Precision Clock Synthesizer for Mobile PCs
1.25V
t
HSKW
1.25V
1.5V
t
PSKW
1.5V
Figure 1. Host Clock and PCI CLK Timing
1.25V
1.25V
1.5V
t
HPOFFSET
2.5V
V
SS
2.5V
V
SS
3.3V
V
SS
3.3V
V
SS
PI6C103
2.5V
Clocking
Interface
3.3V
Clocking
Interface
(TTL)
2.0
1.25
0.4
2.4
1.5
0.4
t
Hrise
Output
Buffer
tHKH
tPKH
Test Load
tHKP
Duty Cycle
t
Hfall
tPKP
Test
Point
tHKL
tPKL
t
Prise
t
Pfall
Figure 2. Clock Output Waveforms
231
PS8315-2 04/08/99
2
PI6C103
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Precision Clock Synthesizer for Mobile PCs
PCB Layout Suggestion
FB1
VCC
C1
22µF
C6
1
2
3
4
5
6
7
VSS
C2
VDD
8
9
10
11
12
VDD
13
14
C3
28
VDD
27
26
25
24
23
22
21
20
19
18
17
16
15
C5
VDD
VSS
VSS
C4
VDD
VSS
FB2
VCC
C7
22µF
Via to VDD Plane
Via to GND Plane
Void in Power Plane
Note:
This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C2-C6 should be placed as close as possible to
their respective VDD.
Recommended capacitor values:
C2-C6............... 0.1µF, ceramic
C1, C7 ............ 22µF
232
PS8315-2 04/08/99
Minimum and Maximum Expected Capacitive Loads
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PI6C103
Precision Clock Synthesizer for Mobile PCs
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Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.
2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.
3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an
additional 500Ω resistor in parallel.
Fp
sdaol2elbissop,daolecived1
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.
2. Minimize the number of vias of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock
traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
PI6C103
CPUCLK
PCICLK
REF
2
1 Device load
CL
6
Meets PCI2.1 Req.
CL
2
1 Device load
CL
Ordering Information
N/PnoitpircseD
H301C6IPegakcaPPOSSnip-82
Lxx-301C6IPegakcaPPOSSTnip-82
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
233
PS8315-2 04/08/99
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