PERICOM PI6C100 Technical data

REF0 1
REF1 2

V

SSREF

3

XTAL_IN 4

XTAL_OUT 5

V

SSPCI0

6

PCICLK_F 7

PCICLK1 8

V

DDPCI0

9
PCICLK2 10
PCICLK3 11

V

SSPCI1

12
PCICLK4 13
PCICLK5 14

V

DDPCI1

15
PCICLK6 16
PCICLK7 17

V

SSPCI

2

18

V

DDCORE0

19

V

SSCORE0

20

V

DD

48MHz 21
48MHz 22
48MHz 23

V

SS

48MHz 24

V

DDREF

REF2
V

DDAPIC

APIC0
APIC1
V

SSAPIC

NC
V

DDCPU0

CPUCLK0

48

CPUCLK1

47

V

SSCPU0

46

V

DDCPU1

45

CPUCLK2

44

CPUCLK3

43

V

SSCPU1

42

V

DDCORE1

41

V

SSCORE1

40

PCISTOP#

39

CPUSTOP#

38

PWRDWN#

37

SPREAD#

36

SEL0

35

SEL1

34

SEL100/66#

33
32
31
30
29
28
27
26

25

查询PI6C100V供应商

Features

 Four copies of CPU clock with VDD of 2.5V + 5%
 100 MHz or 66 MHz operation
 Eight copies of PCI clock, (synchronous with CPU clock) 3.3V
 Two copies of IO APIC clock @14.31818 MHz
 Two copies of 48 MHz clock
 Three copies of Ref. clock @14.31818 MHz (3.3V TTL)
 Low cost 14.31818 MHz crystal oscillator input
 Spread spectrum modulation of CPU and PCI clocks for

reduced EMI

 Power management control
 Isolated core VDD, VSS pins for noise reduction
 48-pin SSOP package (V48)

PI6C100

Precision Clock Synthesizer

for Desktop PCs

Description

The PI6C100 is a high-speed low-noise clock generator designed to
work with the PI6C180 clock buffer to meet all clock needs for Intel
Architecture platforms. CPU and chipset clock frequencies of 66.6
MHz and 100 MHz are supported.

Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs. 2.5V signaling follows JEDEC standard
8-X. Power sequencing of the 3.3V and 2.5V supplies is not required.

An asynchronous PWRDWN# signal may be used to orderly power
down (or up) the system.

Block Diagram

SEL100/66#

XTAL_IN

XTAL_OUT

SEL0,1

SPREAD#

REF

OSC

PLL1

PLL2

÷2

V

DDREF

V

DDAPIC

V

DDCPU 0,1

CPUSTOP#

V

DDPCI 0,1

PCISTOP#

VDD48MHz

Buffers

3

REF[0:2]

2

APIC0,1

4

CPUCLK[0:3]

7

PCICLK[1:7]

PCICLK_F

2

48MHz

198

Pin Configuration

48-Pin

V48

PS8142A 10/13/98

Pin Description

niPemaNlangiSepyT.ytQnoitpircseD

74,2,1]2:0[FERO3 .tuptuokcolczHM813.41

PI6C100

Precision Clock Synthesizer

for Desktop PCs

3V

84V

FERSS

FERDD

dnuorg1 stuptuo]2:0[FERrofdnuorG

rewop1 stuptuo]2:0[FERrofrewoP

4NI_LATXI1 .tupnilatsyrczHM813.41

5TUO_LATXO1 .tuptuolatsyrczHM813.41

81,21,6V

]2:0[dnuorg3 stuptuokcolcICProfdnuorG

ICPSS

7F_KLCICPO1 tuptuokcolcICPgninnureerF

51,9V

,31,11,01,8

71,61,41

33,91V

23,02V

12V

42V

DD

SS

]1:0[rewop2 stuptuokcolcICProfrewoP

ICPDD

]7:1[KLCICPO7

]1:0[rewop2 erocrofrewopdetalosI

EROCDD

]1:0[dnuorg2 erocrofdnuorgdetalosI

EROCSS

zHM84rewop1 stuptuozHM84rofrewopdetalosI

zHM84dnuorg1 stuptuozHM84rofdnuorgdetalosI

V3.3elbitapmoc

32,22zHM84O2stuptuozHM84

72,62]1:0[LES12 slevelLTTVL.sniptcelescigoL

52#66/001LESI1

LTT,stuptuokcolcICP

zHM66rozHM001gnilbanerofniptceleS

zHM66=L.zHM001=H

92#NWDRWPI1 WOLdlehnehwecivednwodsrewoP

03#POTSUPCI WOLdlehfiWOLskcolcUPCspotS

13#POTS_ICPI1 WOLdlehfiWOLskcolcICPspotS

14,73V

83,43V

]1:0[rewop2 stuptuoUPCrofrewoP

UPCDD

]:0[dnuorg2 stuptuoUPCrofdnuorG

UCPSS

04,93,63,53]3:0[KLCUPCO4 V5.2stuptuokcolctsoHdnaUPC

34V

64V

CIPASS

CIPADD

dnuorg1 stuptuoCIPArofdnuorG

rewop1 stuptuoCIPArofrewoP

54,44]1:0[CIPAO2 zHM81813.41.V5.2@stuptuoCIPA

82#DAERPSI1 WOLnehwerutaefmurtcepSdaerpSselbanE

24CN1 noitacifidomerutufrofdevreseR

199

PS8142A 10/13/98

Select Functions

#66/001LES1LES0LESnoitcnuF

000 Z-iH

001 devreseR

010 devreseR

011 evitcazHM66

100 edomtseT

101 devreseR

110 devreseR

111 evitcazHM001

PI6C100

Precision Clock Synthesizer

for Desktop PCs

noitcnuF

noitpircseD

Z-iHZ-iHZ-iHZ-iHZ-iHZ-iH

edoMtseT2/KLCT6/KLCT2/KLCTKLCTKLCT

Note:

TCLK is a test clock over driven on the XTAL_IN input during test mode.

UPCFICP,ICPzHM84]2:0[FERCIPAOI

stuptuO

Clock Enable Configuration

#POTS_UPC#POTS_ICP#NWD_RWPKLCUPCKLCICP

XX0wolwoldeppotSffoffo

001wolwolgninnurgninnurgninnur

011wolzHM33gninnurgninnurgninnur

101

66/001

zHM

rehtO

skcolC

wolgninnurgninnurgninnur

latsyrCs'OCV

111

66/001

zHM

200

zHM33gninnurgninnurgninnur

PS8142A 10/13/98

PI6C100

Precision Clock Synthesizer

for Desktop PCs

CPU_STOP# is an input signal used to turn off the CPU clocks
for low power operation. CPU_STOP# is asserted asynchronously
by the external clock control logic with the rising edge of free
running PCI clock and is internally synchronized to the external
PCICLK_F output.

All other clocks continue to run while the CPU clocks are disabled.
The CPU clocks are always stopped in a low state and started
guaranteeing that the high pulse width is a full pulse. CPU clock
on latency is 2 or 3 CPU clocks and CPU clock off latency is 2 or
3 CPU clocks.

Power Management Timing

langiSetatSlangiS

#POTS_UPC)delbasid(01

)delbane(11

#POTS_ICP)delbasid(01

)delbane(11

#NWD_RWP)noitarepolamron(1sm3

nwodrewop(0.xam2

Notes:

1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs between
when the clock disable goes low/high to when the first valid clock comes out of the device.

2. Power up latency is from when PWR_DWN# goes inactive (high) to when the first valid clocks
are driven from the device.

ycnetaL

KLCICPgninnureerffosegdegnisirfo.oN

CPUCLK
(Internal)

CPUCLK
(Internal)

PCICLK_F

(Free-running)

CPU_STOP#

PCI_STOP#

PWR_DWN#

CPUCLK

(External)

CPU_STOP# Timing Diagram

Notes:

1. All timing is referenced to the CPUCLK.

2. The Internal label means inside the chip and is a reference only.
3 CPU_STOP# is an input signal that is made synchronous to the free running PCICLK_F.

4. ON/OFF latency shown is 2 CPU clocks.

201

PS8142A 10/13/98

PI6C100

Precision Clock Synthesizer

for Desktop PCs

PCI_STOP# is an input signal used to turn off the PCI clocks for low power operation. PCI clocks are stopped in the low state and started
with a guaranteed full high pulse width. There is ONLY one rising edge of external PCICLK after the clock control logic.

CPUCLK
(Internal)

PCICLK

(Internal)

PCICLK_F

(Free-running)

CPU_STOP#

PCI_STOP#

PWR_DWN#

PCICLK

(External)

PCI_STOP# Timing Diagram

Notes:

1. All timing is referenced to the CPUCLK.

2. The Internal label means inside the chip and is a reference only.

The PWR_DWN# is used to place the device in a very low power state. PWR_DWN# is an asynchronous active low input. Internal clocks
are stopped after the device is put in power down mode. The power on latency is less than 3ms. PCI_STOP# and CPU_STOP# are dont
cares during the power down operations. The REF0 clock is stopped in the LOW state as soon as possible.

CPUCLK
(Internal)

PCICLK

(Internal)

PWR_DWN#

CPUCLK

(External)

PCICLK

(External)

VCO

Crystal

PWR_DWN# Timing Diagram

Notes:

1. All timing is referenced to the CPUCLK.

2. The Internal label means inside the chip and is a reference only.

3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part.

4. The shaded sections on the VCO and the Crystal signals indicate an active clock.

202

PS8142A 10/13/98

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature ................................................................... 65°C to +150°C

Ambient Temperature with Power Applied .................................... 0°C to +70°C

3.3V Supply Voltage to Ground Potential ....................................... 0.5V to +4.6V

2.5V Supply Voltage to Ground Potential ....................................... 0.5V to +3.6V

DC Input Voltage ............................................................................ 0.5V to +4.6V

PI6C100

Precision Clock Synthesizer

for Desktop PCs

Note:

Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.

DC Electrical Characteristics (V

sretemaraPnoitpircseDsnoitidnoCtseT.niM.pyT.xaMstinU

I

LI

V

LI

V

HI

V

LO

V

HO

I

2QDD

I

2QDD

I

2QDD

I

3QDD

I

3QDD

I

3QDD

tnerruCegakaeLtupnIV<V0

egatloVwoLtupnIV

egatloVhgiHtupnIV@

egatloVwoLtuptuOI

egatloVhgiHtuptuOI

tnerruCylppuSV5.2

tnerruCylppuSV3.3

3 = +3.3V ± 5%, V

DDQ

NI

DD

LO

LO

V

2QDD

C

DAOL

V

2QDD

C

DAOL

V

2QDD

C

DAOL

V

3QDD

C

DAOL

V

3QDD

C

DAOL

V

3QDD

C

DAOL

2 = +2.5V ± 5%, TA = 0°C to +70°C)

DDQ

V<

DD

5-5+

3.0-8.0

SS

0.2+V

3.0+

DD

µA

V

V,Am1=

DD

V,Am1-=

.xaM=

.xaM=

.niM=4.0

DD

.niM=2

0=#NWDRWP,V526.2=

zHM66.66@V526.2=

001

µA

27

Am

zHM001@V526.2=

.xaM=

0=#NWDRWP,V564.3=

.xaM=

zHM66.66,V564.3=

.xaM=

001

005

µA

071

Am

zHM001,V564.3=

.xaM=

071

C

NI

ecnaticapaCtupnI 5

Fp

C

TUO

L

NIP

T

A

ecnaticapaCtuptuO 6

ecnatcudnoCniP 7Hn

erutarepmeTtneibmAwolfriAoN007C°

203

PS8142A 10/13/98

DC Operating Specifications

lobmySsretemaraPsnoitidnoC.niM.xaMstinU

PI6C100

Precision Clock Synthesizer

for Desktop PCs

V,egatloVtupnI

V

3HI

]1-0[%5±V3.3=

EROCDD

egatlovhgihtupnIV

EROCDD

0.2V

3.0+

EROCDD

V

V

3LI

I

LI

V

2HO

egatlovwoltupnIV

tnerrucegakaeltupnIV<0

V%5±V5.2=egatloVtuptuO

CIPADD

,V

egatlovhgihtuptuOI

V<

NI

UPCDD

HO

EROCDD

]1-0[

Am1-=0.2

3.0-8.0

SS

5-5+

µA

V

V

2LO

V

3HO

egatlovwoltuptuOI

V%5±V3.3=egatloVtuptuO

FERDD

egatlovhgihtuptuOI

HO

Am1=4.0

LO

Am1-=4.2

V

V

3LO

V

HOP

egatlovwoltuptuOI

V%5±V3.3=egatloVtuptuO

IPCDD

egatlovhgihtuptuosuBICPI

LO

]1-0[

HO

Am1=4.0

Am1-=4.2

V

V

LOP

C

NI

C

X

LATX

LAT

egatlovwoltuptuosuBICPI

LO

ecnaticapacniptupnI5

ecnaticapacsnip5.310.815.22

Am1=55.0

Fp

C

TUO

L

NIP

T

A

ecnatcudnIniP7Hn

ecnaticapacniptuptuO6

erutarepmeTtneibmAwolfriaoN007C°

204

PS8142A 10/13/98

Buffer Specifications

PI6C100

Precision Clock Synthesizer

for Desktop PCs

emaNreffuBV

DD

)V(egnaR(ecnadepmI ΩΩΩΩΩ)epyTreffuB

UPC526.2-573.254-5.311epyT

CIPA526.2-573.203-92epyT

FER,zHM84564.3-531.306-023epyT

ICP564.3-531.355-214epyT

Type 1: CPU Clock Buffers (2.5V)

lobmySsretemaraPsnoitidnoC.niM.pyT.xaMstinU

I

NIMHO

I

XAMHO

I

NIMLO

I

XAMLO

t

HR

t

HF

tnerrucpu-lluPV

tnerrucpu-lluPV

Type 2: APIC Buffers (2.5V)

V0.1=72-

TUO

TUO

tnerrucnwod-lluPV

tnerrucnwod-lluPV

TUO

TUO

V573.2=72-

Am

V2.1=72

V3.0=03

etaregdeesirtuptuo1epyTV5.2V0.2-V4.0@%5-/+V5.214

sn/V

etaregdellaftuptuo1epyTV5.2V4.0-V0.2@%5-/+V5.214

lobmySsretemaraPsnoitidnoC.niM.pyT.xaMstinU

I

NIMHO

I

XAMHO

I

NIMLO

I

XAMLO

t

HR

t

HF

tnerrucpu-lluPV

tnerrucpu-lluPV

tnerrucnwod-lluPV

tnerrucnwod-lluPV

Type 3: 48MHz, REF Buffers (3.3V)

lobmySsretemaraPsnoitidnoC.niM.pyT.xaMstinU

I

NIMHO

I

XAMHO

I

NIMLO

I

XAMLO

t

HR

t

HF

tnerrucpu-lluPV

tnerrucpu-lluPV

tnerrucnwod-lluPV

tnerrucnwod-lluPV

V4.1=63-

TUO

V5.2=12-

TUO

Am

V0.1=63

TUO

V2.0=13

TUO

etaregdeesirtuptuo2epyTV5.2V0.2-V4.0@%5±V5.214

sn/V

etaregdellaftuptuo2epyTV5.2V4.0-V0.2@%5±V5.214

V0.1=92-

TUO

TUO

V531.3=32-

Am

TUO

TUO

V59.1=92

V4.0=72

etaregdeesirtuptuo3epyTV3.3V4.2-V4.0@%5±V3.35.02

sn/V

etaregdellaftuptuo3epyTV3.3V4.0-V4.2@%5±V3.35.02

205

PS8142A 10/13/98

Type 4: PCI Clock Buffers (3.3V)

lobmySsretemaraPsnoitidnoC.niM.pyT.xaMstinU

PI6C100

Precision Clock Synthesizer

for Desktop PCs

I

NIMHO

I

XAMHO

I

NIMLO

I

XAMLO

t

HR

t

HF

AC Timing

t

PKH

t

HKH

t

LKH

t

ESIRH

t

tnerrucpu-lluPV

tnerrucpu-lluPV

tnerrucnwod-lluPV

TUO

TUO

tnerrucnwod-lluPV

V0.1=33-

TUO

V531.3=33-

V59.1=03

V4.0=83

TUO

etaregdeesirtuptuo4epyTV3.3V4.2-V4.0@%5±V3.314

etaregdellaftuptuo4epyTV3.3V4.0-V4.2@%5±V3.314

otkcolCtsoH.1erugiF

tesffOKLCICP

sretemaraP

zHM66zHM001

.niM.xaM.niM.xaM

)V5.2(doirepKLCtsoH0.515.510.015.01

)V5.2(emithgihKLCtsoH2.50.3

)V5.2(emitwolKLCtsoH0.58.2

)V5.2(emitesirKLCtsoH4.06.14.06.1

)V5.2(emitllafKLCtsoH4.06.14.06.1

LLAFH

Am

sn/V

stinU

sn

t

RETTIJ

)V5.2(rettiJKLCtsoH052052sp

)V5.2(elcyCytuDV52.1taderusaeM54555455%

t

WKSH

)V5.2(wekSKLCsuBtsoH571571

sp

t

WKSOI

t

t,

LZP

HZP

wekSKLCsuBCIPAOI052052

yaledelbanetuptuO0.10.80.10.8

sn

t

t,

ZLP

ZHP

t

BTSH

t

PKP

t

SPKP

t

HKP

yaledelbasidtuptuO0.10.80.10.8

pu-rewopmorfnoitazilibatSKLCtsoH33sm

doirepKLCICP0.03

∝

0.03

ytilibatsdoirepKLCICP005005sp

emithgihKLCICP0.210.21

∝

sn

sn

t

LKP

t

WKSP

t

TESFFOPH

t

BTSP

emitwolKLCICP0.210.21

wekSKLCsuBICP005005sp

tesffOkcolCICPottsoH5.10.45.10.4sn

pu-rewopmorfnoitazilibatSKLCICP33sm

206

PS8142A 10/13/98

Host CLK

Host CLK

t

HPOFFSET

PCI CLK

PCI CLK

1.25V

1.25V

t

HSKW

1.5V

t

1.5V

PSKW

1.25V

1.25V

t

1.5V

Precision Clock Synthesizer

HPOFFSET

2.5V

V

SS

2.5V

V

SS

3.3V

V

SS

3.3V

V

SS

PI6C100

for Desktop PCs

2.5V
Clocking
Interface

Figure 1. Host Clock to PCI CLK Offset

Test
Point

Test Load

tHKP

t

Hfall

tPKP

2.0

1.25

0.4

t

Hrise

Output
Buffer

Duty Cycle

tHKH

tPKH

tHKL

3.3V
Clocking
Interface

(TTL)

2.4

1.5

0.4

t

Prise

t

Pfall

Figure 2. Clock Output Waveforms

207

tPKL

PS8142A 10/13/98

Minimum and Maximum Expected Capacitive Loads

kcolCdaoL.niMdaoL.xaMstinUsetoN

PI6C100

Precision Clock Synthesizer

for Desktop PCs

)KLCH(skcolCUPC0102

sdaol2elbissop,daolecived1

)KLCP(skcolCICP0303stnemeriuqer1.2ICPsteeM

kcolCzHM840102daolecived1

Fp

FER0102daolecived1

CIPA0102sdaolecived2

Notes:

1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.

2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.

3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an
additional 500W resistor in parallel.

Design Guidelines to Reduce EMI

1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for

CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still
within the specified values.

2. Minimize the number of vias of the clock traces.

3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock

traces from plane to plane (refer to rule #2).

4. Position clock signals away from signals that go to any cables or any external connectors.

PI6C100

CPUCLK

PCICLK

REF

APIC

48MHZ

4

8

3

2

2

33

Ω

33

Ω

22Ω/33

33

Ω

22

Ω

1 Device load

CL

Meets PCI2.1 Req.

CL

Ω

1 Device load

CL

2 Device loads

CL

1 Device load

CL

208

PS8142A 10/13/98

PCB Layout Suggestion

FB1

VCC

C1

22uF

C2

C3

C4

C5

C6

VSS

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

VDD

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

C11

C10

C9

C8

C7

PI6C100

Precision Clock Synthesizer

for Desktop PCs

FB2

VCC (CPU)

C12

22uF

Via to VDD Plane

Via to GND Plane

Void in Power Plane

Note:

This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C2-C11 should be placed as close as possible
to their respective VDD.

Recommended capacitor values:

C2-C11.............. 0.1µF, ceramic

C1, C12 ........... 22µF

209

PS8142A 10/13/98

48-Pin SSOP Package Data

48

PI6C100

Precision Clock Synthesizer

for Desktop PCs

1

Table of Dimensions

.620
.630

15.75

16.00

.025 BSC

0.635

.395

.291

.420

.299

7.39

10.03

7.59

10.67

.008

.008
.0135

0.20

0.34

X.XX

DENOTES DIMENSIONS

X.XX

IN MILLIMETERS

0.20

Nom.

0-8˚

Gauge Plane

0.25

.010

DENOTES DIMENSIONS

0.381

.015

0.635

.025

X.XX
X.XX

IN MILLIMETERS

x 45˚

.02
.04

0.51

1.01

.008
.016

.110

0.20

0.40

2.79

Max

ydoB)htdiW(E)htgneL(D)thgieH(A)hctipniP-ot-niP(e

snip84.niM192.0026.0590.0520.0

)lim003(.xaM992.0036.0011.0-

Ordering Information

N/PnoitpircseD

V001C6IPegakcaPPOSSnip-84

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax [phone] • http://www.pericom.com

210

PS8142A 10/13/98