PERIC PI29FCT2520T, PI29FCT520T, PI29FCT521T Datasheet

PI29FCT520T/2520T

PI29FCT521T

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Fast CMOS Multilevel Pipeline Registers

Product Features:

•PI29FCT520T and PI29FCT521T are pinout and function compatible with IDT29FCT520/521, QS29FCT520/521 and AMD's Am29520/521

•Four 8-bit high-speed registers

•Hold, Transfer, and load instructions

•Dual two-level or single four-level pipeline operation

•TTL input and output levels, reducing problematic "ground bounce"

•High output drive

IOL = 48 mA

•Extremely low static power (1 mW, typ.)

•Industrial operating temperature range: –40°C to +85°C

• FCT (2xxxT) has a 25 Ω series resistor.

•Packages available:

–24-pin 300 mil wide plastic DIP (P24)

–24-pin 150 mil wide plastic QSOP (Q24)

–24-pin 150 mil wide plastic TQSOP (R24)

–24-pin 300 mil wide plastic SOIC (S24)

Product Description:

Pericom Semiconductor’s PI29FCT series of logic circuits are pro-duced in the Company’s advanced 0.8 micron CMOS technology, achieving industry leading speed grades.

The PI29FCT520T/2520T and PI29FCT521T are multilevel pipeline registers containing four 8-bit positive triggered registers which can be configured as a dual 2-level or a single 4-level pipeline. These products are designed for use as temporary storage or for storage delays in pipelined systems.

The PI29FCT521T differs from the PI29FCT520T/2520T only in the way data is loaded into and between registers in the dual 2-level operation. When data is entered into the first level (I = 2 or I = 1) of the PI29FCT520T/2520T, the existing data in the first level is moved to the second level. In the PI29FCT521T, these instructions simply overwrite the data in the first level. Transfer of data to the second level is achieved using the 4-level shift instruction (I = 0) causing the first level to change. In either part, I = 3 shift instruction puts the registers on hold.

Device models available upon request.

Logic Block Diagram
			D0–D7
			8
			MUX
2
I0,I1
	REGISTER
	CONTROL	OCTAL	OCTAL
		REGISTER A1	REGISTER B1
1
CLK
		OCTAL	OCTAL
		REGISTER A2	REGISTER B2
		2
		S0,S1	MUX
		OE
			8
			Y0–Y7
		1	PS2002B	12/10/96
FCT520.pm6	1		12/18/96, 4:44 PM

PI29FCT520/521T/2520T

MULTILEVEL PIPELINE REGISTERS

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Product Pin Configuration

Product Pin Description

I0		1		24			VCC
I1		2		23			S0
D0		3		22			S1
D1		4		21			Y0
D2		5	24-PIN	20			Y1
D3		6	P24	19			Y2
			Q24
D4	7			18			Y3
D5		8	R24	17			Y4
			S24
D6		9		16			Y5
D7		10		15			Y6
CLK							Y7
		11		14
GND		12		13			OE

Register Selection

S1	S0	Register
0	0	B2
0	1	B1
1	0	A2
1	1	A1

PI29FCT520/T2520T Data Loading

Pin Name			Description
			Output Enable Input (Active LOW) for
	OE
			3-State Output Port
CLK			Clock Input. Enter data into registers on
			LOW-to-HIGH transistions
I0,I1			Instruction Inputs
S0,S1			Multiplexer Select. Inputs either register
			A1, A2, B1, or B2 data to be avaialbe at the
			output ports
Dx			Register Inputs
Yx			Register Outputs
GND			Ground
VCC			Power

DUAL 2-LEVEL

SINGLE 4-LEVEL

A1

B1

A1

B1

A1

B1

A2

B2

A2

B2

A2

B2

I = 2

I = 1

I = 0

NOTE: I = 3 FOR HOLD

PI29FCT521T Data Loading

DUAL 2-LEVEL

SINGLE 4-LEVEL

A1

B1

A1

B1

A1

B1

A2

B2

A2

B2

A2

B2

I = 2

I = 1

I = 0

NOTE: I = 3 FOR HOLD

2	PS2002B	12/10/96

FCT520.pm6

2

12/18/96, 4:44 PM