PERIC GTLP6C816 Datasheet

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GTLP6C816

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GTLP-to-TTL 1:6 Clock Driver

Features

Bidirectional interface between GTLP and TTL logic levels

Designed with Edge Rate Control Circuit to reduce output noise on the GTLP port

Power up/down high impedance for live insertion

1:6 fanout clock driver for TTL port

Lower Drive (12mA) on TTL Port to reduce noise

1:2 fanout clock driver for GTLP port

TTL compatible driver and control inputs

Flow -through architecture optimizes PCB layout

Open drain on GTLP to support wired-or connection

Operating Temperature: –40°C to +85°C

Package:

–24-Pin173milwideplasticTSSOP(L24)

ProductDescription

PericomSemiconductor’sGTLPseriesoflogiccircuitsareproduced using the Company’s advanced 0.5 micron CMOS technology, achieving industry leading performance.

The GTLP6C816 is a clock driver that provides TTL to GTLP signal level translation (and vice versa). The device provides a high-speed interfacebetweencardsoperatingatTTLlogiclevelsandabackplane operating at GTLP logic levels. High-speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels, and output edge-rate control which minimizes bus settling times.

Pericom’sGTLPhasinternaledge-ratecontrol.Itsfunctionissimilar toBTLorGTLbutwithdifferentoutputlevelsandreceiverthreshold. GTLP output low voltage is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.

Logic Block Diagram

PinConfiguration

OEB

OB0

TTLIN

OB1

OEA

 

GTLP

OA0

Ports

 

OA1

 

TTL

 

Ports

GTLPIN

 

OA5

 

 

 

 

 

 

 

 

 

 

 

 

TTLIN

 

 

1

 

24

 

 

GNDT

 

 

 

 

 

 

 

2

 

23

 

 

 

 

 

OA0

 

 

 

 

 

OEB

 

 

 

 

GNDT

 

3

 

22

 

 

OB0

OA1

 

4

 

21

 

 

GNDG

VCCT

 

5

24-Pin

20

 

 

VREF

 

 

 

OA2

 

6

19

 

 

GNDG

GNDT

 

 

7

L

18

 

 

VCC

 

 

 

 

OA3

 

8

 

17

 

 

OB1

VCCT

 

9

 

16

 

 

GNDG

 

 

 

 

OA4

 

10

 

15

 

 

GTLPIN

GNDT

 

11

 

 

 

 

 

 

 

 

 

 

14

 

 

OEA

 

 

 

 

OA5

 

12

 

13

 

 

GNDT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

PS8426A

03/15/00

GTLP6C816

GTLP-to-TTL1:6ClockDriver

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FunctionalDescription

The GTLP6C816 is a clock driver that provides TTL to GTLP clock

FortheGTLP-to-TTLdirection,theclockreceiverpathisa1:6buffer

translation, and GTLP-to-TTL clock translation. The TTL-to-GTLP

with a single Enable control (OEA). Data polarity is inverting for

direction is a 1:2 clock driver path with a single Enable pin (OEB).

both directions.

Pin Descriptions

Pin Names

Description

 

 

 

 

 

 

TTLIN, GTLPIN

Clock Inputs (TTL and GTLP respectively)

 

 

 

 

 

 

 

 

 

Output Enable (Active LOW) GTLP Port (TTL Levels)

 

 

OEB

 

 

 

 

 

 

 

 

 

 

Output Enable (Active LOW) TTL Port (TTL Levels)

OEA

 

 

 

 

 

 

VCCT, GNDT

TTL Output Supplies (5V)

 

 

 

 

 

 

VCC

Internal Circuitry VCC (5V)

 

 

 

 

 

 

GNDG

OBn GTLP Output Grounds

 

 

 

 

 

 

VREF

Voltage Reference Input

 

 

 

 

 

 

OA0 - OA5

TTL Buffered Clock Outputs

 

 

 

 

 

 

OB0 - OB5

GTLP Buffered Clock Outputs

 

 

 

 

 

 

TruthTable

Inputs

 

 

 

 

Outputs

 

 

 

 

 

 

 

TTLIN

 

 

 

 

OBn

 

OEB

 

 

 

 

 

 

 

H

 

 

L

L

 

 

 

 

 

 

 

L

 

 

L

H

 

 

 

 

 

 

 

X

 

 

H

High Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GTLPIN

 

OEA

OAn

 

 

 

 

 

 

 

H

 

 

L

L

 

 

 

 

 

 

 

L

 

 

L

H

 

 

 

 

 

 

 

X

 

 

H

High Z

 

 

 

 

 

 

 

2

PS8426A

03/15/00

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