PERIC GTLP16612AA Datasheet

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GTLP16612A

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CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

Features

Bidirectional interface between GTLP and TTL logic levels

Designed with Edge Rate Control Circuit to reduce output noise

VREF pin provides external supply reference voltage for receiver threshold

5V tolerant inputs and outputs on A-Port

Increased B-Port Drive, 50mA

Bus-Hold data inputs on A-Port to eliminate the need for pull-up resistors for unused inputs

Power up/down high impedance

TTL compatible Driver and Control inputs

ProductDescription

PericomSemiconductor’sGTLPseriesoflogiccircuitsareproduced using the Company’s advanced 0.5 micron CMOS technology, achieving industry leading performance.

TheGTLP16612A18-bituniversaltransceiverprovidesTTLtoGTLP signal level translation. The device is designed to provide highspeed interface between cards operating at TTL logic levels and a back plane operating at GTLP logic levels. High-speed back plane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels, and output edge-rate control which minimizes signal settling times. Its function is similar to BTL or GTL but with modified driver output levels and receiver threshold. GTLP outputlowvoltageistypicallylessthan0.5V,theoutput highis1.5V, and the receiver threshold is 1.0V.

• A-Port Balanced Drive: –32mA/+32mA

PinConfiguration

 

Flow-through architecture

Open drain on GTLP to support wired-or connection

Package:

 

 

 

OEAB

1

 

56

CEAB

 

 

 

LEAB

2

 

55

CLKAB

 

— 56-pin 240 Mil Wide Plastic TSSOP (A)

 

 

 

 

 

 

A1

3

 

54

B1

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

4

 

53

GND

 

 

 

 

 

 

A2

5

 

52

B2

 

 

 

 

 

 

A3

6

 

51

B3

Logic Block Diagram

 

 

 

VCC(3.3V)

7

 

50

VCCQ(5.0V)

 

 

 

 

 

 

A4

8

 

49

B4

 

 

1

 

 

 

A5

9

 

48

B5

 

OEAB

 

 

 

 

 

 

CEAB

56

 

 

 

A6

10

 

47

B6

 

 

 

 

 

 

 

 

 

 

 

 

55

 

 

 

GND

11

 

46

GND

 

CLKAB

 

 

 

A7

12

56-Pin

45

 

 

 

 

 

 

B7

 

 

 

 

 

 

 

 

A,V

 

 

LEAB

2

 

 

 

A8

13

44

B8

 

 

 

 

 

 

 

 

28

 

 

 

A9

14

 

43

B9

 

LEBA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

42

B10

 

 

 

 

 

 

A10

 

 

CLKBA

30

 

 

 

A11

16

 

41

B11

 

 

 

 

 

 

 

CEBA

29

 

 

 

A12

17

 

40

B12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

18

 

39

GND

 

OEBA

27

 

1 of 18 Channels

 

 

 

 

 

 

 

 

 

 

A13

19

 

38

B13

 

 

 

 

 

 

 

 

 

 

CE

 

 

A14

20

 

37

B14

 

 

3

 

 

 

 

 

 

 

 

A1

1D

54

 

A15

21

 

36

B15

 

 

 

 

 

 

 

 

CI

GTLP

B1

 

 

 

 

 

 

 

 

 

 

VCC(3.3V)

22

 

35

VREF

 

 

 

VCLK

 

 

 

 

 

 

CE

 

 

A16

23

 

34

B16

 

 

 

1D

 

 

 

 

 

 

 

 

A17

24

 

33

B17

 

 

 

CI

 

 

 

 

 

 

CLK V

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

25

 

32

GND

 

 

 

 

 

 

A18

26

 

31

B18

 

 

 

 

 

 

OEBA

27

 

30

CLKBA

 

 

 

 

 

 

LEBA

28

 

29

CEBA

 

 

 

1 of 18 Channels

 

 

 

 

 

 

 

1

PS8431

09/24/99

 

 

 

 

 

 

 

 

 

 

 

 

 

GTLP16612A

 

 

 

 

 

 

 

 

 

 

 

CMOS18-BitTTL/GTLP

 

 

 

 

 

 

 

 

 

 

 

Universal Bus Transceiver

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Pin Descriptions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Names

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A-to-B Output Enable (Active LOW)

 

 

OEAB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B-to-A Output Enable (Active LOW)

 

 

OEBA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A-to-B Clock Enable (Active LOW)

 

 

 

 

 

CEAB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B-to-A Clock Enable (Active LOW)

 

 

 

CEBA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LEAB

A-to-B Latch Enable (Transparent HIGH)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LEBA

B-to-A Latch Enable (Transparent HIGH)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKAB

A-to-B Clock Pulse

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKBA

B-to-A Clock Pulse

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF

GTLP Input Reference Voltage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1-A18

A-to-B TTL Data Inputs or

 

 

B-to-A 3-State Outputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B1-B18

B-to-A GTLP Data Inputs or

 

 

 

 

 

 

 

 

 

 

 

A-to-B Open Drain Outputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FunctionalDescription

The PI74GTLP16612A combines a universal transceiver function with a TTL to GTLP translation. The A-Port and control pins operate at LVTTL or 5V TTL levels while the B-Port operates at GTLP levels. The transceiver logic includes D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clock mode. The functional operation is described below:

TruthTable(1)

 

 

 

 

 

 

Inputs

 

 

Output B

Mode

 

 

 

 

 

 

 

 

 

 

CEAB

 

 

OEAB

 

LEAB

CLKAB

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

H

X

X

X

Z

Latched

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B0(2)

 

L

 

L

L

H

X

Storage

 

 

 

 

 

 

 

 

 

 

of A Data

 

L

 

L

L

L

X

B0(3)

 

 

 

 

X

 

L

H

X

L

L

Transparent

 

 

 

 

 

 

 

 

 

 

 

X

 

L

H

X

H

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

L

L

L

Clocked Storage

 

L

 

L

L

H

H

of A Data

 

 

 

 

 

 

 

 

 

 

 

 

H

 

L

L

X

X

B0(3)

Clock Inhibit

Notes:

1.A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.

2.Output level before indicated steady-state input conditions were established, provided CLKAB was HIGH before LEAB went LOW.

3.Output level before indicated steady-state input conditions were established.

2

PS8431

09/24/99

 

 

 

 

 

 

GTLP16612A

 

 

 

 

CMOS18-BitTTL/GTLP

 

 

 

 

Universal Bus Transceiver

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Absolute Maximum Ratings(4)

 

 

 

(Above which the useful life may be impaired. For user guidelines, not tested.)

 

 

 

 

 

 

 

Storage Temperature (TSTG) ...............................................

–65°Cto+150°C

 

 

 

Supply Voltage (VCC, VCCQ) ...................................................

–0.5Vto+7.0V

 

 

 

DC Input Voltage (VI) ...........................................................

–0.5Vto+7.0V

 

 

 

DC Output Voltage (VO)

 

 

 

 

Outputs 3-State ..................................................................

–0.5Vto+7.0V

 

 

 

Outputs Active(5) ........................................................

–0.5VtoVCC +0.5V

 

 

 

DC Output Current into A-Port IOH /IOL ...............................

–64mA/+64mA

 

 

 

DC Output Sink Current into B-Port in LOW State IOL ......................

100mA

 

 

 

DC Input Diode Current (IIK)

 

 

 

 

VI < 0V ............................................................................................

–50mA

 

 

 

DC Output Diode Current (IOK)

 

 

 

 

VO < 0V ...........................................................................................

–50mA

 

 

 

VO > VCC ..........................................................................................

+50mA

 

 

 

ESDPerformance ..............................................................................

>2000V

 

 

 

 

 

 

 

Recommended Operating Condition(6)

 

 

 

 

Supply Voltage (VCC)

 

 

 

 

VCC .......................................................................................

3.15Vto3.45V

 

 

 

VCCQ .....................................................................................

4.75Vto5.25V

 

 

 

Bus Termination Voltage (VTT) ..............................................

1.35Vto1.65V

 

 

 

Input Voltage (VI) on A-Port and Control Pins ........................

0.0Vto5.5V

 

 

 

HIGH Level Output Current (IOH)

 

 

 

 

A-Port ............................................................................................

–32mA

 

 

 

LOW Level Output Current (IOL)

 

 

 

 

A-Port ............................................................................................

+32mA

 

 

 

B-Port .............................................................................................

+50mA

 

 

 

Operating Temperature (TA) ................................................

–40°C to +85°C

 

 

 

 

 

 

 

Notes:

4.The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristic tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

5.IO Absolute Maximum Rating must be observed

6.Unused inputs must be held HIGH or LOW.

3

PS8431

09/24/99

 

 

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