Pentek 6230, 6231 Operating Manual

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Page 1

Pentek Model 6230/6231 Operating Manual Page 1

OPERATING MANUAL

MODEL 6230/6231

32/16−Channel Digital Receiver VIM Module

for Pentek VIM Baseboards

Manual Part No: 800.62300 Rev: C.1 − October 23, 2006

Pentek, Inc.

One Park Way

Upper Saddle River, NJ 07458

(201) 818−5900

http://www.pentek.com

Page 2

Page 2 Pentek Model 6230/6231 Operating Manual

Manual Revision History

Date Manual Rev Comments

6/8/01 Preliminary Initial product release.

1/31/02 A Added instructions for programming ADM1024, Sect 3.6. Added channel number coding

for Channel Tag in output format, Section 4.2, per KB Case 972. Added detailed installation instructions for Option 102, Sect 2.3. Removed Virtex−E FPGA Appendix—data is in FPGA

Design Kit, Part #49530−250. Added Input Offset Error Specifications, per KB case 1016. 6/14/02 A.1 Added notes on Real mode output from GC4016s in DDR modes, Sect 4.2, per KBcase 1073. 9/26/02 A.2 Added note on Reset hold time, Sect 3.7, per KBcase 961.

12/16/02 A.3 Added board weight, Sect 1.11, per KBcase 1137. Corrected installation instructions, Sect 2.3,

per KBcase 1138. Corrected FPGA mating connector ERNI part #, Sect 2.4.5, per KBcase 1129. 2/24/03 A.4 Corrected Sync/Gate & FPGA connector part numbers, Sect 2.4.3 and 2.4.5, per KBcase 1155.

3/4/03 A.5 Corrected DDR Bypass mode descriptions, Sect 4.2.1 and 4.2.2.

5/21/03 B Added Option 105 information.

6/6/03 B.1 Corrected Configuration Data Register to Write Only, Sect 3.4.

7/15/03 B.2 Added VME baseboards, Sect 1.1, added Support Software Sect 1.11, corrected Model 4205

base addresses, Sect 3.2.

10/15/03 B.3 Corrected footnotes for register power−up states, Tables 3−5, 3−19, 3−20, 3−23, 3−26, 3−27.

Added comment that input channel data goes only to associated BIFO for Bypass modes,

Sect 4.2.1 & 4.2.2, per KBcase 1153. Moved Timing & Sync to new Chapter 5. 6/25/04 B.4 Added note about more samples than trigger length , Sect 3.11, per KBcase 1161. 1/14/05 C Updated Power Specifications, Sect 1.12.

10/23/06 C.1 Added Environmental Specifications, Sect 1.12. Updated ERNI conector part numbers, Sect

2.4.3 & 2.4.5, per KBCase 1308.

Warranty

Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are free from defects in mate− rials and workmanship for a period of one year from the date of delivery when used under normal operating conditions and within the service conditions for which they were furnished.

The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any product that in Pentek’s sole opinion proves to be defective within the scope of the warranty. Pentek must be notified in writing of the defect or nonconformity within the warranty period and the affected product returned to Pentek within thirty days after discovery of such defect or nonconformity.

Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Pentek for warranty service. Pentek shall pay for the return of products to buyer except for products returned from another country.

Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized modification, misuse, neglect, inadequate maintenance, or accident, or for any product that has been repaired or altered by anyone other than Pentek or its authorized representatives.

The warranty described above is buyer’s sole and exclusive remedy and no other warranty, whether written or oral, is expressed or implied. Pentek specifically disclaims fitness for a particular purpose. Under no circumstances shall Pentek be liable for any direct, indi− rect, special, incidental, or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or any other legal theory.

Copyrights

With the exception of those items listed below, the contents of this publication are copyright © 2006, Pentek, Inc. All Rights Reserved. Contents of this publication may not be reproduced in any form without written permission.

Appendix B, AD6644 Datasheet, is the copyrighted property of Analog Devices, Inc., Norwood MA Appendix C, Graychip GC4016 Datasheet, is the copyrighted property of Graychip, Inc., Palo Alto, CA Appendix D, ADM1024 Datasheet, is the copyrighted property of Analog Devices, Inc., Norwood MA.

Trademarks

Pentek, GateFlow, ReadyFlow, and VIM are registered trademarks or trademarks of Pentek, Inc. VxWorks is a registered trademark of Wind River Systems, Inc. Xilinx and Virtex are registered trademarks or trademarks of Xilinx, Inc.

Printed in the United States of America.

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Pentek Model 6230/6231 Operating Manual Page 3

Table of Contents

Page

Chapter 1: Introduction

1.1 General Description..............................................................................................................................9

1.2 Features ..................................................................................................................................................9

1.3 Analog/Digital Conversion ..............................................................................................................10

1.4 Digital Receivers .................................................................................................................................10

1.5 Digital Interfaces.................................................................................................................................10

1.6 Timing and Synchronization.............................................................................................................11

1.7 Interrupts .............................................................................................................................................11

1.8 VIM Interface.......................................................................................................................................11

1.9 Block Diagrams ...................................................................................................................................12

Figure 1−1: Model 6230 Block Diagram.........................................................................................12

Figure 1−2: Model 6231 Block Diagram.........................................................................................12

Figure 1−3: Model 6230 Block Diagram, with Option 105 .........................................................13

Figure 1−4: Model 6231 Block Diagram, with Option 105 .........................................................13

1.9.1 Channels .............................................................................................................................14

1.10 FPGA Configuration ..........................................................................................................................15

1.10.1 Model 6230 .........................................................................................................................16

Figure 1−5: Model 6230 FPGA Interconnectivity .......................................................16

1.10.2 Model 6231 .........................................................................................................................17

Figure 1−6: Model 6231 FPGA Interconnectivity .......................................................17

1.11 Board Support Software ....................................................................................................................17

1.12 Specifications.......................................................................................................................................18

Chapter 2: Installation and Connections

2.1 Inspection.............................................................................................................................................21

2.2 Jumper Block Settings ........................................................................................................................21

2.2.1 Analog Input Filter Bypass Jumpers (without Option 105) .......................................21

Table 2−1: Analog Input Filter Bypass Jumpers.........................................................21

2.2.2 FPGA Configuration Data Source Jumper ....................................................................22

Table 2−2: FPGA Configuration Data Source Jumper ..............................................22

2.2.3 External TTL Inputs Select Jumpers ..............................................................................22

Table 2−3: External TTL Inputs Select Jumpers .........................................................22

Figure 2−1: Model 6230 PCB Assembly, Component Side ........................................................23

Figure 2−2: Model 6231 PCB Assembly, Component Side ........................................................24

Figure 2−3: Model 6231 Option 102 PCB Assembly, Component Side ...................................24

Rev.: B.4

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Page 4 Pentek Model 6230/6231 Operating Manual

Table of Contents

Page

Chapter 2: Installation and Connections (continued)

2.3 Installing the Model 6230/6231 on a VIM Baseboard................................................................... 25

Figure 2−4: Typical VIM Baseboard − Connectors & Mounting Holes .................................26

2.3.1 Installing Model 6230, or Model 6231 without Option 102 ........................................27

Figure 2−5: VIM−4 Panel Mounting & Shipping Screws ........................................27

Figure 2−6: VIM Module Nylon Spacer....................................................................... 28

Figure 2−7: VIM Baseboard Blank Panel Screws....................................................... 28

2.3.2 Installing Model 6231 with Option 102 .........................................................................30

Figure 2−8: Model 6231 with Option 102 Shipping Assembly................................ 30

Figure 2−9: VIM Module Nylon Spacer....................................................................... 31

Figure 2−10: VIM Baseboard Blank Panel Screws..................................................... 31

Figure 2−11: Option 102 Front Panel Assembly.........................................................32

Figure 2−12: VIM Baseboard with Option 102 Front Panel Assembly.................. 33

Figure 2−13: Option 102 Stacking Connectors on VIM Module .............................33

Figure 2−14: Option 102 PCB Mounted on VIM Module.........................................34

2.4 Front Panel Connections ................................................................................................................... 35

2.4.1 Analog Input Connectors ................................................................................................ 35

2.4.2 Sample Clock Input Connector ...................................................................................... 35

Figure 2−15: Models 6230 and 6231 Front Panels ........................................................................ 36

2.4.3 Sync/Gate Connector ......................................................................................................37

Table 2−4: SYNC/GATE Connector Pins..................................................................... 37

2.4.4 Sync/Gate Header ...........................................................................................................37

Table 2−5: SYNC/GATE/TRG Header Pins ................................................................ 37

2.4.5 FPGA Connector ..............................................................................................................38

Table 2−6: FPGA Connector Pins..................................................................................38

2.5 Front Panel LEDs................................................................................................................................39

2.5.1 Clock (CLK) LED .............................................................................................................. 39

2.5.2 Over Temperature (TEMP) LED ....................................................................................39

2.5.3 Master (MAS) LED ........................................................................................................... 39

2.5.4 Terminate (TRM) LED ..................................................................................................... 39

2.5.5 Overload (OVLD CHn) LEDs ......................................................................................... 39

Rev.: B.4

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Pentek Model 6230/6231 Operating Manual Page 5

Table of Contents

Page

Chapter 3: Memory Maps and Register Descriptions

3.1 Overview..............................................................................................................................................41

3.2 Model 6230/6231 Memory Map.......................................................................................................41

Table 3−1: VIM Base Addresses for Models 4290 to 4295 VIM Baseboards ..........................41

Table 3−2: VIM Base Addresses for Model 4205 VIM Baseboards .........................................41

Table 3−3: Model 6230/6231 Memory Map ...................................................................................42

3.3 Virtex Config Register........................................................................................................................43

Table 3−4: Virtex Config Register ..................................................................................................43

3.3.1 WRITE ................................................................................................................................43

3.3.2 BUSY ...................................................................................................................................43

3.3.3 INIT .....................................................................................................................................43

3.3.4 DONE .................................................................................................................................44

3.3.5 PRGM .................................................................................................................................44

3.3.6 LD SRC ...............................................................................................................................44

3.4 Virtex Config Data Register ..............................................................................................................44

Table 3−5: Virtex Config Data Register.........................................................................................44

3.5 Wait States Register............................................................................................................................45

Table 3−6: Wait States Register.......................................................................................................45

3.6 Hardware Monitor Port Register......................................................................................................46

Table 3−7: Hardware Monitor Port Register ................................................................................46

Table 3−8: ADM1024 Registers.......................................................................................................47

3.7 Master Control Register.....................................................................................................................48

Table 3−9: Master Control Register................................................................................................48

3.7.1 RESET .................................................................................................................................48

3.7.2 SYNC SRC ..........................................................................................................................48

3.7.3 SYNC POL .........................................................................................................................49

3.7.4 EXT SYNC EN ...................................................................................................................49

3.7.5 MCLK DIVn .......................................................................................................................49

3.7.6 CLK SRC SEL ....................................................................................................................49

3.7.7 OSC DSBL ..........................................................................................................................49

3.7.8 EXT CLK ............................................................................................................................50

3.7.9 TERM ..................................................................................................................................50

3.7.10 MASTR ...............................................................................................................................50

3.8 Bypass Rate Divide Register .............................................................................................................51

Table 3−10: Bypass Rate Divide Register .....................................................................................51

3.9 Channel Enable Register....................................................................................................................52

Table 3−11: Channel Enable Register............................................................................................52

Table 3−12: Register Bit Channel Assignments...........................................................................52

3.10 Gate Control Register.........................................................................................................................53

Table 3−13: Gate Control Register..................................................................................................53

3.10.1 INT EDGE x .......................................................................................................................53

3.10.2 GATE POL .........................................................................................................................54

3.10.3 GATE SELn ........................................................................................................................54

Rev.: B.4

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Page 6 Pentek Model 6230/6231 Operating Manual

Table of Contents

Page

Chapter 3: Memory Maps and Register Descriptions

3.10.4 GATE DISBL ..................................................................................................................... 54

3.10.5 GATE SRC .........................................................................................................................54

3.10.6 TRIG CLEAR .....................................................................................................................54

3.10.7 HOLD MODE ................................................................................................................... 55

3.10.8 GATE/TRIG ......................................................................................................................55

3.10.9 EXT GATE .........................................................................................................................55

3.11 Trigger Length Register.....................................................................................................................56

Table 3−14: Trigger Length Register .............................................................................................56

3.12 Channel Control Register.................................................................................................................. 57

Table 3−15: Channel Control Register ..........................................................................................57

3.12.1 RESET ................................................................................................................................. 57

3.12.2 DIV RST EN ......................................................................................................................57

3.12.3 FMTR EN ........................................................................................................................... 57

3.12.4 DAT MODEn ....................................................................................................................58

3.13 Sync/Gate Generator Register ......................................................................................................... 59

Table 3−16: Sync/Gate Generator Register................................................................................... 59

3.13.1 FIFO GATE ........................................................................................................................59

3.13.2 SYNC ..................................................................................................................................59

3.14 Interrupt Mask Register .................................................................................................................... 60

Table 3−17: Interrupt Mask Register.............................................................................................60

Table 3−18: Interrupt Register Bits ................................................................................................ 61

3.15 Interrupt Flag Register ...................................................................................................................... 62

Table 3−19: Interrupt Flag Register ............................................................................................... 62

3.16 Interrupt Status Register ...................................................................................................................63

Table 3−20: Interrupt Status Register............................................................................................ 63

3.17 Semaphore Register ...........................................................................................................................64

Table 3−21: Semaphore Register.................................................................................................... 64

3.18 I/O Direction 2 Register (Model 6231 only)................................................................................... 65

Table 3−22: I/O Direction 2 Register (Model 6231 Option 102 only) ...................................... 65

3.19 I/O Data 2 Register (Model 6231 only)........................................................................................... 66

Table 3−23: I/O Data 2 Register (Model 6231 Option 102 only) ............................................... 66

3.20 I/O Direction Register.......................................................................................................................67

Table 3−24: I/O Direction Register ................................................................................................ 67

3.21 I/O Enable Register ...........................................................................................................................68

Table 3−25: I/O Enable Register..................................................................................................... 68

3.21.1 I/O EN1 .............................................................................................................................68

3.21.2 I/O EN2 .............................................................................................................................68

3.22 I/O Data Register...............................................................................................................................69

Table 3−26: I/O Data Register......................................................................................................... 69

3.23 Graychip 0 & 1 Registers...................................................................................................................70

Table 3−27: Graychip 0 & 1 Registers............................................................................................70

Table 3−28: Processor/Graychip Register Sets............................................................................. 70

Rev.: B.4

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Pentek Model 6230/6231 Operating Manual Page 7

Table of Contents

Page

Chapter 4: Data Formatting and Routing

4.1 Overview..............................................................................................................................................71

4.2 Data Routing and Formats ................................................................................................................71

4.2.1 DDR Bypass Mode, A/D Data, Unpacked (001) ..........................................................72

Table 4−1: Output Data Format − DDR Bypass Mode, Unpacked.........................72

4.2.2 DDR Bypass Mode, A/D Data, Time Packed (010) .....................................................72

Table 4−2: Output Data Format − DDR Bypass Mode, Time Packed ....................72

4.2.3 DDR Bypass Mode, A/D Data, Channel Packed (011) ...............................................73

Table 4−3: Output Data Format − DDR Bypass Mode, Channel Packed ..............73

4.2.4 DDR Mode, 16−Bit, Unpacked I/Q, Tagged (100) .......................................................74

Table 4−4: Output Data Format − DDR Mode, 16−bit, Unpacked I/Q, Tagged ...74

4.2.5 DDR Mode, 24−Bit, Unpacked I/Q, Tagged (101) .......................................................75

Table 4−5: Output Data Format − DDR Mode, 24−bit, Unpacked I/Q, Tagged ...75

4.2.6 DDR Mode, 16−Bit, Packed I/Q (110) ...........................................................................76

Table 4−6: Output Data Format − DDR Mode, 16−bit, Packed I/Q ........................76

4.2.7 DDR Mode, 24−Bit, Packed I/Q (111) ...........................................................................77

Table 4−7: Output Data Format − DDR Mode, 16−bit, Packed I/Q ........................77

Chapter 5: Timing and Synchronization

5.1 Overview..............................................................................................................................................79

Figure 5−1: Model 6230 Gate/Sync/Clock Logic ..........................................................................79

Figure 5−2: Model 6231 Gate/Sync/Clock Logic ..........................................................................80

5.2 Sync.......................................................................................................................................................80

5.3 Clock.....................................................................................................................................................80

5.4 Gates .....................................................................................................................................................81

Rev.: B.4

Page 8

Page 8 Pentek Model 6230/6231 Operating Manual

Table of Contents

Page

Appendix A: Configuration EEPROM Format

A.1 Introduction .....................................................................................................................................A−1

A.2 EEPROM Format Example ............................................................................................................A−1

Table A−1: VIM ID EEPROM Register......................................................................................A−1

Table A−2: EEPROM Example (Model 6230 shown)...............................................................A−2

Appendix B: Analog Devices AD6644 A/D Converter

B.1 Introduction ..................................................................................................................................... B−1

Appendix C: Graychip GC4016 Digital Receiver

C.1 Introduction .....................................................................................................................................C−1

Appendix D: Analog Devices ADM1024 System Hardware Monitor

D.1 Introduction .....................................................................................................................................D−1

Rev.: B.4

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Pentek Model 6230/6231 Operating Manual Page 9

Chapter 1: Introduction

1.1 General Description

The Models 6230 and 6231 are general purpose, narrowband digital receiver VIM® (Velocity Interface Mezzanine) modules that perform frequency down conversion, low−pass filtering, and decimation of the digitized input signal. The Model 6230 is a 32−channel VIM−4 module that features four 14−bit, 65−MHz A/D converters, and can be configured with up to 32 channels of narrowband receivers. The Model 6231 is a 16−channel VIM−2 module, with two 14−bit, 65−MHz A/D converters, and up to 16 channels of narrowband receivers.

The Models 6230 and 6231 attach directly to VIM−compatible baseboards, including the Pentek Models 4205, and 4290 through 4295 Quad DSP (Digital Signal Processing) boards.

1.2 Features

 Four 65−MHz, 14−bit A/D converters (Model 6230)

Two 65−MHz, 14−bit A/D converters (Model 6231)

 32 channels of narrowband digital receivers (Model 6230)

16 channels of narrowband digital receivers (Model 6231)

 All receivers can select any of the A/D inputs

 DC to 90−MHz input range (standard models)

300−kHz to 150−MHz input range (Option 105)

 DC to 32−MHz center frequency tuning with 0.02−Hz resolution

 3.6−kHz to 1.6−MHz output bandwidths

 Front panel clock and sync bus can synchronize multiple boards

 Direct connection to each VIM processor with no shared bus bottlenecks

 Compliant with VIM module specification

In this manual, all specifications and user instructions are presented in reference to

Note

the Model 6230. Where a difference exists, the corresponding information for the Model 6231 is included in brackets “[...]”.

Rev.: B.4

Page 10

Page 10 Pentek Model 6230/6231 Operating Manual

1.3 Analog/Digital Conversion

The Model 6230 [Model 6231] accepts four [two] analog RF inputs on front panel SMA connectors in the range of DC to 90 MHz to support direct IF undersampling. Each input signal is buffered by an Analog Devices OPA642 amplifier. Low−pass anti− aliasing filters for each input signal may be individually enabled or bypassed by on− board jumpers. With Option 105, the amplifier, filters, and bypass jumpers are replaced by an RF transformer, and the RF input range is 300 kHz to 150 MHz.

An Analog Devices AD6644 14−bit, 65−MHz A/D converter then digitizes each of the analog inputs. The A/D converter clock can be driven from an internal 64−MHz crys− tal oscillator, from an external sample clock supplied through a front panel SMA con− nector, or from the front panel sync bus.

1.4 Digital Receivers

The Model 6230 [Model 6231] includes eight [four] Graychip GC4016 quad narrowband digital receiver (DDR) chips. Each GC4016 DDR accepts four [two] 14−bit parallel inputs from the AD6644 A/D converters. A crossbar switch inside each GC4016 allows each of the 32 [16] receiver channels on the board to independently select any of the A/D inputs for flexible switching.

The maximum input sampling rate, f includes four independently tunable receiver channels capable of tuning throughout the DC to f

/2 range, with output bandwidths ranging from 0.8 · fs/N (for the standard

80% FIR filter), where the decimation factor, N, ranges from 32 to 16,384. For an input sampling clock of 64 MHz, this output bandwidth range becomes approximately

3.1 kHz to 1.6 MHz. Each processor on the VIM baseboard can control all programma− ble registers on its two associated GC4016s.

1.5 Digital Interfaces

The Model 6230 [Model 6231] contains two [one] Xilinx® Virtex®−E XCV300 FPGAs (field programmable gate arrays). (These are optionally replaceable by other Virtex devices in the series up to XCV600.) The FPGAs are factory programmed to implement the standard data formatting, clocking, and control functions specified in this docu− ment. Each GC4016 DDR delivers real or complex serial data streams into one FPGA, where data is formatted and multiplexed for delivery across the VIM interface into the 32−bit parallel Bi−FIFOs (BIFOs) on the VIM baseboard. The AD6644 digital outputs are also connected directly to each FPGA so that wideband A/D data can be delivered directly to the DSP board, bypassing the digital receivers.

The user can re−program the Virtex−E FPGAs from the VIM baseboard processors. This allows the user to implement his own algorithms for special timing requirements and for pre−processing of AD6644 or GC4016 output data before sending it to the pro− cessor BIFOs. Refer to Section 1.10, FPGA Configuration, for additional information about the gate array configurations.

, for the GC4016 is 80 MHz. Each receiver

Rev.: B.4

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Pentek Model 6230/6231 Operating Manual Page 11

1.6 Timing and Synchronization

A VIM baseboard processor can access all board control and status registers to control synchronization, gating, triggering, and clocking functions. All VIM baseboard pro− cessors can generate sync, gate, and trigger signals for distribution on the front panel LVDS (low−voltage differential signal) sync bus. This sync bus includes sample clock, gate, and sync signals. It allows one Model 6230/6231 to act as a bus Master, driving these signals out to a front panel flat cable using LVDS differential signaling. Addi− tional sync lines on the bus allow synchronization of the local oscillator phase, fre− quency switching, decimating filter phase, and BIFO data collection on multiple modules. Up to seven slave 6230/6231 modules can be driven from the bus Master, supporting synchronous sampling and sync functions across all connected boards. If the Model 6230/6231 is a bus Master, any of the VIM baseboard processors can create a sync individually (one at a time) by toggling a bit in a register.

In addition to the LVDS sync bus, the Model 6230/6231 can receive two external input signals: one TTL sync and one TTL gate or trigger. Refer to Chapter 5, Gate/Sync Description, for additional information about the use and programming of gate, clock, and sync signals.

1.7 Interrupts

The Model 6230/6231 has several maskable interrupt sources. Interrupts may be gen− erated to any of the VIM baseboard processors by the A/D converter overload outputs, transitions on the gate or sync signals, clock loss, or a programmable over−temperature or a faulty power supply voltage.

The board’s Voltage/Temperature Monitor, an ADM1024, provides constant monitor− ing of critical voltages and temperatures on the Model 6230/6231 PCB. This device is programmable for voltage and temperature limits. If the voltage/temperature fall out− side of the set limits, an interrupt can be generated.

1.8 VIM Interface

The FPGA outputs are connected directly through the VIM mezzanine interface to the 32−bit synchronous BIFOs on the VIM baseboard, where they are buffered for efficient block transfers to the processors. Each processor on the VIM baseboard can control all programmable registers on the associated GC4016s, as well as control and initiate sync bus functions.

Rev.: B.4

Page 12

Page 12 Pentek Model 6230/6231 Operating Manual

1.9 Block Diagrams

The following are block diagrams of the Models 6230 and 6231 digital receivers.

Sample Clock In

CLOCK

GENERATOR/

DIVIDER

Clock

& Sync

Bus

TTL

Sync &

Gate

SYNCHRONIZATION

INTERRUPTS

AND CONTROL

Front Panel I/O

Model 6230 VIM Processor Board

XTL

OSC.

A/D Clock

GC4016

NARROW−

BAND

DIG. RCVR

Control

4−CH

RF In

AMPLIFIER

LOW PASS

FILTER

AD6644

14−BIT A/D

14 14 14 14

GC4016

NARROW−

BAND

4−CH

DIG. RCVR

GC4016

NARROW−

BAND

4−CH

DIG. RCVR

AMPLIFIER

LOW PASS

FILTER

AD6644

14−BIT A/D

GC4016

NARROW−

BAND

4−CH

DIG. RCVR

RF In

GC4016

NARROW−

BAND

4−CH

DIG. RCVR

I&QI&Q I&QI&QI&Q I&QI&Q I&Q

Virtex−E FPGA Virtex−E FPGA

I & Q I & Q

PROC

BI−

FIFO

32 32

PROC

I & Q I & Q

BI−

FIFO

ControlControl Control

Figure 1−1: Model 6230 Block Diagram

AMPLIFIER

LOW PASS

14−BIT A/D

PROC

RF In

FILTER

AD6644

GC4016

NARROW−

BAND

4−CH

DIG. RCVR

3232 32

BI−

FIFO

GC4016

NARROW−

BAND

4−CH

DIG. RCVR

PROC

AMPLIFIER

LOW PASS

FILTER

AD6644

14−BIT A/D

NARROW− BAND DIG. RCVR

RF In

GC4016

BI−

FIFO

4−CH

Front

Panel

I/O

Rev.: B.4

Sample Clock In

CLOCK

GENERATOR/

DIVIDER

Clock

& Sync

Bus

TTL

Sync &

Gate

SYNCHRONIZATION

INTERRUPTS

AND CONTROL

Model 6231

VIM Processor Board

Figure 1−2: Model 6231 Block Diagram

XTL

OSC.

A/D Clock

GC4016

NARROW−

BAND

4−CH

DIG. RCVR

Control

PROC

A (or C)

RF In

AMPLIFIER

LOW PA SS

FILTER

AD6644

14−BIT A/D

14 14

GC4016

NARROW−

BAND

DIG. RCVR

4−CH

GC4016

NARROW− BAND DIG. RCVR

I&QI&Q I&QI&Q

Virtex−E FPGA

Control

I & Q

BI−

FIFO

4−CH

PROC

B (or D)

AMPLIFIER

LOW PA SS

FILTER

AD6644

14−BIT A/D

GC4016

NARROW− BAND DIG. RCVR

BI−

FIFO

RF In

4−CH

I & Q

Front Panel I/O

(optional)

Page 13

Pentek Model 6230/6231 Operating Manual Page 13

1.9 Block Diagrams (continued)

The following are block diagrams of the Models 6230 and 6231 with Option 105.

Sample Clock In

CLOCK

GENERATOR/

DIVIDER

Clock

& Sync

Bus

TTL

Sync &

Gate

SYNCHRONIZATION

INTERRUPTS

AND CONTROL

Front Panel I/O

Model 6230 VIM Processor Board

XTL

OSC.

A/D Clock

BAND DIG. RC VR

GC4016

NARROW−

4−CH

RF In

TRANSFORMER

AD6644

14−BIT A/D

GC4016

NARROW−

BAND

4−CH

DIG. RC VR

GC4016

NARROW−

BAND

4−CH

DIG. RC VR

RF In RF In RF In

TRANSFORMER

AD6644

14−BIT A/D

14 14 14

GC4016

NARROW−

BAND

4−CH

DIG. RC VR

GC4016 NARROW− BAND DIG. RC VR

TRANSFORMER

AD6644

14−BIT A/D

GC4016

NARROW−

BAND

4−CH

DIG. RC VR

4−CH

GC4016

NARROW−

BAND

DIG. RC VR

I&QI&Q I&QI&QI&Q I&QI&Q I&Q

Control

PROC

32 32

Virtex−E FPGA Virtex−E FPGA

I & Q I & Q

FIFO

BI−

PROC

I & Q I & Q

BI−

FIFO

ControlControl Control

PROC

3232 32

BI−

FIFO

Figure 1−3: Model 6230 Block Diagram, with Option 105

TRANSFORMER

AD6644

14−BIT A/D

GC4016

NARROW−

BAND

4−CH

DIG. RC VR

PROC

FIFO

BI−

4−CH

Front

Panel

I/O

Clock

& Sync

Bus

TTL

Sync &

Gate

Sample

Clock In

CLOCK

GENERATOR/

DIVIDER

SYNCHRONIZATION

INTERRUPTS

AND CONTROL

XTL

OSC.

A/D Clock

GC4016

NARROW−

BAND

4−CH

DIG. RC VR

RF In

TRANSFORMER

AD6644

14−BIT A/D

GC4016

NARROW−

BAND

4−CH

DIG. RC VR

GC4016

NARROW−

BAND

4−CH

DIG. RC VR

RF In

TRANSFORMER

AD6644

14−BIT A/D

GC4016

NARROW−

BAND

4−CH

DIG. RC VR

I&QI&Q I&QI&Q

Model 6231

VIM Processor Board

Control

PROC

A (or C)

Virtex−E FPGA

Control

I & Q

BI−

FIFO

PROC

B (or D)

I & Q

BI−

FIFO

Front Panel I/O

(optional)

Figure 1−4: Model 6231 Block Diagram, with Option 105

Rev.: B.4

Page 14

Page 14 Pentek Model 6230/6231 Operating Manual

1.9.1 Channels

The following defines the different uses of the term ‘Channel’ in this manual (refer also to the block diagrams on the prior two pages).

 Input Channels — There are four input channels on the Model 6230

[two input channels on the Model 6231], one for each analog RF input and A/D converter. These are identified as CH1, CH2, CH3, and CH4 for the 6230 [CH1 and CH2 for the 6231]. Each input channel may be independently selected by any of the receiver channels (below).

 Receiver Channels — Each VIM baseboard processor has access to eight

receiver channels, four channels in each of the two Graychip GC4016 DDRs associated with that processor. These are identified as DSP CH1 through DSP CH8, for each processor. Any one of the A/D input channels (above) may be connected independently to each receiver channel. Each receiver channel may be individually selected for output to the VIM Bi−FIFO by the associated processor.

 Processor Channels — There are four processor channels on the Model

6230 [two processor channels on the 6231], one for each processor on the VIM baseboard. These are identified as Processors A, B, C, and D for the 6230 [Processors A and B, or C and D, for the 6231, depending on the mezzanine position that the module is installed into on the VIM baseboard]. Each processor channel is associated with (and provides control for) two GC4106s on the module, and one Bi−FIFO on the VIM baseboard. Two processor channels are associated with each FPGA (Processor A controls FPGA1, Processor C controls FPGA2).

Rev.: B.4

Page 15

Pentek Model 6230/6231 Operating Manual Page 15

1.10 FPGA Configuration

The standard FPGAs on the Model 6230/6231 are the Xilinx Virtex−E XCV300E; the Virtex−E XCV600E models are available as Option 600. The baseline functionality con− sumes about 60% of the XCV300E or 30% of the XCV600E.

All data from the AD6644 A/D converters and the Graychip GC4016 DDRs pass through these FPGAs before being fed to the VIM baseboard BIFOs. The Model 6230/ 6231 is shipped with a default set of logic functions for the FPGAs, on JTAG−program− mable serial EEPROMs. Each FPGA has it’s own EEPROM to facilitate two different programmings. At power−up, this set of default functions is loaded into the FPGAs.

The FPGAs can be configured in several different ways:

• The default method is configuration loading from separate 4−Mbit configuration EEPROMs. This is the power−up mode of the board. Configuration reload may also be forced by Processors A and C (see Section 3.3).

• The second method, to facilitate development and debugging, is by serial download to the FPGAs using a Xilinx download cable. This method will replace the factory− programmed configuration that loads at power up from the EEPROMs. In this mode, the FPGAs are chained to accept one download stream, so two different or identical programs can be strung together in the download bitstream. This method is volatile and will exist only until the power is turned off.

• The third method is byte−wide upload from Processors A and C. Processor A configures the first FPGA, and Processor C the second, by writing the configuration data to the FPGA Configuration Data Register (see Section 3.4). For a Virtex XCV600E FPGA, approximately 512K bytes on the baseboard are required to hold the configuration for each FPGA. This method is volatile and will exist only until the power is turned off.

• The last method is to use the serial EEPROM configuration method, then overwrite the default configuration by reprogramming each EEPROM from the JTAG interface. This overwrites the default configuration by reprogramming the EEPROMs. After turning power off, the FPGAs will power up with this new configuration instead of the default configuration.

NOTE:

This method will permanently overwrite the default configuration supplied by Pentek. The default configuration is supplied with the available FPGA Design Kit so that it can be restored if necessary.

Pentek has available GateFlow™ FPGA Design Kits that provide resources for the user to modify the programmable logic functions for the Virtex−E FPGA. This allows the user to implement his own algorithms for special timing requirements and for pre− processing of AD6644 or GC4016 output data. Pentek offers this capability as a sepa− rate development package, Model 4953 − Option 230 for the 6230, or Model 4953 − Option 231 for the Model 6231. Contact Pentek at (201) 818−5900 for details about this package.

Rev.: B.4

Page 16

Page 16 Pentek Model 6230/6231 Operating Manual

1.10 FPGA Configuration (continued)

1.10.1 Model 6230

Some spare pins on the Model 6230 FPGAs are cross−connected to facilitate user programming or future functionality. The spare pins are broken up into the following groups:

• The first group of 38 spares is available on either FPGA model. Twelve pins are connected to a serial port on Processors A and C through a quick switch, but are disabled in the default configuration (see Note below). This optional connection allows a path for the two serial ports to the front panel connector if desired. These spare pins split into two groups of 19, and are cross−connected so that identical programming and I/O pin numbers in both FPGAs is possible.

• The second group of 44 spares exists only in the XCV600E model. They are divided into two groups of 22 pins and cross−connected.

• The third group of 16 pins and two quickswitch enables from each FPGA go to the front panel FPGA connector (see Section 2.4.5). These are connected with either FPGA model (XCV300E or XCV600E), and can be used as either inputs or outputs. The quickswitches and 25−ohm series resistors provide some over−voltage and short protection to the FPGA I/O pins. See Section 3.22 for description of this I/O register.

When the Model 6230 is attached to a Pentek VIM baseboard, the FPGAs provide serial port connectivity as shown in the following illustration.

Virtex−E FPGA 1 Virtex−E FPGA 2

Control

Quick

Switch

Model 6230

VIM Baseboard Serial Ports

Control

Quick Switch

A0 A1 B0 B1 C0 C1 D0 D1

The control signals needed to enable connection of serial ports A1 and C1 to the FPGAs are disabled in the default Model 6230 FPGA configuration. If

Note

needed, these connections will have to be optionally programmed into the FPGA logic.

Rev.: B.4

Figure 1−5: Model 6230 FPGA Interconnectivity

Page 17

Pentek Model 6230/6231 Operating Manual Page 17

1.10 FPGA Configuration (continued)

1.10.2 Model 6231

All spare pins on the Model 6231 FPGA are brought to the front panel FPGA connector (see Section 2.4.5). These pins are connected with either FPGA model (XCV300E or XCV600E), and can be used as either inputs or outputs. See Section 3.22 for description of the associated I/O register.

When the Model 6231 is attached to a Pentek VIM baseboard, the FPGA provides serial port connectivity as shown in the following illustration.

Virtex−E FPGA

Model 6231

VIM Baseboard Serial Ports

(or C0)A1(or C1)B0(or D0)B1(or D1)

Figure 1−6: Model 6231 FPGA Interconnectivity

1.11 Board Support Software

Pentek’s Model 4999 ReadyFlow® Board Support Libraries allow high−level program− ming to speed development tasks. Refer to the ReadyFlow software documentation for the Model 6230/6231 (Pentek part #801.62300) for further description of these capabili− ties.

Pentek’s Model 4996 VxWorks workstation platforms. In addition to the feature set provided by the driver, source code is included, allowing users to modify software functionality. Refer to the VxWorks Driver documentation for the Model 6230/6231 (Pentek part #803.62300) for further description of these capabilities.

Driver allows high−level programming for various

Rev.: B.4

Page 18

Page 18 Pentek Model 6230/6231 Operating Manual

1.12 Specifications

Front Panel Connectors

Analog Inputs: Four [two] female SMA connectors (one per A/D converter) Sample Clock Input: One female SMA connector Sync/Gate Bus: One 26−pin connector, with four gates, one sync, and one

clock input/output LVDS signals, plus one sync and one gate input TTL signals

TTL Sync/Gate: One 4−pin header, with one sync and one gate TTL inputs FPGA Input/Output:

Model 6230:

Model 6231, Option 102:

Analog Signal Inputs

Quantity: Four [two], via front panel SMA connectors Input Type: Single−ended, non−inverting Coupling: DC Input Impedance: 50 Full Scale Input: Standard: 2 V

Input Offset Error: ± 0.6% full scale range @ 25° C

One 50−pin connector, with 32 FPGA input/output pins,

20 mA maximum load per pin

One 50−pin connector, with 24 FPGA input/output pins,

20 mA maximum load per pin

Ω

(± 1.0 V)

p−p

Option 105: 1 V

(± 0.5 V)

p−p

± 1.6% full scale range over operating temperature range

Analog Input Conditioning

Analog Input Amplifiers

Quantity: Four [two] (enclosed in a shielded cover) Device: Analog Devices OPA642 Gain: One (unity), standard 3 dB Bandwidth: 90 MHz (based on gain of one)

Analog Input Filters

Quantity: Four [two] (enclosed in a shielded cover) Type: Fixed frequency low−pass, 7−pole, LC Passband: DC to 26 MHz (±3.0 dB ripple) Stopband Attenuation: >70 dB @ 60 MHz Bypass: May be bypassed by on−board jumper selection

Analog Input Conditioning

Analog Input Transformers

Quantity: Four [two] (enclosed in a shielded cover) Type: Mini−Circuits ADT4−5WT 3 dB Passband: 300 kHz to 500 MHz Input Return Loss: 8.72 dB min., 31.13 dB max. Bypass: None

(without Option 105)

(with Option 105)

Rev.: B.4

Page 19

Pentek Model 6230/6231 Operating Manual Page 19

1.12 Specifications (continued)

Analog/Digital Converters

Quantity: Four [two] (enclosed in a shielded cover) Device: Analog Devices AD6644 (see Appendix B) Sampling Rate: 15 MHz to 65 MHz Resolution: 14 bits Coupling: DC Clock Source: Onboard crystal oscillator, external clock, or LVDS clock

(software selectable)

External Clock Input

Voltage Range: 1 V Type: Square or Sine Wave Duty Cycle: 45% to 55% Frequency: 15 MHz to 65 MHz Impedance: 50

Sample Rate Control

Internal Clock: 64 MHz External Clock: 15 MHz to 65 MHz Sample Rate Divider: Divisible by 1, 2, or 4 (internal or external source)

(minimum), 5 V

P−P

Ω, AC coupled

(maximum)

P−P

Gates

Quantity: Four [two], one per VIM baseboard BIFO Polarity: Programmable Routing: Each VIM baseboard processor can create its own gate Gate Disable: Each gate can be disabled from its processor

(BIFO writes default to enable)

Digital Receivers

Quantity: Eight [four] quad receiver chips (32 [16] receiver channels) Device: Graychip GC4016 (see Appendix C) Decimation: 32 to 16,384 Data Source: All A/D outputs are connected to each GC4016 Clock Source: A/D clock Sync: Maskable inside each GC4016 chip

(All receiver channels directed to the same VIM base− board BIFO must be synced at the GC4016 output)

Output: Serial data

(Serial output rate must be same as input clock rate)

Bypass Mode: Data from the A/D converters can be written directly into the

VIM baseboard BIFOs (bypassing the GC4016s), at a sam− ple rate equal to the A/D clock decimated by 1 or any even value between 2 and 4096

Rev.: B.4

Page 20

Page 20 Pentek Model 6230/6231 Operating Manual

1.12 Specifications (continued)

Field−Programmable Gate Arrays

Quantity: Two [one], one for Processors A & B, one for Processors C & D Device: Xilinx Virtex−E XCV300E (standard);

Option 600 – Xilinx Virtex−E XCV600E

Programming: Factory programmed by Pentek

(contact Pentek for user programming information)

Estimated Power Dissipation:

+2.5V Digital Supply (DC/DC):

Graychip GC4016s:

+5V Analog Supply

(LC Filtered +5V):

AD6644 A/D Converters: OPA642 Amplifiers: 25 mA * 4 = 0.10 A 25 mA * 2 = 0.05 A AD8138 Amplifiers: 24 mA * 4 = 0.10 A 24 mA * 2 = 0.05 A

−5V Analog Supply

(Linear from −12V):

OPA642 Amplifiers: AD8138 Amplifiers: 24 mA * 4 = 96 mA 24 mA * 2 = 48 mA

+1.8V Digital Supply

(DC/DC from 5V):

XCV300E FPGAs w/base circuitry: 1.3 W 0.65 W XCV300E FPGAs w/heavy use: 5.6 W 2.8 W XCV600E FPGAs w/heavy use: 11.8 W 5.91 W

+3.3V Digital Supply

(DC/DC from 12V):

XCV300E FPGAs w/base circuitry: 1.2 W 0.6 W XCV300E FPGAs w/heavy use: 1.3 W 0.65 W XCV600E FPGAs w/heavy use: 1.9 W 0.95 W

Total Board Power:

XCV300E FPGAs w/base circuitry: 15 W 7.55 W XCV300E FPGAs w/heavy use: 19.4 W 9.75 W XCV600E FPGAs w/heavy use: 25.2 W 13.15 W (Notes: Estimated at 80MHz — power consumption is less at 65 MHz;

FPGA power consumption will vary based on usage)

Model 6230 Model 6231

(at 80MHz and minimum decimation)

8 * 187mA = 1.5A 4 * 187mA = 0.75A

1.5A * 2.5V = 3.75W

3.75W/.93 = 4.0 W 1.875W/.93 = 2.0 W

260 mA * 4 = 1.04 A 260 mA * 2 = 0.52 A

1.24 A * 5V = 6.2 W 0.62 A * 5V = 3.1 W

25 mA * 4 = 100 mA 25 mA * 2 = 50 mA

196 mA * 12V = 2.3 W 98 mA * 12V = 1.2 W

0.75A * 2.5V = 1.875W

_______ _______

Physical

Dimensions: 6230 VIM−4 Module 6231 VIM−2 Module

Height: 228.6 mm (9.00 in) 114.3 mm (4.50 in) Depth: 82.5 mm (3.25 in) 82.5 mm (3.25 in) Width: 20.3 mm (0.80 in) 20.3 mm (0.80 in)

Weight: 260.8 grams (9.2 oz) 138.9 grams (4.9 oz)

Environmental

Operating Temperature: 0° to 50°C Storage Temperature: −20° to 90°C Relative Humidity: 0 to 95% non−condensing

Rev.: C

Page 21

Pentek Model 6230/6231 Operating Manual Page 21

Chapter 2: Installation and Connections

2.1 Inspection

After unpacking, inspect the unit carefully for possible damage to connectors or com− ponents. If any damage is discovered, contact Pentek immediately at (201) 818−5900. Please save the shipping container and packing material in case reshipment is required.

2.2 Jumper Block Settings

The Model 6230 [Model 6231] PCB has ten [six] jumper blocks that the user can set. With Option 105, the PCB has only two jumper blocks. These jumpers are described in the following subsections. Assembly drawings of the Model 6230 and 6231 PCBs are provided in Figures 2−1 and 2−2, showing the locations of these jumpers. Note that most components are normally hidden under a heat sink/shield. To remove this shield, remove ten [five] Phillips screws that hold the heat shield, from the solder side of the board. Be sure to replace this shield after making any jumper changes.

2.2.1 Analog Input Filter Bypass Jumpers (without Option 105)

On boards without Option 105, jumper blocks JB1 to JB8 [JB1 to JB4] allow you to bypass the analog input filters (see Figures 1−1 and 1−2)—these jumpers are not present with Option 105. For each input channel, you must set two jumper blocks, one on either side of the input filter. Each jumper block has three pins (as illustration in Table 2−1, below). The arrangement of the pins on each jumper block is the same, however, the jumper blocks are oriented differently on the PCB. Note the location of pin 1 of each jumper block (Figures 2−1 and 2−2). For each jumper block, set the jumper on pins 1

− 2 to bypass the analog filter, or set the jumper on pins 2 − 3 to route the analog input through the filter (default setting).

Table 2−1: Analog Input Filter Bypass Jumpers

Input Channel Jumper Blocks

CH1

CH2

CH3

CH4

JB1 & JB2

JB3 & JB4 JB5 & JB6 (6230 only) JB7 & JB8 (6230 only)

Pins 1 − 2 = Bypass the analog filter Pins 2 − 3 = Use the analog filter *

Jumper Position

* (factory default setting)

For a given input channel, make sure to set both jumper blocks to the same

Note

pin positions.

Rev.: B.4

Page 22

Page 22 Pentek Model 6230/6231 Operating Manual

2.2 Jumper Block Settings (continued)

2.2.2 FPGA Configuration Data Source Jumper

Jumper JB9 selects the source of the Virtex FPGA configuration data down− load. The FPGA can select its configuration data either from an on−board Serial EEPROM or from a serial download (X−Checker cable), depending on the setting of this jumper. The following table shows the jumper settings for this FPGA configuration data source jumper. This jumper block has three pins, similar to the Filter Bypass jumpers (see illustration in Table 2−1, on prior page). (Refer to Virtex Config Register, Section 3.3, for further infor− mation on reconfiguring the Virtex FPGAs.)

Table 2−2: FPGA Configuration Data Source Jumper

Jumper JB9 Position FPGA Data Source

Pins 1 − 2 Serial Download

Removed, or pins 2 − 3 * On−board Serial EEPROM

* Factory Default Setting

2.2.3 External TTL Inputs Select Jumpers

Jumper block JB10 selects the input connector to use as the source of the external TTL SYNC or TTL GATE inputs. Each TTL signal can be input from either the 26−pin sync/gate connector (see Section 2.4.3) or the 4−pin sync/ gate header (see Section 2.4.4) on the front panel. The following table shows the jumper settings for this jumper block.

Table 2−3: External TTL Inputs Select Jumpers

Jumper JB10 Position External TTL Gate/Sync Inputs

Pins 1 − 2

Pins 3 − 4

Installed

Removed

Installed

Removed

1 − Factory Default Setting on Model 6231 2 − Factory Default Setting on Model 6230

TTL SYNC from 26−pin Sync/Gate Connector

TTL SYNC from 4−pin Sync/Gate/Trig Header

TTL GATE from 26−pin Sync/Gate Connector

TTL GATE from 4−pin Sync/Gate/Trig Header

Rev.: B.4

Page 23

Pentek Model 6230/6231 Operating Manual Page 23

2.2 Jumper Block Settings (continued)

Upper

JB2

Front Panel

Rear

Mounting

Holes

(a)

JB1

JB4

JB3

JB9

JB10

Filter Bypass Jumpers (

Shield

removed

JB6

JB5

)

(b)

Figure 2−1: Model 6230 PCB Assembly, Component Side

JB8

JB7

Rev.: B.4

Page 24

Page 24 Pentek Model 6230/6231 Operating Manual

2.2 Jumper Block Settings (continued)

Front

JB2

Panel

Rear

Mounting

Hole

JB1

(a)

JB4

JB10

JB9

JB3

Figure 2−2: Model 6231 PCB Assembly, Component Side

Fron Panel

Panel Mounting Holes

JB9

JB10

Filter Bypass Jumpers

Shield

(

removed

)

Figure 2−3: Model 6231 Option 102 PCB Assembly, Component Side

Rev.: B.4

J13

Standoff Mounting Holes

J12

Page 25

Pentek Model 6230/6231 Operating Manual Page 25

2.3 Installing the Model 6230/6231 on a VIM Baseboard

This section provides instructions for installing the Model 6230 VIM−4 module or the Model 6231 VIM−2 module on a VIM−compatible baseboard. Pentek’s VIM base− boards ship with two blank panels and four VIM interface connectors where you can install optional VIM modules, such as the Model 6230 or Model 6231. An illustration of a typical Pentek VIM baseboard is provided in Figure 2−4 on the following page.

Perform all assembly steps at an antistatic workstation.

CAUTION

Tools required for all procedures:

• #1 Phillips screwdriver

• Flat−blade screwdriver (blade width 5/16−inch or less)

The Models 6230 and 6231 are shipped in different configurations. The installation instructions vary according to the configuration you receive from Pentek, as follows:

 If you have ordered a Model 6230, or a Model 6231 without Option 102, for

installation on your VIM baseboard, you have received a single VIM module that you must mount on your existing VIM baseboard.

Refer to Section 2.3.1 for the instructions for this configuration.

 If you have ordered a Model 6231 with Option 102 for installation on your VIM

baseboard, you have received an assembly of a Model 6231 PCB and an Option 102 PCB that you must disassemble and mount on your existing VIM baseboard.

Refer to Section 2.3.2 for the instructions for this configuration.

Note

All required mounting hardware and front panels are included with your shipment.

Be sure to follow all instructions in the order presented.

Rev.: B.4

Page 26

Page 26 Pentek Model 6230/6231 Operating Manual

2.3 Installing the Model 6230/6231 on a VIM Baseboard (continued)

(a)

(b)

(c)

Top Position

Mounting Holes

Bottom Position

Mounting Holes

(f)

(e)

Top Position

VIM Connectors

Bottom Position VIM Connectors

(d)

Figure 2−4: Typical VIM Baseboard − Connectors & Mounting Holes

Rev.: B.4

Page 27

Pentek Model 6230/6231 Operating Manual Page 27

2.3 Installing the Model 6230/6231 on a VIM Baseboard (continued)

2.3.1 Installing Model 6230, or Model 6231 without Option 102

This section provides instructions for installing a Model 6230 VIM−4 or Model 6231 VIM−2 (without Option 102) on your existing VIM baseboard.

The Model 6230 or 6231 is shipped as an assembled unit and must be disas− sembled for installation.

1) Remove both front panels from the Model 6230 VIM−4 module [single front panel from the Model 6231 VIM−2 module] by removing the two countersunk Phillips screws from each panel (see following illustration).

VIM Panel Screws Shipping Bracket Screws

VIM Panel Shipping Brackets

Figure 2−5: VIM−4 Panel Mounting & Shipping Screws

(Model 6230 illustrated, with lower panel removed)

2) Remove the (red) shipping brackets that hold the front panel(s) to the VIM module by removing the pan−head Phillips shipping bracket screws from the solder side of the VIM PCB (see illustration above). Set these screws aside, as they are used to secure the VIM module to the VIM baseboard.

(The shipping brackets may be discarded, or saved to store the panels on the VIM module if it is removed from the VIM baseboard.)

3) At the rear of the Model 6230 PCB, on the component side, are two nylon spacers [one spacer on the Model 6231 VIM−2 PCB] (see Figure 2−6 on the next page). Remove the nylon screws that are threaded into the top of the spacers from the component side. Set these screws aside, as they are used to secure the VIM module to the VIM baseboard.

Rev.: B.4

Page 28

Page 28 Pentek Model 6230/6231 Operating Manual

2.3 Installing the Model 6230/6231 on a VIM Baseboard (continued)

2.3.1 Installing Model 6230, or Model 6231 w/o Option 102 (continued)

Note

Nylon Spacer

Nylon Screw

VIM module

Figure 2−6: VIM Module Nylon Spacer

The nylon spacers must be in the holes at the REAR of the VIM connectors, farthest from the front panel (as illustrated above, and indicated at locations (a) and (b) in Figures 2−1 and 2−2). If either spacer is in the front hole, reposition it using the nylon screw on the solder side of the module.

Rev.: B.4

4) For the Model 6230, remove both blank panel inserts from the VIM baseboard, by removing the two countersunk Phillips screws from each insert (see illustration below). For the Model 6231, remove one blank panel insert, at the VIM position you wish to install the VIM−2 module.

Blank Panel Screws

210

Figure 2−7: VIM Baseboard Blank Panel Screws

Page 29

Pentek Model 6230/6231 Operating Manual Page 29

2.3 Installing the Model 6230/6231 on a VIM Baseboard (continued)

2.3.1 Installing Model 6230, or Model 6231 w/o Option 102 (continued)

5) With the VIM baseboard’s component side (the side with the VIM

connectors) facing up, align the four VIM connectors on the Model 6230 VIM−4 module (J1, J2, J3, and J4) with the four VIM connectors on the baseboard. For the Model 6231, align the two mezzanine connectors on the VIM−2 module (J1 and J2) with two of the VIM connectors on the baseboard—the Model 6231 VIM−2 module may be installed in either the top or bottom mezzanine position on the VIM baseboard. See Figures 2−1 and 2−2 for location of the Models 6230 and 6231 VIM connectors, and see

Figure 2−4 for location of the VIM connectors on a typical VIM baseboard.

6) GENTLY but firmly, press down on the VIM module opposite the

connectors, to fully seat the module’s connectors into the baseboard’s. If you meet with significant resistance, check the connector alignment.

NOTE:

Misalignment can cause bent pins or break connector housings, so NEVER APPLY EXCESSIVE FORCE.

7) After seating the connectors, secure the front of the VIM module to the

VIM baseboard by screwing four [two for the Model 6231] pan−head Phillips screws through the holes at the front of the VIM module into the threaded holes in baseboard’s panel brackets (indicated at positions (a), (b), (c), and (d) on Figure 2−4).

8) Turn the assembly over, such that the VIM module is on the work surface

and the solder side of the VIM baseboard is facing up. Secure the baseboard to the nylon spacer(s) on the VIM module, using the two nylon screws removed earlier [one for the Model 6231], through the rear mounting hole(s) on the baseboard (indicated at positions (e) and (f) on

Figure 2−4).

9) Attach the VIM module’s front panel(s) to the baseboard, by screwing the

countersunk Phillips screws through the holes of each VIM panel into the threaded holes in the front of the baseboard’s panel brackets. Note that the Model 6230 panels fit only in their proper locations on the baseboard.

The Model 6230/6231 installation is complete.

Rev.: B.4

Page 30

Page 30 Pentek Model 6230/6231 Operating Manual

2.3 Installing the Model 6230/6231 on a VIM Baseboard (continued)

2.3.2 Installing Model 6231 with Option 102

The Model 6231 with Option 102 is shipped as an assembled unit and must be disassembled for installation on your baseboard. A separate Option 102 front panel assembly is also provided.

1) Remove both front panels from the Model 6231 VIM−2 module and the Option 102 module by removing the two countersunk Phillips screws from each panel (see following illustration).

Standoff Screws (5)

Standoffs

VIM Panel Screws

Shipping Bracket Screws (2)

Stacking Connectors (2)

VIM Panel Shipping Brackets

(Side View)

Figure 2−8: Model 6231 with Option 102 Shipping Assembly

(Shown with Option 102 panel removed)

2) Remove the (red) shipping brackets that hold the front panels to both boards by removing the two pan−head Phillips shipping bracket screws from the solder side of the Option 102 board (see illustration above).

(The shipping brackets may be discarded, or saved to store the panels if they are removed.)

3) Remove and set aside the five pan−head Phillips standoff screws from the top of the Option 102 board (see figure above).

4) CAREFULLY, remove the Option 102 board from the stacking connectors (see figure above), taking care to not bend the pins.

5) GENTLY, remove and set aside both stacking connectors from the Model 6231 PCB. Do not remove the five (black) metal standoffs from this PCB.

Be careful when removing the stacking connectors, as they are fragile

CAUTION

Rev.: B.4

and can easily be damaged.

Page 31

Pentek Model 6230/6231 Operating Manual Page 31

2.3 Installing the Model 6230/6231 on a VIM Baseboard (continued)

2.3.2 Installing Model 6231 with Option 102 (continued)

6) A nylon spacer is installed on the component side of the Model 6231 PCB,

between the VIM connectors. Remove and set aside the nylon screw that is threaded into the top of the spacer (see following illustration).

Note

Nylon Spacer

Nylon Screw

VIM module

Figure 2−9: VIM Module Nylon Spacer

The nylon spacer must be installed in the hole at the REAR of the VIM connectors, farthest from the front panel (as shown in the figure above). If the spacer is installed in the front hole, reposition it using the nylon screw on the solder side of the module.

7) Remove one blank panel insert from your VIM baseboard, at the VIM

position you wish to install the Model 6231 module, by removing the two countersunk Phillips screws from that blank panel insert (see following illustration).

Blank Panel Screws

321

210

Figure 2−10: VIM Baseboard Blank Panel Screws

Rev.: B.4

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Page 32 Pentek Model 6230/6231 Operating Manual

2.3 Installing the Model 6230/6231 on a VIM Baseboard (continued)

2.3.2 Installing Model 6231 with Option 102 (continued)

8) With the VIM baseboard’s component side (the side with the VIM connectors) facing up, align the two VIM connectors on the Model 6231 VIM−2 module (J1 and J2) with two VIM connectors on the baseboard— the Model 6231 VIM−2 module may be installed in either the top or bottom mezzanine position on the VIM baseboard. See Figure 2−2 for location of the Model 6231 VIM connectors, and see Figure 2−4 for location of the VIM connectors on a typical VIM baseboard.

9) GENTLY but firmly, press down on the VIM module opposite the connectors to fully seat the VIM module’s connectors into the baseboard’s. If you meet with significant resistance, check the connector alignment.

NOTE:

Misalignment can cause bent pins or break connector housings, so NEVER APPLY EXCESSIVE FORCE.

10) After seating the connectors, secure the front of the VIM module to the VIM baseboard by screwing two short pan−head Phillips screws through the holes at the front of the VIM module into the threaded holes in the baseboard’s panel brackets (indicated at positions (a) and (b), or (c) and (d) on Figure 2−4).

11) Turn the assembly over, such that the VIM module is on the work surface and the solder side of the VIM baseboard is facing up. Secure the baseboard to the nylon spacer on the VIM module, using the nylon screw removed earlier, through the rear mounting hole on the baseboard (indicated at position (e) or (f) on Figure 2−4).

12) Remove one top or bottom blank panel insert from the Option 102 front panel assembly provided (see illustration below), depending on the VIM position in which the Model 6231 module was installed in the above steps. The remaining fixed plates and blank panel will be installed onto the baseboard front panel in the following steps.

Top

fixed plate

Figure 2−11: Option 102 Front Panel Assembly

Rev.: B.4

Top blank panel Bottom blank panel

Middle

fixed plate

Bottom

fixed plate

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Pentek Model 6230/6231 Operating Manual Page 33

2.3 Installing the Model 6230/6231 on a VIM Baseboard (continued)

2.3.2 Installing Model 6231 with Option 102 (continued)

13) Install the Option 102 front panel assembly, which is in two pieces

depending on which blank panel you removed in the prior step, onto the VIM baseboard front panel, using the four long pan−head Phillips screws supplied (see following illustration).

Front Panel Bracket Screws

Option 102 Standoff

210

Figure 2−12: VIM Baseboard with Option 102 Front Panel Assembly

(Model 6231 illustrated in upper VIM position)

14) CAREFULLY, insert the two stacking connectors into the solder side of the

Model 6231 PCB. Note that the stacking connector’s longer leads must be inserted through holes on the solder side of the PCB (see following illustration).

Stacking Connectors

Stacking Connector Long Leads

VIM PCB

(Side View)

Figure 2−13: Option 102 Stacking Connectors on VIM Module

Be careful when installing the stacking connectors, as they are fragile

CAUTION

and can easily be damaged.

Rev.: B.4

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Page 34 Pentek Model 6230/6231 Operating Manual

2.3 Installing the Model 6230/6231 on a VIM Baseboard (continued)

2.3.2 Installing Model 6231 with Option 102 (continued)

15) Align the Option 102 PCB connectors J1 and J2 with the two stacking connectors on the VIM module. GENTLY but firmly, press down on the areas of the board opposite the connectors to fully seat the board’s connectors into the VIM module.

NOTE:

Misalignment can cause bent pins or break connector housings, so NEVER APPLY EXCESSIVE FORCE.

16) After seating the connectors, secure the front of the Option 102 PCB to the baseboard by screwing two short pan−head Phillips screws through the holes in the front of the PCB into the threaded holes in the Option 102 front panel assembly’s panel brackets (see illustration below) .

Standoff Screws (5)

Standoffs

Front Mounting Screws (2)

Figure 2−14: Option 102 PCB Mounted on VIM Module

Option 102 PCB

VIM PCB

VIM Panel Brackets

(Side View)

17) Screw the five pan−head Phillips standoff screws removed from the PCB earlier through the solder side of the Option 102 PCB into the VIM module standoffs (see illustration above).

18) Attach the Model 6231 and Option 102 front panels to the assembly, by screwing the countersunk Phillips panel screws through the holes in each VIM panel into the corresponding threaded holes in the front panel brackets.

The Model 6231 installation is complete.

Rev.: B.4

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Pentek Model 6230/6231 Operating Manual Page 35

2.4 Front Panel Connections

The Model 6230 has two (upper and lower) VIM front panels. The Model 6231 stan− dard configuration has a single VIM front panel—a second front panel is provided with Option 102, mounted on an adjacent board. The Model 6231 panels can be installed in either the upper or the lower VIM position of the baseboard (Section 2.3). All panels are illustrated in Figure 2−15, on the following page.

The front panel signal connectors are described in the following subsections. The front panel LEDs are described in Section 2.5.

2.4.1 Analog Input Connectors

The front panels provide threaded, coaxial SMA connectors for analog sig− nal inputs, one for each A/D input channel. The Model 6230 has four analog input connectors labeled CH1 IN to CH4 IN, two on each panel. The Model 6231 has two analog input connectors labeled CH1 IN and CH2 IN on its standard panel.

The analog input signal to each connector must be in the range of 2 V ±1.0 V. Each input drives an Analog Devices OPA642 amplifier with approximately 50

Ω input impedance, which amplifies the amplitude of the

signal by a factor of one.

2.4.2 Sample Clock Input Connector

The Model 6230 upper panel, and Model 6231 standard panel, has a threaded, coaxial SMA connector, labeled EXT CLK IN, for input of an external clock. The external clock signal should be a TTL pulse train with a 45% to 55% duty cycle, or a sine signal of 1 to 3 V

This input clock can be used as the reference signal to derive the sample clock signal for the A/D converters and digital receivers. Use bit D2, EXT CLK, in the Master Control Register (see Section 3.7.8), to enable this input.

p−p

Rev.: B.4

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Page 36 Pentek Model 6230/6231 Operating Manual

2.4 Front Panel Connections (continued)

Upper

Panel

Lower

Panel

Model 6230

Figure 2−15: Models 6230 and 6231 Front Panels

Rev.: B.4

Standard

Panel

Model 6231

Option 102

Panel

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Pentek Model 6230/6231 Operating Manual Page 37

2.4 Front Panel Connections (continued)

2.4.3 Sync/Gate Connector

The 26−pin SYNC/GATE connector provides input/output pins for the

low−voltage differential signal (LVDS) Sync Bus: four gates, one sync, and one clock. When the Model 6230/6231 is a sync bus Master, these pins out− put the bus to other slave units. When the 6230/6231 is a Slave, these pins input the signals from a Master. This connector also accepts two TTL gate and sync inputs. The mating 26−pin connector is Pentek part # 353.02607 (ERNI part # 214346). The following table shows the connector pinouts.

Table 2−4: SYNC/GATE Connector Pins

Signal Pin Pin Signal

TTL GATE B1 A1 GND TTL SYNC B2 A2 GND

GATE D− B3 A3 GATE D+

GND B4 A4 GND

GATE C− B5 A5 GATE C+

GND B6 A6 GND

GATE B− B7 A7 GATE B+

GND B8 A8 GND

GATE A− B9 A9 GATE A+

GND B10 A10 GND

SYNC− B11 A11 SYNC+

GND B12 A12 GND

CLK− B13 A13 CLK+

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11 B12 B13

A1 A2 A3 A4 A5 A6 A7 A8

A9 A10 A11 A12 A13

2.4.4 Sync/Gate Header

The 4−pin SYNC/GATE/TRG connector [optional on the Model 6231] pro−

vides a second set of pins for TTL sync/gate inputs. These are wired to the

same TTL SYNC and GATE signals as pins B2 and B1 of the SYNC/GATE

connector, above. The mating 2−pin connector housing (use two for both signals) is Pentek part # 353.00201 (Berg # 65039−035) or equivalent. This housing uses discrete 0.025" square socket pins, Pentek part # 354.00104 (Berg # 48254−000). The following table shows the connector pinouts.

TTL SYNC 1 2 GND

TTL GATE/TRG 3 4 GND

Table 2−5: SYNC/GATE/TRG Header Pins

Signal Pin Pin Signal

2 4

Rev.: C.1

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Page 38 Pentek Model 6230/6231 Operating Manual

2.4 Front Panel Connections (continued)

2.4.5 FPGA Connector

The 50−pin FPGA connector for the Model 6230 includes two 16−pin FPGA

input/output data paths. The pins correspond to bits D15 through D0 of the I/O Data Register for each of the FPGAs (see Section 3.22). This 50−pin connector is optional on Model 6231 (Option 102), and includes one 24−pin I/O data path. These pins correspond to bits D15 through D0 of the I/O Data Register (see Section 3.22), and bits D16 through D23 of the I/O Data 2 Register (see Section 3.22). The mating connector is Pentek part # 353.05006 (ERNI part # 214347). The following table shows the connector pin configu− ration for both VIM models.

Table 2−6: FPGA Connector Pins

Model 6230 Model 6231 Pin Pin Model 6230 Model 6231

GND GND B1 A1 GND GND FPGA2 I/O 15 N/C B2 A2 FPGA2 I/O 14 N/C FPGA2 I/O 13 N/C B3 A3 FPGA2 I/O 12 N/C

GND GND B4 A4 GND GND FPGA2 I/O 11 N/C B5 A5 FPGA2 I/O 10 N/C

FPGA2 I/O 9 N/C B6 A6 FPGA2 I/O 8 N/C

GND GND B7 A7 GND GND

FPGA2 I/O 7 FPGA I/O 23 B8 A8 FPGA2 I/O 6 FPGA I/O 22 FPGA2 I/O 5 FPGA I/O 21 B9 A9 FPGA2 I/O 4 FPGA I/O 20

GNDGNDB10 A10GNDGND

FPGA2 I/O 3 FPGA I/O 19 B11 A11 FPGA2 I/O 2 FPGA I/O 18 FPGA2 I/O 1 FPGA I/O 17 B12 A12 FPGA2 I/O 0 FPGA I/O 16

N/C N/C B13 A13 N/C N/C

GNDGNDB14 A14GNDGND FPGA1 I/O 15 FPGA I/O 15 B15 A15 FPGA1 I/O 14 FPGA I/O 14 FPGA1 I/O 13 FPGA I/O 13 B16 A16 FPGA1 I/O 12 FPGA I/O 12

GNDGNDB17 A17GNDGND FPGA1 I/O 11 FPGA I/O 11 B18 A18 FPGA1 I/O 10 FPGA I/O 10

FPGA1 I/O 9 FPGA I/O 9 B19 A19 FPGA1 I/O 8 FPGA I/O 8

GNDGNDB20 A20GNDGND

FPGA1 I/O 7 FPGA I/O 7 B21 A21 FPGA1 I/O 6 FPGA I/O 6

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11 B12 B13 B14 B25 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25

FPGA1 I/O 5 FPGA I/O 5 B22 A22 FPGA1 I/O 4 FPGA I/O 4

GNDGNDB23 A23GNDGND FPGA1 I/O 3 FPGA I/O 3 B24 A24 FPGA1 I/O 2 FPGA I/O 2 FPGA1 I/O 1 FPGA I/O 1 B25 A25 FPGA1 I/O 0 FPGA I/O 0

A1 A2 A3 A4 A5 A6 A7 A8

A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25

Rev.: C.1

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Pentek Model 6230/6231 Operating Manual Page 39

2.5 Front Panel LEDs

The Model 6230 front panel has eight LED indicators [six LEDs on the Model 6231], as illustrated in Figure 2−15, on page 36.

2.5.1 Clock (CLK) LED

The green CLK LED is illuminated when a valid clock signal is detected. If this LED is not illuminated, then no clock has been detected and no data from the input stream can be processed.

2.5.2 Over Temperature (TEMP) LED

There are four temperature/voltage sensors on the Model 6230 PCB [two sensors on the Model 6231 PCB]. The temperature sensor thresholds are set by a baseboard processor (see Hardware Monitor Port Register, Section 3.6). When an over−temperature (or over−voltage) condition is indicated, the red TEMP LED is illuminated on the front panel. In addition, two TEMP inter− rupts from these sensors are available to all processors on the VIM base− board (see Table 3−18, Section 3.14).

NOTE:

You must set up the temperature/voltage sensors’ Hardware Monitor Port following power on of the VIM baseboard. ReadyFlow board support software is provided for this purpose (see Hardware Monitor Port Register, Section 3.6).

2.5.3 Master (MAS) LED

The yellow MAS LED illuminates when this Model 6230/6231 is the sync bus Master (MASTR bit D00 = 1, Master Control Register, Section 3.7.10). The bus Master generates all sync/gate/clock signals on the sync bus.

2.5.4 Terminate (TRM) LED

When this Model 6230/6231 is the last (or only) Slave unit on the sync bus, you must enable bus termination (TERM bit D01, Master Control Register,

Section 3.7.9). Enabling bus termination illuminates the yellow TRM LED.

2.5.5 Overload (OVLD CHn) LEDs

There are four red overload LEDs on the Model 6230 [two on the Model 6231], one for each A/D input, labeled OVLD CH1 to OVLD CH4 [OVLD CH1 to OVLD CH2]. Each LED is an indicator for an A/D overload detec− tion function in each of the AD6644 A/D converters. When an overload indication is set by the AD6644, the associated OVLD LED is illuminated. In addition, an OVLD interrupt may be generated from each A/D overload indication to all VIM baseboard processors (see Table 3−18, Section 3.14).

Rev.: B.4

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This page is intentionally blank

Rev.: B.4

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Pentek Model 6230/6231 Operating Manual Page 41

Chapter 3: Memory Maps and Register Descriptions

3.1 Overview

This chapter describes processor access to the Model 6230 and Model 6231 from the VIM baseboard. Memory maps to VIM module resources are given from the baseboard processor’s viewpoint, and details are provided describing the use of each resource.

3.2 Model 6230/6231 Memory Map

The two tables below provide base addresses of the control and status registers for each type of Pentek VIM Baseboard. Use the applicable base address from these tables as the VIM registers base address (‘

For a Pentek Model 4290 through 4295 VIM baseboard, use the VIM base addresses in

Table 3−1, below. On these baseboards, each node processor uses the same VIM base

address, which refers to the VIM Node Interface connected to that processor.

VIM_base’) in the following sections.

Table 3−1: VIM Base

Addresses for Models 4290 to 4295 VIM Baseboards

VIM Baseboard VIM Registers Base Address (VIM_base)

Model 4290 or 4291 0x0032 0000

Model 4292 or 4293 0x0202 0000

Model 4294 or 4295 0x1D02 0000

For a Pentek Model 4205 VIM baseboard, use the VIM base addresses in Table 3−2, below. The Model 4205 has a single baseboard processor, which uses a separate base address for each VIM Node Interface (emulating four processors). In addition, on this baseboard the VIM module registers can be accessed from the VMEbus.

Table 3−2: VIM Base Addresses for Model 4205 VIM Baseboards

VIM Registers Base Address (VIM_base)

VIM

MPC7455 VMEbus A32 Slave *

VIM A 0x4082 0000 A32VME_base + 0x00B2 0000

VIM B 0x4086 0000 A32VME_base + 0x00B6 0000

VIM C 0x408A 0000 A32VME_base + 0x00BA 0000

VIM D 0x408E 0000 A32VME_base + 0x00BE 0000

* Offsets relative to the base address ‘A32VME_base’ set on the Model 4205 baseboard (refer

to the Model 4205 Operating Manual for these settings)

Rev.: B.4

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Page 42 Pentek Model 6230/6231 Operating Manual

3.2 Model 6230/6231 Memory Map (continued)

The following table provides a memory map for accessing the Model 6230/6231 control registers. All register addresses are expressed as offsets from the VIM base address for th e applicable VIM baseboard—see Table 3−1 or Table 3−2 on the prior page for the VIM registers base address (‘VIM_base’) for your VIM baseboard. The subsections follow− ing the table provide detailed information about each register.

Table 3−3: Model 6230/6231 Memory Map

Address Offset* Register Description Access Additional Info.

VIM_base+0x0000 ID EEPROM Readout R.O. Appendix A

VIM_base+0x0004 Virtex Config (Proc A & C only) R/W Section 3.3

VIM_base+0x0008 Virtex Config Data (Proc A & C only) W.O Section 3.4

VIM_base+0x000C Wait State R/W Section 3.5

VIM_base+0x0010 Hardware Monitor Port (Proc A or C only) R/W Section 3.6

VIM_base+0x0014 – 0x001C Not Used − −

VIM_base+0x0020 Master Control (Proc A or C only) R/W Section 3.7

VIM_base+0x0024 Bypass Rate Divide R/W Section 3.8

VIM_base+0x0028 Channel Enable R/W Section 3.9

VIM_base+0x002C Not Used − −

VIM_base+0x0030 Gate Control R/W Section 3.10

VIM_base+0x0034 Trigger Length R/W Section 3.11

VIM_base+0x0038 Channel Control R/W Section 3.12

VIM_base+0x003C Sync/Gate Generator R/W Section 3.13

VIM_base+0x0040 Not Used − −

VIM_base+0x0044 Interrupt Mask R/W Section 3.14

VIM_base+0x0048 Interrupt Flag R/Clr Section 3.15

VIM_base+0x004C Interrupt Status R.O. Section 3.16

VIM_base+0x0050 Semaphore R/W Section 3.17

VIM_base+0x0054 Not Used − −

VIM_base+0x0058 I/O Direction 2 (Model 6231, Proc A or C only) R/W Section 3.18

VIM_base+0x005C I/O Data 2 (Model 6231, Proc A or C only) R/W Section 3.19

VIM_base+0x0060 I/O Direction (Proc A & C only) R/W Section 3.20

VIM_base+0x0064 I/O Enable (Proc A & C only) R/W Section 3.21

VIM_base+0x0068 I/O Data (Proc A & C only) R/W Section 3.22

VIM_base+0x006C – 0x00FC Not Used − −

VIM_base+0x0100 – 0x01FC Graychip Registers R/W Section 3.23

* VIM_base = see Table 3−1 or Table 3−2 on prior page

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Pentek Model 6230/6231 Operating Manual Page 43

3.3 Virtex Config Register

The Virtex Config Register is used to reconfigure/reprogram the Virtex FPGAs. The bits in this register allow you to read and set the status of the FPGA configuration cycle, and to upload the configuration from a VIM processor. Only Processor A and Proces− sor C on the VIM baseboard have their own version of this register, for the Virtex FPGA associated with that processor (for example, FPGA1 for Processor A).

Refer to Section 1.10, FPGA Configuration, for additional information about configur− ing the gate arrays.

The following table shows the contents of the Virtex Config Register. The subsections following the table provide descriptions of the bits in this register.

Table 3−4: Virtex Config Register

R/W @ VIM_base+0x0004 (Proc A & C only)

D15 – D06 D05 D04* D03* D02* D01 D00

Bit Name

Function

Not used WRITE BUSY INIT DONE PRGM LD SRC

Write zeros,

Mask read

All bits default to the logic '0' state at power on and reset

0 = Disable

1 = Write

0 = Disable

1 = Enable

* These bits are Read Only

0 = Configuring

1 = Completed

0 = Configuring 1 = Completed

0 = Disable

1 = Reprogram

0 = Onboard

1 = Upload

3.3.1 WRITE Bit D05

This bit sets the write access of the Virtex Config Data Register, described in

Section 3.4. When you set this bit to logic '1', you can write configuration

data to the FPGA. To write data with the Virtex Config Data Register, you must also enable configuration Processor Upload (LD SRC bit D00 = 1, next page). Clear the bit to logic '0' (its default state) to disable configuration data from being accepted by the FPGA.

3.3.2 BUSY Bit D04

This read−only bit indicates the status of the Virtex FPGA’s ‘BUSY’ pin. It is only meaningful in processor upload mode, though not needed. (For refer− ence only.)

3.3.3 INIT Bit D03

This read−only bit indicates the status of the Virtex FPGA’s ‘INIT initialization of a configuration cycle this bit goes to logic '0', then logic '1'. It will remain at logic '0' if an error in configuration data is detected. When read as logic '1', initialization is done.

’ pin. At

Rev.: B.4

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Page 44 Pentek Model 6230/6231 Operating Manual

3.3 Virtex Config Register (continued)

3.3.4 DONE Bit D02

This read−only bit indicates the status of the Virtex FPGA’s ‘DONE’ pin. When read as logic '0', the FPGA is in the configuration cycle. When read as logic '1', the FPGA has completed configuration.

3.3.5 PRGM Bit D01

The FPGA begins a configuration reprogramming cycle after you transition this bit from logic '0', to logic '1', then to logic '0', while in Serial PROM or Processor Upload mode (see LD SRC, below). It has no effect in the Serial Download mode, as the X−Checker cable has control in that mode.

3.3.6 LD SRC Bit D00

This bit selects the source of the Virtex FPGA configuration data. When you clear this bit to logic '0' (its default state), the FPGA selects its configuration data from the on−board Serial PROM or from a Serial Download, depending on the setting of the configuration data source jumper on the module’s PCB, see Section 2.2. When you set this bit to logic '1', the FPGA is in Processor Upload mode, and you can upload the configuration from the processor using the Virtex Config Data Register, as described in Section 3.4 below.

3.4 Virtex Config Data Register

The Virtex Config Data Register writes configuration data to the Virtex FPGA. Write access is set using the WRITE bit in the Virtex Config Register, Section 3.3.1. When LD SRC = 1, Section 3.3.6, FPGA configuration data can be written, one byte at a time, using this register. Processors A and C on the VIM baseboard have their own version of this register, for the Virtex FPGA associated with that processor (for example, FPGA1 for Processor A). The following table shows the contents of this register.

Table 3−5: Virtex Config Data Register

W.O. @ VIM_base+0x0008 (Proc A & C only)

D15 – D08 D07 D06 D05 D04 D03 D02 D01 D00

Bit Name

Function

Not used D7 D6 D5 D4 D3 D2 D1 D0

Write zeros,

Mask read

When reset or power−up, the state of this register is unknown.

Eight bits (one byte) of configuration data

Refer to Section 1.10, FPGA Configuration, for additional information about configur− ing the Virtex FPGA.

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Pentek Model 6230/6231 Operating Manual Page 45

3.5 Wait States Register

With the possibility of DBCLKs on future processor boards above 50 MHz, program− mable wait states are provided to guarantee adequate access time. These wait states are user−programmable, using the Wait States Register. Each processor on the VIM base− board has its own version of this register for the devices associated with that processor (for example, Processor A can set the wait states for FPGA1 and CG4016 A & B).

The following table shows the contents of this register. The paragraphs following the table provide descriptions of these bits.

Table 3−6: Wait States Register

R/W @ VIM_base+0x000C

D15 – D08 D07 D06 D05 D04 D03 D02 D01 D00

Bit Name

Function

Not used

Write zeros,

Mask read

GC DDR W3GC DDR W2GC DDR W1GC DDR W0CTL REG W3CTL REG W2CTL REG W1CTL REG

Number of wait states for DDRs Number of wait states for FPGAs

All bits default to the logic '1' state at power on and reset

NOTE:

At power up, the wait states default to a maximum.

The binary value in the four GC DDR bits determines the number of wait states for both GC4016 DDRs (wait state = [GC DDR] + 2 DBCLK cycles).

The binary value in the four CTL REG bits sets the number of wait states for the FPGA (wait state = [CTL REG] + 2 DBCLK cycles).

The wait states are equal to the greater of the VIM interface minimum write cycle time or the wait state selection in this register.

For Model 6230/6231 boards with a DBCLK of 50 MHz or less, a setting of GC DDR = 0x2 and CTL REG = 0x2 is adequate.

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Page 46 Pentek Model 6230/6231 Operating Manual

3.6 Hardware Monitor Port Register

The board’s Voltage/Temperature Monitors, Analog Devices ADM1024s, provide con− stant monitoring of critical voltages and temperatures on the PCB. There are four tem− perature sensors on the Model 6230 [two on the Model 6231], which are controlled by the Hardware Monitor Port. When an over−temperature or over−voltage condition is indicated, the red TEMP LED is illuminated on the front panel. In addition, an over− temperature/voltage interrupt from each ADM1024 is available to all VIM baseboard processors (see Table 3−18, Section 3.14).

There are several programmable temperature and voltage sensors controlled by these ADM1024s. The Hardware Monitor Port Register allows you to configure the sensor thresholds. The Hardware Monitor Port Register is accessible only to Processor A on the VIM baseboard (or to Processor C for a Model 6231 that is installed in the bottom VIM position on the baseboard).

The following table shows the contents of this register. The register contains three bits: one bit sets the read/write direction of the register and the other two provide the serial clock and data to/from the Hardware Monitor Port.

Bit Name

Function

Note

Table 3−7: Hardware Monitor Port Register

R/W @ VIM_base+0x0010 (Proc A or C only)

D15 – D03 D02 D01 D00

Not used SER DIR SER CLK SER DAT

Write with zeros, Mask when reading

All bits default to the logic '0' state at power on and reset

0 = Write

1 = Read

Serial Clock

Serial

Data

You must set up the Hardware Monitor Port and the port devices following power on of the VIM baseboard.

Routines for setup and programming the temperature and voltage thresholds are pro− vided in the ReadyFlow board support software for the Model 6230 (Pentek part #801.62300).

Alternately, you can program the voltage and temperature thresholds directly using the Hardware Monitor Port Register. The instructions for programming the ADM1024 with this register are provided on the following page.

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Pentek Model 6230/6231 Operating Manual Page 47

3.6 Hardware Monitor Port Register (continued)

The Model 6230 uses two ADM1024’s. Each ADM1024 controls several temperature sensors and voltage sensors on the PCB. Both ADM1024’s can be accessed only from processor A using the Hardware Monitor Port Register. The Model 6231 uses one ADM1024, which can be accessed only from processor A or C, depending on its installed VIM position, using the Hardware Monitor Port Register.

You can set their limits using internal ADM1024 registers (refer to the ADM1024 data sheet, Appendix D, for description of these registers). These ADM1024 registers are programmed from the Hardware Monitor Port Register and are addressed using sepa− rate bus read and write addresses, sent as serial data through the port.

• On the Model 6230 with two ADM1024’s, the bus addresses are ("Upper" and “Lower” refer to the associated VIM position on the baseboard for each ADM1024):

Upper ADM1024 − bus write address: 58 hex Upper ADM1024 − bus read address: 59 hex Lower ADM1024 − bus write address: 5A hex Lower ADM1024 − bus read address: 5B hex

• On the Model 6231 with one ADM1024, the bus addresses are:

Bus write address: 58 hex Bus read address: 59 hex

There are eight conditions on the PCB monitored by each ADM1024. These conditions, the registers used, and their limits are identified in the following table:

Table 3−8: ADM1024 Registers

Monitored Condition ADM1024 Register Limits

Internal temperature Internal Temp Value 0 to 85 degrees C External temperature sensor 1 (under shield) Ext. Temp1 Value 0 to 85 degrees C External temperature sensor 2 (on PCB) +2.5V Measured Value/EXT Temp2 0 to 85 degrees C +1.8 Volt supply +Vccp1 Measured Value +1.8 Volts, ±10% +2.5 Volt supply FAN2/AIN2 Value +2.5 Volts, ±10% +3.3 Volt supply Vcc Measured Value +3.3 Volts, ±10% +5 Volt supply +5V Value +5 Volts, ±10% +12 Volts Supply +12V Measured Value +12 Volts, ±10%

Refer to the ADM1024 data sheet, Appendix D, for more information on reading and writing from/to this device.

Rev.: B.4

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Page 48 Pentek Model 6230/6231 Operating Manual

3.7 Master Control Register

The Master Control Register allows you to configure the Model 6230 or Model 6231 as a Master or Slave on the LVDS sync bus, toggle the on−board sync bus termination, select the source of the clock, select a clock divider, select the source and polarity of the sync, and enable the on−board oscillator. The Master Control Register is accessible only to Processor A on the VIM baseboard (or Processor C for a Model 6231 that is installed in the bottom VIM position on the baseboard).

The following table shows the contents of the Master Control Register. The subsections following the table provide descriptions of the bits and fields in the register.

Table 3−9: Master Control Register

R/W @ VIM_base+0x0020 (Proc A or C only)

D15 D14 – D10 D09 D08

Bit Name

Function

Bit Name

Function

RESET Not used SYNC SRC SYNC POL

0 = Run

1 = Reset

Write with zeros,

Mask when reading

0 = Bypass

1 = Sync Bus

0 = Negative

1 = Positive

D07 D06 D05 D04 D03 D02 D01 D00

EXT SYNC

0 = Register

1 = Ext Sync

All bits default to the logic '0' state at power on and reset

MCLK DIV1 MCLK DIV0

00 = Divide by 1 01 = Divide by 2

10 or 11 = Divide by 4

CLK SRC

SEL

0 = Bypass

1 = Sync Bus

OSC DSBL EXT CLK TERM MASTR

0 = Enable

1 = Disable

0 = Oscillator 1 = Ext Clock

0 = None

1 =

Terminat’d

0 = Slave

1 = Master

3.7.1 RESET Bit D15

This bit issues a reset to the entire Model 6230/6231 VIM module. When this bit is set to logic '1', the board is in reset. When the bit is cleared to logic '0' (its default state), the board is in a normal run state.

The Reset signal should be held for at least four times the front panel

Note

clock speed (4 x Front Panel Clock).

3.7.2 SYNC SRC Bit D09

This bit selects the source of the sync signal for the GC4016 DDRs from either the LVDS sync bus or an on−board sync. When this bit is cleared to logic '0' (its default state), the sync bus is bypassed and the sync is selected by EXT SYN EN bit D07, on the next page. When the bit is set to logic '1', the sync bus (SYNC/GATE connector, Section 2.4.3) is the source of the sync.

Rev.: B.4

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Pentek Model 6230/6231 Operating Manual Page 49

3.7 Master Control Register (continued)

3.7.3 SYNC POL Bit D08

This bit selects the polarity of the external sync signal for resetting the GC4104 DDRs. When this bit is cleared to logic '0' (its default state), a nega− tive sync resets the GC4016s. When the bit is set to logic '1', a positive sync resets the GC4016s.

3.7.4 EXT SYNC EN Bit D07

When this Model 6230/6231 is the sync bus Master (MASTR bit D00 = 1) or when the LVDS sync bus sync input is bypassed (SYNC SRC bit D09 = 0), this bit selects the sync signal for the GC4016 DDRs from either an on−board register or the external TTL sync input. When this bit is cleared to logic '0' (its default state), the register (Sync/Gate Generator Register, Section 3.13) is the source of the sync. When the bit is set to logic '1', the external TTL sync input (SYNC/GATE connectors, Section 2.4.3 or 2.4.4) is the source.

3.7.5 MCLK DIVn Bits D06 to D05

These two bits select the master clock divider when this Model 6230/6231 is a sync bus Master (MASTR bit D00 = 1). This clock divider applies to the clock selected by EXT CLK bit D02, below. The settings for these bits are:

'00' (default) - divide by 1 '01' - divide by 2 '10' or '11' - divide by 4

3.7.6 CLK SRC SEL Bit D04

This bit selects the source of the module’s clock from either the LVDS sync bus or an on−board clock source. When the bit is cleared to logic '0' (its default state), the sync bus is bypassed and the clock is selected by EXT CLK bit D02, below. When this bit is set to logic '1', the sync bus (SYNC/GATE connector, Section 2.4.3) is the source of the clock.

3.7.7 OSC DSBL Bit D03

This bit enables or disables the output from the on−board oscillator. When the bit is cleared to logic '0' (its default state), the on−board oscillator is enabled. When this bit is set to logic '1', the on−board oscillator is disabled.

Rev.: B.4

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Page 50 Pentek Model 6230/6231 Operating Manual

3.7 Master Control Register (continued)

3.7.8 EXT CLK Bit D02

When this Model 6230/6231 is a sync bus Master (MASTR bit D00 = 1) or when the sync bus clock is bypassed (CLK SRC bit D04 = 0), this bit selects the module’s clock signal from either the on−board oscillator or the external clock input. When this bit is cleared to logic '0' (its default state), the on− board oscillator is selected (for this setting, OSC DSBL bit D03, above, must be cleared to logic '0' to enable the oscillator). When the bit is set to logic '1', the external clock input is used (EXT CLK IN connector, Section 2.4.2).

3.7.9 TERM Bit D01

This bit enables termination of the sync bus by a Slave unit, or a Master unit if it is the only unit on the bus. When the bit is cleared to logic '0' (its default state), the sync bus is not terminated. When the bit is set to logic '1', the bus is terminated. The sync bus must be terminated when this Model 6230/6231 is the last (or only) Slave on the sync bus, or if it is a Master and the only unit on the bus.

3.7.10 MASTR Bit D00

This bit selects either Master or Slave on the sync bus for this Model 6230/

6231. When the bit is cleared to logic '0' (its default state), the module is a Slave. When bit is set to logic '1', the sync bus on this board is Master.

When set to a sync bus Master, this Model 6230/6231 is the source of the sync, clock, and gate signals output to the LVDS sync bus. You must select these sources using control bits EXT SYNC EN (bit D07), EXT CLK (bit D02), and EXT GATE (Section 3.10.9), and if needed, generate the sync and/or gate signals using the Sync/Gate Generator Register (Section 3.13).

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3.8 Bypass Rate Divide Register

This register sets the decimation rate of data samples written to the processor BIFO when the module is in DDR Bypass mode (see Section 4.2, Data Routing and Formats). Each processor on the VIM baseboard has its own version of this register for the BIFO associated with that processor.

The following table shows the contents of this register. The paragraph following the table provide descriptions of these bits.

Table 3−10: Bypass Rate Divide Register

R/W @ VIM_base+0x0024

D15 – D12 D11 D10 D09 D08

Bit Name

Function

Bit Name

Function

Note

Not used B11 B10 B09 B08

Write with zeros, Mask when reading 4 MSBs of 12−bit rate divider 'N−1'

D07 D06 D05 D04 D03 D02 D01 D00

B7 B6 B5 B4 B3 B2 B1 B0

8 LSBs of 12−bit rate divider 'N−1'

All bits default to the logic '0' state at power on and reset

The rate divider is a 12−bit binary value, with bit D11 the MSB. To take every Nth sample, where N is any integer value between 1 and 4096, set this register to N−1. The default value is '0x000', which is dividing by 1.

If you select ‘Channel Packing’ DDR Bypass mode (Section 4.2.3), the bypass rate dividers of both processor channels (A and B, or C and D) MUST be set at the same rate and synchronized for proper operation.

Rev.: B.4

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Page 52 Pentek Model 6230/6231 Operating Manual

3.9 Channel Enable Register

The Channel Enable Register enables the output from any of the eight receiver channels of the two GC4016s associated with a VIM baseboard processor, to a processor’s BIFO. It has no effect in DDR Bypass mode (see Section 4.2). Each processor on the VIM base− board has its own version of this register for the BIFO associated with that processor.

The following table shows the contents of this register. The paragraph following the table provide descriptions of these bits.

Table 3−11: Channel Enable Register

R/W @ VIM_base+0x0028

D15 – D08 D07 D06 D05 D04 D03 D02 D01 D00

Bit Name

Function

Not used EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

Write zeros,

Mask read

All bits default to the logic '0' state at power on and reset

0 = Disable output

1 = Enable output

Each register bit corresponds to one of the GC4016 channels for this processor. When a bit is cleared to logic '0', output from the associated GC4016 channel is disabled. When a bit is set to logic '1', the output is enabled to the associated BIFO for this channel. The following table gives the DSP/GC4016 channel assignments for each bit.

Table 3−12: Register Bit Channel Assignments

EN0 DSP CH1 EN1 DSP CH2 Channel B EN2 DSP CH3 Channel C EN3 DSP CH4 Channel D EN4 DSP CH5 EN5 DSP CH6 Channel B EN6 DSP CH7 Channel C EN7 DSP CH8 Channel D

First GC4016

Second GC4016

Channel A

When you enable any DDR channel outputs, ensure that the Graychip GC4016s

Note

Rev.: B.4

are configured accordingly, by writing control information into control registers in the GC4016s (see Section 3.23 for the Graychip Registers).

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3.10 Gate Control Register

The Gate Control Register contains several fields that select the characteristics and source of the BIFO write gates for the controlling processor. Each processor on the VIM baseboard has its own version of this register. However, only Processors A and C can set the gate polarity (GATE POL, bit D08). Each processor may use any one of the gates available (Gate A, B, C, or D) for enabling BIFO writes associated with that processor.

When the Model 6230/6231 is the sync bus Master (MASTR = 1, Master Control Regis− ter, Section 3.7.10), the board generates four gates for the LVDS sync bus: Gates A and C from Processor A (or Processor C for a Model 6231 that is installed in the bottom VIM position on the baseboard), and Gates B and D from Processor B (or Processor D). When the sync bus is bypassed (GATE SRC bit D04 = 0), the Model 6230/6231 gener− ates only Gate A and B for selection on the board. Refer to Chapter 5, Gate/Sync/Clock Description, for additional information about these gate and sync signals.

The following table shows the contents of the Gate Control Register. The subsections following the table give descriptions of the bits in this register.

Bit Name

Function

Bit Name

Function

Table 3−13: Gate Control Register

R/W @ VIM_base+0x0030

D15 – D13 D12 D11 D10 D09 D08

Not used INT EDGE D INT EDGE C INT EDGE B INT EDGE A GATE POL

Write with zeros,

Mask when reading

0 = Start

1 = End

0 = Start

1 = End

0 = Start

1 = End

0 = Start

1 = End

0 = Negative

1 = Positive

D07 D06 D05 D04 D03 D02 D01 D00

GATE SEL1 GATE SEL0 GATE DISBL GATE SRC

00 = Gate A 01 = Gate B 10 = Gate C 11 = Gate D

All bits default to the logic '0' state at power on and reset

0 = Enable

1 = Disable

0 = External

1 = Sync

Bus

TRIG

CLEAR

0 = None

1 = Force

Gate inactive

HOLD

MODE

0 = None

1 = Hold

GATE/TRIG EXT GATE

0 = Gate

1 = Trigger

0 = Register

1 = TTL

Input

3.10.1 INT EDGE x Bit D12/D11/D10/D09

Each of these four bits selects whether the start or the end of the respective gate (Gate A for INT EDGE A, etc.) creates an interrupt to the controlling processor (each gate interrupt may be independently enabled for this pro− cessor using the Interrupt Mask Register, Section 3.14). When the bit is cleared to logic '0' (its default state), the start of the gate creates an interrupt. When the bit is set to logic '1', the end of the gate creates the interrupt.

Rev.: B.4

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3.10 Gate Control Register (continued)

3.10.2 GATE POL Bit D08

This bit selects the polarity of the external TTL gate/trigger input. This bit is only available to Processors A and C (Processor A controls polarity for B; Processor C controls polarity for D). When the bit is cleared to logic '0' (its default state), BIFO writes are enabled by a negative input in Gate mode, or triggered on a negative−going edge in Trigger mode. When the bit is set to logic '1', BIFO writes are enabled by a positive input in Gate mode, or trig− gered on a positive−going edge in Trigger mode.

3.10.3 GATE SELn Bits D07 to D06

These two bits select the gate for the BIFO writes associated with this pro− cessor on the VIM baseboard. The settings for these two bits are:

'00' (default) - Gate A '01' - Gate B '10' - Gate C '11' - Gate D

3.10.4 GATE DISBL Bit D05

This bit enables or disables the selected gate (GATE SEL bits D07 to D06, above) from controlling BIFO writes for this processor. When this bit is cleared to logic '0' (its default state), the gate is enabled to control BIFO writes. When this bit is set to logic '1', the gate is disabled. When the gate is disabled, BIFO writes are defaulted to enabled; however, it does not disable the generation of interrupts from the gate signal.

3.10.5 GATE SRC Bit D04

This bit selects the source of the selected BIFO gate (GATE SEL bits D07 to D06, above) from either the LVDS sync bus or an external/on−board source. When this bit is cleared to logic '0' (its default state), the sync bus is bypassed and the BIFO gate is selected using EXT GATE bit D00, next page. When the bit is set to logic '1', the LVDS sync bus (SYNC/GATE connector,

Section 2.4.3) is the source of the gate.

3.10.6 TRIG CLEAR Bit D03

This bit forces the selected gate to the inactive state in Trigger mode (GATE/ TRIG bit D01 = 1, next page). When this bit is cleared to logic '0' (its default state), there is no effect on the gate. When the bit is set to logic '1', the gate is forced to inactive (BIFO writes disabled), regardless of the trigger length specified (Trigger Length Register, Section 3.11).

Rev.: B.4

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3.10 Gate Control Register (continued)

3.10.7 HOLD MODE Bit D02

This bit enables a gate Hold after the trigger is received in Trigger mode (GATE/TRIG bit D01 = 1, below). When the bit is cleared to logic '0' (its default state), the selected gate is active (BIFO writes enabled) for the speci− fied trigger length after the trigger (specified using the Trigger Length Reg− ister, Section 3.11), and then goes inactive (BIFO writes disabled). When the bit is set to logic '1', Hold is enabled and the gate remains active (BIFO writes enabled) after the trigger is received until this bit is cleared.

3.10.8 GATE/TRIG Bit D01

When the source of the selected BIFO gate is either an on−board register or the external TTL gate input (EXT GATE bit D00, below), this bit selects between Gate or Trigger mode for enabling BIFO writes. When the bit is cleared to logic '0' (its default state), Gate mode is selected. When the bit is set to logic '1', Trigger mode is selected, and you must set the trigger length using the Trigger Length Register, Section 3.11, or enable trigger Hold (HOLD MODE bit D02, above).

3.10.9 EXT GATE Bit D00

When the Model 6230/6231 is the sync bus Master (MASTR = 1, Master Control Register, Section 3.7.10), or when LVDS sync bus is bypassed for gate signals (GATE SRC bit D04 = 0), this bit selects the source of the designated BIFO gate either from an on−board register generator or from the external TTL gate input. When this bit is cleared to logic '0' (its default state), the on− board register (Sync/Gate Generator Register, Section 3.13) is the source of the BIFO gate. When the bit is set to logic '1', the external TTL gate input (SYNC/GATE connectors, Section 2.4.3 or 2.4.4) is the source of the gate.

See Chapter 5, Gate/Sync/Clock Description, for additional information about the use and programming of gate and sync signals.

Rev.: B.4

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Page 56 Pentek Model 6230/6231 Operating Manual

3.11 Trigger Length Register

When Trigger mode is selected for a BIFO gate (GATE/TRIG = 1, Gate Control Regis− ter, Section 3.10.8), this register sets the length that the gate is active (BIFO writes enabled) after receipt of the trigger. Each processor on the VIM baseboard has its own version of this register for the gate selected by that processor.

The following table shows the contents of this register. The paragraph following the table provide descriptions of these bits.

Table 3−14: Trigger Length Register

R/W @ VIM_base+0x0034

D15 – D14 D13 D12 D11 D10 D09 D08

Bit Name

Function

Bit Name

Function

Note

Not used D13 D12 D11 D10 D9 D8

Write with zeros,

Mask when reading

6 MSBs of 14−bit Trigger Length

D07 D06 D05 D04 D03 D02 D01 D00

D7 D6 D5 D4 D3 D2 D1 D0

8 LSBs of 14−bit Trigger Length

All bits default to the logic '0' state at power on and reset

The trigger length is a 14−bit binary value, with bit D13 the MSB. This value specifies the length of the gate after the trigger as the number of BIFO writes of the processor that generates the selected gate, up to 16,383.

If you set the Trigger Length Register and select this gate source for multiple processor channels (GATE SEL, Gate Control Register, Section 3.10.3), you must set the same data routing modes for those channels (DAT MODE, Channel Control Register, Section 3.12.4)

When in Master/Slave Mode only, there are several additional clock cycles between when the Master Gate is turned off and when the BIFO write logic is finally disabled. During that time period, depending on the Bypass Rate Divider setting (Section 3.8), several additional samples will be written into the VIM BIFO. This is unavoidable, because of the register delays in both the SYNC

Note

Rev.: B.4

bus Gate transmit and SYNC bus Gate receive logic. For any given setting of the Bypass Rate Divider, however, the number of extra clock cycles is absolutely deterministic and repeatable. One can, therefore, compensate for the extra clocks incurred due to SYNC bus delays by reducing the Trigger Length setting accordingly.

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Pentek Model 6230/6231 Operating Manual Page 57

3.12 Channel Control Register

The Channel Control Register selects the data routing mode of each processor channel, and contains bits to reset the data formatter state machine (in the associated FPGA), to enable the sync signal to reset the DDR Bypass mode decimate dividers, and to reset the processor channel. Each processor has its own version of this register, associated with that processor channel on the VIM baseboard.

The following table shows the contents of the Channel Control Register. The subsec− tions following the table provide descriptions of the bits in this register.

Table 3−15: Channel Control Register

R/W @ VIM_base+0x0038

D15 D14 − D05 D04 D03 D02 D01 D00

Bit Name

Function

RESET Not used DIV RST EN FMTR EN DAT MODE2 DAT MODE1 DAT MODE0

0 = Run

1 = Reset

All bits default to the logic '0' state at power on and reset

Write with zeros,

Mask when reading

0 = Disable

1 = Enable

0 = Disable

1 = Enable

Data Routing mode −

see Section 3.12.4

3.12.1 RESET Bit D15

This bit issues a reset to the associated processor channel (A, B, C, or D). (This does not reset the Master Control Register, Section 3.7). When the bit is set to logic '1', the processor channel is in reset. When this bit is cleared to logic '0' (its default state), the channel is in a normal run state.

3.12.2 DIV RST EN Bit D04

This bit enables the sync signal to reset the DDR Bypass mode rate dividers, to allow synchronization of all dividers. When this bit is cleared to logic '0' (its default state), this reset is not enabled. When bit is set to logic '1', the sync is enabled to reset the bypass mode rate dividers.

3.12.3 FMTR EN Bit D03

This bit enables or resets the data formatter state machine (in the associated FPGA). When this bit is cleared to logic '0' (its default state), the formatter is disabled and reset. When the bit is set to logic '1', the formatter is enabled for normal operation.

Rev.: B.4

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3.12 Channel Control Register (continued)

3.12.4 DAT MODEn Bits D02 to D00

These three bits select the data routing mode from the two GC4016 DDRs to the FPGA associated with this processor channel (for example, FPGA1 for Processor A). There are seven different modes of data formatting (these modes are described in Section 4.2). The settings for these three bits are:

'000' - Disabled (default) '001' - DDR Bypass, 14-bit data, Unpacked '010' - DDR Bypass, 14-bit data, Time Packed '011' - DDR Bypass, 14-bit data, Channel Packed (two channels) '100' - DDR Mode, 16-bit data, Unpacked I/Q and Tagged '101' - DDR Mode, 24-bit data, Unpacked I/Q and Tagged '110' - DDR Mode, 16-bit data, Packed I/Q '111' - DDR Mode, 24-bit data, Packed I/Q (drop 8 LSBs)

See Section 4.2, Data Routing and Formats, for additional information about the data formatting modes and operation of the FPGAs.

Note

When you select any data routing mode, ensure that the Graychip GC4016s are configured accordingly, by writing control information into control registers in the GC4016s (see Section 3.23 for the Graychip Registers).

The Channel Control Registers do not set up the GC4016 registers.

Rev.: B.4

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Pentek Model 6230/6231 Operating Manual Page 59

3.13 Sync/Gate Generator Register

The Sync/Gate Generator Register is used on a Model 6230/6231 that is configured as a sync bus Master (MASTR = 1, Master Control Register, Section 3.7.10), or on a board that is not connected to an external LVDS sync bus. Each processor on the VIM baseboard has its own copy of this register, associated with that processor channel.

The following table shows the contents of the Sync/Gate Generator Register. The reg− ister contains two bits that generate gate and sync signals for the associated processor channel. The subsections following the table give descriptions of these bits.

Table 3−16: Sync/Gate Generator Register

R/W @ VIM_base+0x003C

D15 − D02 D01 D00

Bit Name

Function

Not used FIFO GATE SYNC

Write with zeros,

Mask when reading

All bits default to the logic '1' state at power on and reset

0 = Enable 1 = Disable

0 = Reset

1 = Release

3.13.1 FIFO GATE Bit D01

If the gate source is set to the on−board register (EXT GATE = 0, Gate Con− trol Register, Section 3.10.9), this bit creates the gate signal (GATE A, B, C, or D) for the associated processor BIFO, and for output to the sync bus (SYNC/ GATE connector, Section 2.4.3) for a sync bus Master. When the bit is cleared to logic '0', BIFO writes are enabled. When the bit is set to logic '1' (its default state), BIFO writes are disabled.

3.13.2 SYNC Bit D00

If the sync source is set to the on−board register (EXT SYNC EN = 0, Master Control Register, Section 3.7.4), this bit creates the sync signal (SYNC) for all GC4016s, and for output to the sync bus for a sync bus Master (SYNC/ GATE connector, Section 2.4.3). The SYNC together to create the SYNC signal for the board. When the bit is cleared to logic '0', the GC4016 is in reset. When bit is set to logic '1' (its default state), the GC4016 is released for normal operation.

bits for all processors are Or’ed

Set the SYNC bit to logic '1' for all processors that are not used to create the

Note

sync signal.

Refer to Chapter 5, Gate/Sync/Clock Description, for additional information about the use and programming of gate and sync signals.

Rev.: B.4

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Page 60 Pentek Model 6230/6231 Operating Manual

3.14 Interrupt Mask Register

The Interrupt Mask Register contains one enable bit for each interrupt condition defined for the controlling processor. Each processor on the VIM baseboard has its own version of this register.

The following table shows which bit in this register is associated with each interrupt condition. Table 3−18, on the next page, provides description of the interrupt condition associated with each of these bits.

Table 3−17: Interrupt Mask Register

R/W @ VIM_base+0x0044

D15 – D13 D12 D11 D10 D09 D08

Bit Name

Function

Bit Name

Function

Not used TEMP 2 TEMP 1 VALID CLK CLK LOSS GATE D

Write with zeros,

Mask when reading

0 = Disable Interrupt

1 = Enable Interrupt

D07 D06 D05 D04 D03 D02 D01 D00

GATE C GATE B GATE A SYNC OVLD CH4 OVLD CH3 OVLD CH2 OVLD CH1

0 = Disable Interrupt

1 = Enable Interrupt

All bits default to the logic '0' state at power on and reset

Each bit of this register enables or disables the generation of the interrupt to that pro− cessor. Setting the bit associated with a given interrupt to the logic '1' state enables the generation of an interrupt to the processor when that interrupt condition occurs. When a bit is cleared to logic '0', the processor will not be interrupted by the associated inter− rupt condition.

The following two sections, Interrupt Flag Register, Section 3.15, and Status Register,

Section 3.16, contain associated functions for using these processor interrupts.

Rev.: B.4

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3.14 Interrupt Mask Register (continued)

Table 3−18: Interrupt Register Bits

Bit Name Bit Position Interrupt Function

Each of these bits is associated with a Temperature/Voltage

sensor interrupt for part of the Model 6230/6231. (There are four TEMP 2 TEMP 1

VALID CLK D10

CLK LOSS D09 This bit is associated with a Clock loss interrupt.

GATE D GATE C GATE B GATE A

SYNC D04

OVLD CH4 OVLD CH3 OVLD CH2 OVLD CH1

D12 D11

D08 D07 D06 D05

D03 D02 D01 D00

sensors on the Model 6230 [two on the Model 6231]. These are

controlled using the Hardware Monitor Port. To determine the

sensor causing the interrupt, use the Hardware Monitor Port

This bit is associated with a Valid Clock indication interrupt. The

interrupt status will go to logic '1' 16 clock cycles after detection

of a clock. It will also indicate that 16 clock cycles have occurred

since the beginning of a BIFO reset. This can be used as an

indication that the BIFO reset is complete, since a BIFO reset

requires several clock cycles to complete. The bit will remain

high during normal operation, thus it should be masked

(disabled) after it is no longer useful to prevent undesired

interrupts.

Each of these bits is associated with a Gate interrupt. The

interrupt occurs at the start or end of the respective gate signal,

depending on the setting of INT EDGE in the Gate Control

This bit is associated with a Sync interrupt. The interrupt occurs

at the start of the sync pulse.

Each of these bits is associated with an interrupt for an analog

input Overload indication from one of the A/D converters (A/D4,

A/D3, A/D2, or A/D1, respectively).

Note: These bit definitions apply to the Interrupt Mask Register, Section 3.14, Interrupt Flag

Rev.: B.4

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Page 62 Pentek Model 6230/6231 Operating Manual

3.15 Interrupt Flag Register

The Interrupt Flag Register has one read/clear bit associated with each interrupt con− dition for the VIM processor (the same bit associations as the Interrupt Mask Register,

Section 3.14). Each processor on the VIM baseboard has its own version of this register.

The following table shows which bit in this register is associated with each interrupt condition. Table 3−18, on the prior page, provides description of the interrupt condit ion associated with each of these bits.

Table 3−19: Interrupt Flag Register

R/Clr @ VIM_base+0x0048

D15 – D13 D12 D11 D10 D09 D08

Bit Name

Function

Bit Name

Function

IMPORTANT! When reset, including power−up, the state of this register is unknown.

Not used TEMP 2 TEMP 1 VALID CLK CLK LOSS GATE D

Write with zeros,

Mask when reading

Read:

Clear:

0 = No interrupt 1 = Interrupt latched 0 = Enabled to latch 1 = Clear latch

D07 D06 D05 D04 D03 D02 D01 D00

GATE C GATE B GATE A SYNC OVLD CH4 OVLD CH3 OVLD CH2 OVLD CH1

Read:

Clear:

You should clear this register before using it, by writing '1's into all bits.

0 = No interrupt 1 = Interrupt latched 0 = Enabled to latch 1 = Clear latch

Each bit of this register latches an interrupt occurrence. A logic '1' in any bit in this register indicates that an interrupt has occurred. Note that when any bit in the Status Register (Section 3.16) changes to logic '1', the corresponding bit in this register will also be set to logic '1'. However, when a bit in the Status Register changes from logic '1' to logic '0', the corresponding latched bit in this register does not clear, but remains at the logic '1' state.

Since these bits latch in response to an interrupt, to detect subsequent interrupts, you must clear the bits in this register. To clear any bit in this register that is set to the logic '1' state, you must write to that bit twice, first with a '1' to clear the bit, then with a '0' to re−enable the bit for latching.

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3.16 Interrupt Status Register

The Interrupt Status Register has one read−only bit associated with each interrupt con− dition for the VIM processor (the same bit associations as the Interrupt Mask Register,

Section 3.14). Each processor on the VIM baseboard has its own version of this register.

The following table shows which bit in this register is associated with each interrupt condition. Table 3−18, on page 61, provides description of the interrupt condition asso− ciated with each of these bits.

Table 3−20: Interrupt Status Register

RO @ VIM_base+0x004C

D15 – D13 D12 D11 D10 D09 D08

Bit Name

Function

Bit Name

Function

Not used TEMP 2 TEMP 1 VALID CLK CLK LOSS GATE D

Mask when reading

0 = No

interrupt

1 = Overtemp

0 = No

interrupt

1 = Overtemp

0 = No

interrupt

1 = Clock OK

0 = No

interrupt

1 = No Clock

0 = No

interrupt

1 = Gate

D07 D06 D05 D04 D03 D02 D01 D00

GATE C GATE B GATE A SYNC OVLD CH4 OVLD CH3 OVLD CH2 OVLD CH1

0 = No

interrupt

1 = Gate

When reset or power−up, the state of this register is unknown.

0 = No

interrupt

1 = Gate

0 = No interrupt 1 = Gate

0 = No

interrupt

1 = Sync

0 = No

interrupt

1 = Overload

0 = No

interrupt

1 = Overload

0 = No

interrupt

1 = Overload

0 = No

interrupt

1 = Overload

Each bit in this register changes whenever the associated interrupt indication changes. A bit changes to the logic '1' state whenever that interrupt occurs, and clears to logic '0' state when that interrupt clears (whereas the associated bit in the Interrupt Flag Regis− ter, Section 3.15, remains latched at logic '1' until it is cleared by that register’s clear action).

If the corresponding bit in the Interrupt Mask Register (Section 3.14) has been set to the logic '1' state, then a Status Register bit transition from logic '0' to logic '1' will also gen− erate an interrupt to the processor on the VIM baseboard. If you do not want an inter− rupt to occur and have set the corresponding interrupt mask bit to '0', you may poll this Status Register bit to determine if such an event has occurred.

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3.17 Semaphore Register

The Semaphore Register contains communications bits that may be written by one pro− cessor on the VIM baseboard and read by all four processors [two processors for the Model 6231]. This register is common to all processors on the baseboard.

The following table shows which bits are associated with each processor for writing.

Table 3−21: Semaphore Register

R/W @ VIM_base+0x0050

D15 D14 D13 D12 D11 D10 D09 D08

Bit Name

Function

D3 D2 D1 D0 C3 C2 C1 C0

Bits written by Processor D Bits written by Processor C

D07 D06 D05 D04 D03 D02 D01 D00

Bit Name

Function

* For a Model 6231 installed in the bottom VIM position, D07−D04 = Processor D, D03−D00 = Processor C.

B3 B2 B1 B0 A3 A2 A1 A0

Bits written by Processor B* Bits written by Processor A*

All bits default to the logic '0' state at power on and reset

Each processor may write only four of the bits in this register, but any processor may read all bits. These bits allow coordination between programs running in the base− board processors.

NOTE:

Bits D15 through D08 are not used on the Model 6231.

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3.18 I/O Direction 2 Register (Model 6231 only)

The I/O Direction 2 Register determines the input/output direction of each bit in the FPGA I/O Data 2 Register, Section 3.19 below. Each data bit can be individually set for input or output. This register is accessible only to Processor A on the VIM baseboard (or Processor C for a Model 6231 that is installed in the bottom VIM position on the baseboard).

Bit Name

Function

NOTE:

This register is available only on the Model 6231 with Option 102.

The following table shows which bit of this register is associated with each FPGA I/O data bit, and the paragraph following the table provides descriptions of these bits.

Table 3−22: I/O Direction 2 Register (Model 6231 Option 102 only)

R/W @ VIM_base+0x0058 (Proc A or C only)

D15 – D08 D07 D06 D05 D04 D03 D02 D01 D00

Not used DIR23 DIR22 DIR21 DIR20 DIR19 DIR18 DIR17 DIR16

Write zeros,

Mask read

All bits default to the logic '0' state at power on and reset

0 = Input bit

1 = Output bit

Refer to the connector diagram in Table 2−6, Section 2.4.5, for the pin assignments of each bit.

When a bit is cleared to logic '0' (its default state), the corresponding data bit can be input at the front panel FPGA connector (Section 2.4.5). When a bit is set to logic '1', the corresponding data bit is set for output.

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3.19 I/O Data 2 Register (Model 6231 only)

The I/O Data 2 Register allows you to read or write data from the Virtex FPGA to the front panel FPGA connector (Section 2.4.5). The direction (read or write) for each bit is controlled by the corresponding bit of the I/O Direction Register, Section 3.18 above. This register is accessible only to Processor A on the VIM baseboard (or Processor C for a Model 6231 that is installed in the bottom VIM position on the baseboard).

Bit Name

Function

NOTE:

This register is available only on the Model 6231 with Option 102.

The following table shows which bit in this register is associated with each connector data bit.

Table 3−23: I/O Data 2 Register (Model 6231 Option 102 only)

R/W @ VIM_base+0x005C (Proc A or C only)

D15 – D08 D07 D06 D05 D04 D03 D02 D01 D00

Not used

Write zeros,

Mask read

When reset or power−up, the state of this register is unknown.

FPGA I/O 23

FPGA I/O 22

Each bit can be used as data Input or Output, depending on

corresponding bit of I/O Direction 2 Register, Section 3.18

FPGA I/O 21

FPGA I/O 20

FPGA I/O 19

FPGA I/O 18

FPGA I/O 17

FPGA I/O 16

These data bits are always enabled. Refer to the connector pin diagram in Table 2−6,

Section 2.4.5, for the pin assignments of each bit.

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3.20 I/O Direction Register

The I/O Direction Register determines the input/output direction of each bit in the FPGA I/O Data Register (Section 3.22). Each data bit can be individually programmed for input or output. Processor A and Processor C on the VIM baseboard have their own version of this register, for the FPGA associated with that processor.

This register is available on the Model 6230 and only with Option 102 on the Model

6231.

The following table shows which bit of this register is associated with each FPGA I/O data bit.

Table 3−24: I/O Direction Register

R/W @ VIM_base+0x0060 (Proc A & C only)

D15 D14 D13 D12 D11 D10 D09 D08

Bit Name

Function

Bit Name

Function

DIR15 DIR14 DIR13 DIR12 DIR11 DIR10 DIR9 DIR8

0 = Input bit

1 = Output bit

D07 D06 D05 D04 D03 D02 D01 D00

DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0

0 = Input bit

1 = Output bit

All bits default to the logic '0' state at power on and reset

Refer to the connector diagram in Table 2−6, Section 2.4.5, for the pin assignments of each bit.

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3.21 I/O Enable Register

The I/O Enable Register enables connection of the I/O bits of the I/O Data Register (Section 3.22) to the front panel FPGA connector (Section 2.4.5). Processor A and Pro− cessor C on the VIM baseboard have their own version of this register, for the FPGA associated with that processor (for example, FPGA1 for Processor A).

This register is available on the Model 6230 and only with Option 102 on the Model

6231.

The following table shows the contents of the I/O Enable Register. There are two enable bits that allow you to enable either or both 8−bit halves of the 16−bit data word. The sections following the table give descriptions of the bits in this register.

Table 3−25: I/O Enable Register

R/W @ VIM_base+0x0064 (Proc A & C only)

D15 – D02 D01 D00

Bit Name

Function

Not used I/O EN1 I/O EN2

Write with zeros,

Mask when reading

All bits default to the logic '0' state at power on and reset

0 = Disable 1 = Enable

3.21.1 I/O EN1 Bit D01

On the Model 6230, this bit enables connection of I/O bits D7 through D0 of the Data Register to the front panel FPGA connector. On the Model 6231, this bit enables connection of I/O bits D15 through D0. When this bit is set to logic '1', these I/O bits of the Data Register are enabled at the front panel. When the bit is cleared to logic '0', they are disabled.

3.21.2 I/O EN2 Bit D00

On the Model 6230, this bit enables connection of I/O bits D15 through D8 of the Data Register to the front panel FPGA connector. On the Model 6231, this bit enables connection of I/O bits D23 through D16. When this bit is set to logic '1', these I/O bits of the Data Register are enabled at the front panel. When the bit is cleared to logic '0', they are disabled.

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3.22 I/O Data Register

The I/O Data Register allows you to read or write data from the Virtex FPGA to the front panel FPGA connector (Section 2.4.5). The direction (read or write) for each bit is controlled by the corresponding bit of the I/O Direction Register, Section 3.20. The data bits are enabled or disabled for connection to the front panel connector by the I/O Enable Register, Section 3.21. Processor A and Processor C on the VIM baseboard have their own version of this register, for the FPGA associated with that processor (for example, FPGA1 for Processor A).

This register is available on the Model 6230 and only with Option 102 on the Model

6231.

The following table shows which bit in this register is associated with each connector data bit.

Table 3−26: I/O Data Register

R/W @ VIM_base+0x0068 (Proc A & C only)

D15 D14 D13 D12 D11 D10 D09 D08

Bit Name

Function

Bit Name

Function

FPGAn

I/O 15

D07 D06 D05 D04 D03 D02 D01 D00

FPGAn

I/O 7

In Bit Name, ‘n’ is the FPGA number (1 or 2) associated with the processor.

When reset or power−up, the state of this register is unknown.

FPGAn

I/O 14

Each bit can be used as data Input or Output, depending on

corresponding bit of I/O Direction Register, Section 3.20

FPGAn

I/O 6

Each bit can be used as data Input or Output, depending on

corresponding bit of I/O Direction Register, Section 3.20

FPGAn

I/O 13

FPGAn

I/O 5

FPGAn

I/O 12

FPGAn

I/O 4

FPGAn

I/O 11

FPGAn

I/O 3

FPGAn

I/O 10

FPGAn

I/O 2

FPGAn

I/O 9

FPGAn

I/O 1

FPGAn

I/O 8

FPGAn

I/O 0

In the Bit Name of each bit in this table, ‘n’ is the FPGA number (for example, for Pro− cessor A, bit D15 is ‘FPGA1 I/O 15’). [For the Model 6231, there is no FPGA number.]

Refer to the connector pin diagram in Table 2−6, Section 2.4.5, for the pin assignments of each bit.

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3.23 Graychip 0 & 1 Registers

The Graychip Registers allow you to read or write data from/to each Graychip GC4016 DDR. There are eight sets of registers on the Model 6230 [four sets on the Model 6231], one for each GC4016 on the module, with 128 registers in each set. Each processor on the VIM baseboard can use two sets of registers, for the two GC4016 DDRs associated with that processor. The register addresses determines which CG4016 DDR to read/ write to — use register set ‘Graychip 0’ for the first CG4016, use register set ‘Graychip 1’ for the second CG4016. Table 3−28, at the bottom of this page, identifies the CG4016s DDRs that can be set by each processor and the register set to use for each CG4016. The following table shows the bit layout of each register of these sets. You can read or write one byte at a time to each register.

Table 3−27: Graychip 0 & 1 Registers

Graychip 0 Register Set − R/W @ VIM_base+0x0100 – 017C

D15 – D08 D07 D06 D05 D04 D03 D02 D01 D00

Bit Name

Function

Bit Name

Function

Not usedD7D6D5D4D3D2D1D0

Write zeros,

Mask read

Graychip 1 Register Set − R/W @ VIM_base+0x0180 – 01FC

Eight bits of data to/from GC4016

D15 – D08 D07 D06 D05 D04 D03 D02 D01 D00

Not usedD7D6D5D4D3D2D1D0

Write zeros,

Mask read

When reset or power−up, the state of these registers is unknown.

Eight bits of data to/from GC4016

Table 3−28: Processor/Graychip Register Sets

Processor Graychip Register Set

Processor A *

Processor B *

Processor C

Processor D

* Processor C and Processor D, respectively, for a Model 6231

installed in the bottom VIM position

GC4016 A Graychip 0 GC4016 B Graychip 1 GC4016 C Graychip 0 GC4016 D Graychip 1 GC4016 E Graychip 0 GC4016 F Graychip 1

GC4016 G Graychip 0

GC4016 H Graychip 1

Graychip GC4016 DDR library functions are provided in the ReadyFlow board support software package for the Model 6230 (Pentek part #801.62300). Refer to the Graychip GC4016 data sheet, Appendix C, for detailed information on these registers.

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Chapter 4: Data Formatting and Routing

4.1 Overview

This chapter provides descriptions of the data routing and formatting for the Model 6230/6231.

4.2 Data Routing and Formats

Each analog input channel includes an AD6645 A/D converter that can provide data to any of the GC4016 DDRs. Each FPGA is configured to accept 16 channels of serial data from four GC4016s, or A/D data directly from two AD6645s in ‘DDR Bypass’ modes. Use the Channel Control Register (Section 3.12) to select one of the seven Data Routing modes and format of the data from the FPGA to the VIM baseboard processor BIFOs.

In ‘DDR Bypass’ modes (Sections 4.2.1 to 4.2.3), each FPGA takes the A/D data directly, bypassing the GC4016 DDRs. The output is written to the VIM BIFOs at a programmed decimation rate, and may be unpacked, packed by time of arrival, or packed by channel.

In ‘DDR’ routing modes (Sections 4.2.4 to 4.2.7), each VIM BIFO can receive data from only the eight receiver channels of the two GC4016s associated with that processor (DSP CH1 = Channel A output of first GC4016 ... DSP CH8 = Channel D output of second GC4016; see also Table 3−12 on page 52). This can be expanded to 16 or more channels with additional user programming. The channels are scanned by the FPGA’s data for− matter state machine starting at the first channel. You may enable or disable any number of channels using the Channel Enable Register (Section 3.9). If you disable a channel, its data is skipped in the scan. When the gate is disabled, all BIFO writes are disabled. The data formatter state machine is reset when the gate is disabled, but will complete scan− ning through the eight receiver channels and writing them to the BIFO before stopping. All channels enabled for output to the BIFO MUST guarantee that the eight channels are from the same data sample, the GC4016 pair must be synchronized. Output with identical rates but not synchronized is possible, but the relationship between data from different channels is not known.

For ‘DDR’ modes, ensure the Graychip GC4016s are configured accordingly using the GC4016 registers (Section 3.23). The serial−to−parallel converters in the FPGAs accept the GC4016 serial data at the full clock rate, and the SCLK output from the GC4016s is not used, so the GC4016s must be set up for SERIAL output at the full clock rate. The FPGA converters expect the data from the GC4016s to be configured as one SFS pulse per I/Q pair, with the data word size either 16 or 24 bits per I or Q. You must set the mode bits in the Channel Control Register (Section 3.12) to the data word size defined for the GC4016s.

be at the same rate. Additionally, to

The ‘DDR’ modes assume that the GC4016s are set up for COMPLEX output, providing both I and Q values. If the GC4016s are configured for REAL output, data

Note

is still output from the GC4016s as two samples per channel. The value in each sample is real only and both samples are identical, however, the FPGA still marks the data as I and Q samples.

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4.2 Data Routing and Formats (continued)

4.2.1 DDR Bypass Mode, A/D Data, Unpacked (001)

This mode takes the raw 14−bit data directly from the two A/Ds, bypassing the GC4016 DDRs. The output is written to the VIM BIFO at a programmed decimation rate N, where N is 1 to 4096, only when the gate is enabled.

Each processor BIFO receives data from only one input channel: A/D 1 for Processor A, A/D 2 for Processor B, A/D 3 for Processor C, and A/D 4 for Processor D. Each sample is left justified in the 14 most significant bits in both of the 16−bit halves of the 32−bit BIFO data word. Identical data is placed in both halves of the word. Data is in the following format:

Table 4−1: Output Data Format − DDR Bypass Mode, Unpacked

Bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

Valuedddddddddddddd00

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Valuedddddddddddddd00

d = raw A/D data bit (same value in both halves of word)

4.2.2 DDR Bypass Mode, A/D Data, Time Packed (010)

This mode takes the raw 14−bit data directly from the two A/Ds, bypassing the GC4016 DDRs. The output is written to the VIM BIFO at a programmed decimation rate N/2, where N is 1 to 4096, only when the gate is enabled.

Each processor BIFO receives data from only one input channel: A/D 1 for Processor A, A/D 2 for Processor B, A/D 3 for Processor C, and A/D 4 for Processor D. Each sample is left justified in the 14 most significant bits in each of the 16−bit halves of the 32−bit BIFO data word. Data is packed with input data word data(t) in the upper half of the 32 bits, and word data(t−1) in the lower half of the 32 bits. Data is in the following format:

Table 4−2: Output Data Format − DDR Bypass Mode, Time Packed

Bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

Value

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Value

Rev.: B.4

t−1dt−1dt−1dt−1dt−1dt−1dt−1dt−1dt−1dt−1dt−1dt−1dt−1dt−1

= raw data from A/D at time (t), d

= raw data from A/D at time (t−1)

t−1

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4.2 Data Routing and Formats (continued)

4.2.3 DDR Bypass Mode, A/D Data, Channel Packed (011)

Data is packed with data from A/D 1 in the upper half of the 32−bit word, and data from A/D 2 in the lower half of the 32−bit word for processor A and B BIFOs, and with data from A/D 3 in the upper half of the 32−bit word, and data from A/D 4 in the lower half of the 32−bit word for processor C and D BIFOs. Each sample is left justified in the 14 most significant bits in each of the 16−bit halves of the 32−bit data word.

Data is in the following format:

Table 4−3: Output Data Format − DDR Bypass Mode, Channel Packed

Bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

Value

1−3d1−3d1−3d1−3d1−3d1−3d1−3d1−3d1−3d1−3d1−3d1−3d1−3d1−3

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Value

2−4d2−4d2−4d2−4d2−4d2−4d2−4d2−4d2−4d2−4d2−4d2−4d2−4d2−4

Note

= raw data from A/D 1 or A/D 3, d

1−3

You MUST set the decimation rate dividers of both processor channels (A and B, or C and D) at the same rate and synchronized for this mode to function properly!

= raw data from A/D 2 or A/D 4

2−4

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4.2 Data Routing and Formats (continued)

4.2.4 DDR Mode, 16−Bit, Unpacked I/Q, Tagged (100)

This mode expects data from the two GC4016 DDRs to be 32−bit I/Q pairs. Data is accepted and multiplexed to the VIM BIFO in a scanned manner starting with the first of the eight receiver channels. The formatter state machine is reset when the gate is disabled and always starts at the first channel when the gate is enabled. Any disabled channels are skipped. BIFO writes are disabled except when the gate is enabled.

The data is output in two consecutive 32−bit words per I/Q pair—the first word is the I data word. The FPGA inserts a DDR channel number tag in the lowest four bits of each 32−bit word. Data is in the following format:

Table 4−4: Output Data Format − DDR Mode, 16−bit, Unpacked I/Q, Tagged

Bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

ValueDDDDDDDDDDDDDDDD

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Value0 00 00 0 00 0 0T0XXXX

D = Data bit; T = I/Q tag (I = 0, Q = 1);

X = Channel # Tag (DSP CH1 = 0000 ... DSP CH8 = 0111)

NOTE:

The DDR modes assume that the GC4016s are set up for COMPLEX output (the default output), providing both I and Q values. If the GC4016s are configured for REAL output, data is still output from the GC4016s as two samples per channel. The value in each sample is real only and both samples are identical, however, the FPGA still marks the data as I and Q samples.

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4.2 Data Routing and Formats (continued)

4.2.5 DDR Mode, 24−Bit, Unpacked I/Q, Tagged (101)

This mode expects data from the two GC4016 DDRs to be 48−bit I/Q pairs. Data is accepted and multiplexed to the VIM BIFO in a scanned manner starting with the first of the eight receiver channels. The formatter state machine is reset when the gate is disabled and always starts at the first channel when the gate is enabled. Any disabled channels are skipped. BIFO writes are disabled except when the gate is enabled.

Table 4−5: Output Data Format − DDR Mode, 24−bit, Unpacked I/Q, Tagged

Bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

ValueDDDDDDDDDDDDDDDD

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

ValueDDDDDDDD0 0 T 0 XXXX

D = Data bit; T = I/Q tag (I = 0, Q = 1);

X = Channel # Tag (DSP CH1 = 0000 ... DSP CH8 = 0111)

NOTE:

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4.2 Data Routing and Formats (continued)

4.2.6 DDR Mode, 16−Bit, Packed I/Q (110)

This mode expects data from the two GC4016 DDRs to be 32−bit I/Q pairs. Data is accepted and multiplexed to the VIM BIFO in a scanned manner starting with the first of the eight receiver channels. The formatter state machine is reset when the gate is disabled and starts always at the first channel when the gate is enabled. Any disabled channels are skipped. BIFO writes are disabled except when the gate is enabled.

The output data format is a 16−bit I and a 16−bit Q data value packed into a 32−bit word. Since there are no unused bits, data is not tagged for channel identification, but guaranteed to begin with the first enabled channel once gate is enabled. The user must then know which channels are skipped because they are disabled to determine what channel data belongs to.

Data is in the following format:

Table 4−6: Output Data Format − DDR Mode, 16−bit, Packed I/Q

Bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

ValueIIIIIIIIIIIIIIII

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

ValueQQQQQQQQQQQQQQQQ

I = I sample data bit; Q = Q sample data bit

GC4016−formatted tagging can be done in this mode by configuring the GC4016 registers—however, if GC4016 tagging is used, the least significant four bits of each value, D3 to D0 and D16 to D19, will not be available as data bits.

NOTE:

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4.2 Data Routing and Formats (continued)

4.2.7 DDR Mode, 24−Bit, Packed I/Q (111)

This mode expects data from the two GC4016 DDRs to be 48−bit I/Q pairs. Data is multiplexed to the VIM BIFO in a scanned manner starting with the first of the eight receiver channels. The formatter state machine is reset when the gate is disabled and always starts at the first channel when the gate is enabled. Any disabled channels are skipped. BIFO writes are dis− abled except when the gate is enabled. Also, in this mode, the lowest deci− mation rates cannot be reached because the minimum clocks between samples are 48 instead of 32.

The output data format is a 16−bit I and a 16−bit Q data value packed into a 32−bit word, where the 16 bits are the most significant 16 of the 24−bit input words. Since there are no unused bits, data is not tagged for channel identi− fication, but guaranteed to begin with the first enabled channel once the gate is enabled. The user must then know which channels are skipped because they are disabled to determine what channel data belongs to.

Data is in the following format:

Table 4−7: Output Data Format − DDR Mode, 16−bit, Packed I/Q

Bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

ValueIIIIIIIIIIIIIIII

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

ValueQQQQQQQQQQQQQQQQ

I = I sample data bit; Q = Q sample data bit

No tagging can be done in this format.

NOTE:

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Chapter 5: Timing and Synchronization

5.1 Overview

This chapter provides descriptions of the timing and synchronization of the module processing. The Model 6230/6231 provides four gates, one sync, and one clock. These signals go out on the LVDS sync bus if the board is a bus Master, or come in on the LVDS sync bus for a bus Slave unit. The Model 6230/6231 may, alternately, bypass the sync bus and use its own gate, sync, or clock sources for timing and control.

See Figures 5−1 and 5−2, below and on the next page, for logic diagrams of these timing signals.

GATES

A−D

Front Panel

SYNC Bus

MCLK

SYNC

GATE SRC

LVDS

Receiver

LVDS Driver

MASTR

Master Contr ol, D0

Gate Control, D4

CLK SRC

Master Control, D4

SYNC SRC

Master Control, D9

Gate/Trigger

Master Clock

Virtex−E FPGA (2)

Circuit

Divider

CLK IN

SYNC

AD6644

A/Ds (4)

GC4016

DDRs (8)

EXT SYNC EN

Master Contr ol, D7

Gate Control , D0

Master Contr ol, D2

EXT GATE

EXT CLK

ENABLE

CLK IN A

FIFO

CLK IN B

Quad Processor Board

GATE A A)(Processor

GATE B B)(Processor

GATE C C)(Processor

GATE D D)(Processor

Figure 5−1: Model 6230 Gate/Sync/Clock Logic

Gate Input Select

ENABLE

CLK IN C

FIFO

Sync/Gate Gen, D0

SYNC A (Proc A) SYNC B B)(Proc SYNC C C)(Proc SYNC D D)(Proc

Sync/Gate Gen, D1

64 MHz

Oscillator

ENABLE

FIFO

ENABLE

CLK IN D

FIFO

EXT TTL SYNC IN

EXT TTL GATE/TRIG IN

Front Panel Connectors

EXT CLK IN

Rev.: B.4

Page 80

Page 80 Pentek Model 6230/6231 Operating Manual

5.1 Overview (continued)

GATES C,D

GATES A,B

Front Panel

SYNC Bus

MCLK

SYNC

GATE SRC

Gate Control, D4

LVDS

Receiver

LVDS Driver

CLK SRC

Master Control, D4

SYNC SRC

Master Control, D9

Gate/Trigger

Virtex−E

FPGA

Circuit

(C & D)

(A & B)

CLK IN

SYNC

AD6644 A/Ds (2)

GC4016 DDRs (4)

EXT SYNC EN

Master Contr ol, D7

EXT GATE

Gate Control , D0

Gate Input Select

ENABLE ENABLE

CLK IN (A or C)

FIFO

CLK IN (B or D)

FIFO

Quad Processor Board

Sync/ Gate Gen , D0

SYNC A (Proc A or C)

SYNC B (Proc B or D)

Sync/ Gate Gen , D1

GATE A (Proc A or C)

GATE B (Proc B or D)

EXT TTL SYNC IN

EXT TTL GATE/TRG IN

Front Panel

MASTR

Master Contr ol, D0

Master Clock

Divider

EXT CLK

Master Contr ol, D2

64 MHz

Oscillator

Connectors

EXT CLK IN

5.2 Sync

The sync signal is used for data synchronization by the CG4016 DDRs. The sync can be driven either from the front panel LVDS sync bus or from an external TTL sync input (Sections 2.4.3 and 2.4.4), or a sync signal can be generated by a register write by each processor (Section 3.13). When the Model 6230/6231 is a sync bus Master, the gener− ated sync is output to the LVDS Sync Bus.

5.3 Clock

The clock for all the board functions can be driven from either the front panel LVDS sync bus or an external clock input (Section 2.4.2), or a clock can be generated using the on−board 64−MHz oscillator (Section 3.7.7). When the Model 6230/6231 is a sync bus Master, the on−board clock is output to the LVDS Sync Bus.

Figure 5−2: Model 6231 Gate/Sync/Clock Logic

Rev.: B.4

Page 81

Pentek Model 6230/6231 Operating Manual Page 81

5.4 Gates

The four gates are used to enable writes to the VIM baseboard BIFOs. Each gate can be driven either from the front panel LVDS sync bus or from an external TTL gate input (Sections 2.4.3 and 2.4.4), or each gate may be generated from a register write by each processor (Section 3.13). Any receiver channel may use any one of the four gate sources as its gate, but each gate is generated by an individual processor channel on a sync bus Master board.

Gates may be disabled on a channel−by−channel basis, in which case BIFO writes are always enabled. The polarity of the external gate source is programmable. All gate features are programmable on a channel−by−channel basis, except external gate polar− ity, which is selectable from Processor A only and is global (Section 3.10). Gate transi− tions from high to low or low to high can programmably create interrupts on any processor.

When the Model 6230/6231 is a sync bus Master, the generated gates are output to the LVDS Sync Bus. When the Model 6231 is a Master, the board generates four gates for the LVDS sync bus: Gates A and C from Processor A (or Processor C for a Model 6231 that is installed in the bottom VIM position on the baseboard), and Gates B and D from Processor B (or Processor D for a 6231 in the bottom VIM position).

The external TTL gate or the register write gate may be programmed to act as a trigger (Trigger mode). In this case, the gate is generated after a desired polarity logic transi− tion on the external gate source or register write, and the resulting gate continues either indefinitely (Hold mode) or for a programmed number of BIFO writes up to 16,383 (Trigger Length). At any time the triggered gate may be asynchronously disabled by a control register write.

Rev.: B.4

Page 82

Page 82 Pentek Model 6230/6231 Operating Manual

This page is intentionally blank

Rev.: B.4

Page 83

Pentek Model 6230/6231 Operating Manual Page A−1

Appendix A: Configuration EEPROM Format

A.1 Introduction

All VIM Modules contain an Identification (ID) EEPROM with a checksum stored in the last location. When booted, each VIM baseboard processor checks for the presence of a VIM module, through the presence bit on the VIM connector. If a module is present, the processor reads the module’s ID EEPROM and generates a 16−bit checksum from the data read. If the generated checksum does not match the stored value, the proces− sor illuminates its red LED. Even though the processor illuminates LED 0, the red LED, the processor is fully functional.

The contents of the ID EEPROM, plus the calculated checksum, are stored in Global SDRAM on the VIM baseboard. Refer to the respective VIM baseboard Operating Man− ual for the location of the Global SDRAM. The first word stored is a valid data flag, based on the checksum: valid checksum ( no VIM module installed (

0xFFFF FFFE).

0x00EE C0DE), bad checksum (0x000B ADC5), or

The ID EEPROM is accessed using a Model 6230/6231 register at memory address VIM_base+0x0000, as offset from the VIM base address defined for the applicable VIM baseboard. The bit layout of this register is defined in Table A−1, below.

Table A−1: VIM ID EEPROM Register

R/W @ VIM_base+0x0000

Bit # D31 − D4 D3 D2 D1 D0

Bit Name Not Used Chip Select Serial Data Out Reserved Serial Clock

Access Read/Write Read/Write Read Only Read Only Read/Write

Function Not Applicable

1 = Selected 0 = Not Selected

Stored Data

Mask when

reading

Toggle to pulse

Clock line

A.2 EEPROM Format Example

Table A−2 on the next page shows the contents of the ID EEPROM for the Model 6230,

and an explanation of what each pair of 16−bit words is used for. The SDRAM location is the address where each pair of words is stored relative to the start address of the Global SDRAM on the VIM baseboard.

Rev. B.4

Page 84

Page A−2 Pentek Model 6230/6231 Operating Manual

A.2 EEPROM Format Example (continued)

Table A−2: EEPROM Example (Model 6230 shown)

EEPROM

Word Location

00/01 +0x00 0x00EE C0DE Valid data flag 02/03 +0x04 0x6230 0000 Model, Model Extension (Extension currently unused) 04/05 +0x08 0x0354 2001 PCB number − this is taken from the VIM board

06/07 +0x0C 0x0001 FFFF

08/09 +0x10 0xFFFF FFFF Option #2, Option #3 10/11 +0x14 0xFFFF FFFF Option #4, Option #5 12/13 +0x18 0xFFFF FFFF Option #6, Option #7 14/15 +0x1C 0xFFFF FFFF Option #8, Option #9

16/17 +0x20 0xFFFF FFFF

18/19 +0x24 0xFFFF FFFF

20/21 +0x28 0xFFFF FFFF

22/23 +0x2C 0xFFFF FFFF

24/25 +0x30 0xFFFF FFFF

26/27 +0x34 0xFFFF FFFF

28/29 +0x38 0xFFFF FFFF

30/31 +0x3C 0xFFFF FFFF

32/33 +0x40 0xFFFF FFFF

34/35 +0x44 0xFFFF FFFF

36/37 +0x48 0xFFFF FFFF

38/39 +0x4C 0xFFFF FFFF

40/41 +0x50 0xFFFF FFFF

42/43 +0x54 0xFFFF FFFF

44/45 +0x58 0xFFFF FFFF

46/47 +0x5C 0xFFFF FFFF

48/49 +0x60 0xFFFF FFFF

50/51 +0x64 0xFFFF FFFF

52/53 +0x68 0xFFFF FFFF

54/55 +0x6C 0xFFFF FFFF

56/57 +0x70 0xFFFF FFFF

58/59 +0x74 0xFFFF FFFF

60/61 +0x78 0xFFFF FFFF

62/63 +0x7C 0x0000 xxxx

SDRAM

Location

Contents Comments

Assembly Rev, Option #1

Rev A = 0001, Rev B = 0002, etc.; Option #1 − up to 9 installed options may be specified, if there are no options, field = 'FFFF'

Module−specific code goes in locations 16 through 61

Word 62 should always be cleared (0000). Word 63 contains the checksum of words 0 − 61.

Rev. B.4

Page 85

Pentek Model 6230/6231 Operating Manual Page B−1

Appendix B: Analog Devices AD6644 A/D Converter

B.1 Introduction

The following pages are a reprint of the Analog Devices AD6644 14−Bit, 65 MHz A/D Converter data sheet.

Rev.: B.4

Page 86

Page B−2 Pentek Model 6230/6231 Operating Manual

This page is intentionally blank

Rev.: B.4

Page 87

14-Bit, 40 MSPS/65 MSPS

FEATURES 65 MSPS Guaranteed Sample Rate 40 MSPS Version Available Sampling Jitter < 300 fs 100 dB Multitone SFDR

1.3 W Power Dissipation Differential Analog Inputs Digital Outputs

Two’s Complement Format

3.3 V CMOS-Compatible Data Ready for Output Latching

APPLICATIONS Multichannel, Multimode Receivers AMPS, IS-136, CDMA, GSM, Third Generation Single Channel Digital Receivers Antenna Array Processing Communications Instrumentation Radar, Infrared Imaging Instrumentation

PRODUCT DESCRIPTION

The AD6644 is a high-speed, high-performance, monolithic 14-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference, are included onchip to provide a complete conversion solution. The AD6644 provides CMOS-compatible digital outputs. It is the third generation in a wideband ADC family, preceded by the AD9042 (12-bit 41 MSPS) and the AD6640 (12-bit 65 MSPS, IF sampling.)

A/D Converter

AD6644

Designed for multichannel, multimode receivers, the AD6644 is part of ADI’s new SoftCell™ transceiver chipset. The AD6644 achieves 100 dB multitone, spurious-free dynamic range (SFDR) through the Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) which are typically limited by the ADC. Noise performance is exceptional; typical signal-to-noise ratio is 74 dB.

The AD6644 is also useful in single channel digital receivers designed for use in wide-channel bandwidth systems (CDMA, W-CDMA). With oversampling, harmonics can be placed outside the analysis bandwidth. Oversampling also facilitates the use of decimation receivers (such as the AD6620), allowing the noise floor in the analysis bandwidth to be reduced. By replacing traditional analog filters with predictable digital components, modern receivers can be built using fewer “RF” components, resulting in decreased manufacturing costs, higher manufacturing yields, and improved reliability.

The AD6644 is built on Analog Devices’ high-speed complementary bipolar process (XFCB) and uses an innovative, multipass circuit architecture. Units are packaged in a 52-terminal LowProfile Quad Plastic Flatpack (LQFP) specified from –25°C to +85°C.

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate is 65 MSPS.

2. Fully differential analog input stage.

3. Digital outputs may be run on 3.3 V supply for easy interface to digital ASICs.

4. Complete Solution: reference and track-and-hold.

5. Packaged in small, surface-mount, plastic, 52-terminal LQFP.

AVCCDV

AIN

2.4V

REF

ENCODE

SoftCell is a trademark of Analog Devices, Inc.

INTERNAL

TIMING

GND D8D9D10D11D12D13DRYOVRDMID D0D1D2D3D4D5D6D7

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

TH2TH1A1

ADC1 DAC1

MSB LSB

TH3

DIGITAL ERROR CORRECTION LOGIC

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000

TH4

ADC2 DAC2

TH5

ADC3

AD6644

Page 88

AD6644–SPECIFICATIONS

DC SPECIFICATIONS

Parameter Temp Level Min Typ Max Min Typ Max Unit

RESOLUTION 14 14 Bits

ACCURACY

No Missing Codes Full II Guaranteed Guaranteed Offset Error Full II –10 3 +10 –10 3 +10 mV Gain Error Full II –10 –6 +10 –10 –6 +10 % FS Differential Nonlinearity (DNL) Full II –1.0 ±0.25 +1.5 –1.0 ± 0.25 +1.5 LSB Integral Nonlinearity (INL) Full V ± 0.50 ± 0.50 LSB

TEMPERATURE DRIFT

Offset Error Full V 10 10 ppm/°C Gain Error Full V 95 95 ppm/°C

POWER SUPPLY REJECTION (PSRR) Full V ± 1.0 ±1.0 mV/V

REFERENCE OUT (V ANALOG INPUTS (AIN, AIN)

Differential Input Voltage Range Full V 2.2 2.2 V p-p Differential Input Resistance Full V 1 1 kΩ Differential Input Capacitance 25°C V 1.5 1.5 pF

POWER SUPPLY

Supply Voltage

Supply Current

(AVCC = 5.0 V) Full II 245 276 245 276 mA

VCC

(DVCC = 3.3 V) Full II 30 36 30 36 mA

VCC

POWER CONSUMPTION Full II 1.3 1.5 1.3 1.5 W

NOTES

AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V.

Specifications subject to change without notice.

REF

(AVCC = 5 V, DVCC = 3.3 V; T

Test AD6644AST-40 AD6644AST-65

) Full V 2.4 2.4 V

Full II 4.85 5.0 5.25 4.85 5.0 5.25 V Full II 3.0 3.3 3.6 3.0 3.3 3.6 V

= –25ⴗC, T

MIN

= +85ⴗC)

MAX

DIGITAL SPECIFICATIONS

Parameter Temp Level Min Typ Max Min Typ Max Unit

ENCODE INPUTS (ENC, ENC)

Differential Input Voltage Differential Input Resistance 25°C V 10 10 kΩ Differential Input Capacitance 25°C V 2.5 2.5 pF

LOGIC OUTPUTS (D13–D0, DRY, OVR)

Logic Compatibility CMOS CMOS Logic “1” Voltage Logic “0” Voltage Output Coding Two’s Complement Two’s Complement DMID Full V DVCC/2 DVCC/2 V

NOTES

All ac specifications tested by driving ENCODE and ENCODE differentially. Reference Figure 22 for performance versus encode power.

Digital output logic levels: DVCC = 3.3 V, C

Specifications subject to change without notice.

SWITCHING SPECIFICATIONS

Parameter Temp Level Min Typ Max Min Typ Max Unit

Maximum Conversion Rate Full II 40 65 MSPS Minimum Conversion Rate Full IV 15 15 MSPS ENCODE Pulsewidth High Full IV 10 6.5 ns ENCODE Pulsewidth Low Full IV 10 6.5 ns

Specifications subject to change without notice.

(AVCC = 5 V, DVCC = 3.3 V; T

Test AD6644AST-40 AD6644AST-65

Full IV 0.4 0.4 V p-p

Full V 2.5 2.5 V Full V 0.4 0.4 V

= 10 pF. Capacitive loads >10 pF will degrade performance.

LOAD

= –25ⴗC, T

MIN

= +85ⴗC)

MAX

(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; T –25ⴗC, T

= +85ⴗC)

MAX

Test AD6644AST-40 AD6644AST-65

MIN

–2–

REV. 0

Page 89

AD6644

AC SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; T

Test AD6644AST-40 AD6644AST-65

Parameter Temp Level Min Typ Max Min Typ Max Unit

SNR

Analog Input 2.2 MHz 25°C II 74.5 72 74.5 dB @ –1 dBFS 15.5 MHz 25°C II 74.0 72 74.0 dB

30.5 MHz 25°C II 73.5 72 73.5 dB

SINAD

Analog Input 2.2 MHz 25°C II 74.5 72 74.5 dB @ –1 dBFS 15.5 MHz 25°C II 74.0 72 74.0 dB

30.5 MHz 25°C V 73.0 73.0 dB

WORST HARMONIC

(2ND

or 3RD)

Analog Input 2.2 MHz 25°CII 92 83 92 dBc @ –1 dBFS 15.5 MHz 25°CII 90 83 90 dBc

30.5 MHz 25°C V 85 85 dBc

WORST HARMONIC (4

or Higher)

Analog Input 2.2 MHz 25°CII 93 85 93 dBc @ –1 dBFS 15.5 MHz 25°CII 92 85 92 dBc

30.5 MHz 25°C V 92 92 dBc

TWO-TONE SFDR2,

TWO-TONE IMD REJECTION

3, 4

Full V 100 100 dBFS

2, 4

F1, F2 @ –7 dBFS Full V 90 90 dBc

ANALOG INPUT BANDWIDTH 25°C V 250 250 MHz

NOTES

All ac specifications tested by driving ENCODE and ENCODE differentially.

AVCC = 5 V to 5.25 V for rated ac performance.

Analog input signal power swept from –7 dBFS to –100 dBFS.

F1 = 15 MHz, F2 = 15.5 MHz.

Specifications subject to change without notice.

= –25ⴗC, T

MIN

= +85ⴗC)

MAX

SWITCHING SPECIFICATIONS

(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; T –25ⴗC, T

= +85ⴗC, C

MAX

LOAD

= 10 pF)

MIN

Test AD6644AST-40/65

Parameter Name Temp Level Min Typ Max Unit

ENCODE INPUT PARAMETERS

Encode Period1 @ 65 MSPS t Encode Period Encode Pulsewidth High

@ 40 MSPS t

Encode Pulsewidth Low @ 65 MSPS t

@ 65 MSPS t

ENC

ENCH

ENCL

Full V 15.4 ns Full V 25 ns Full IV 6.2 7.7 9.2 ns Full IV 6.2 7.7 9.2 ns

ENCODE/DATA READY

Encode Rising to Data Ready Falling t Encode Rising to Data Ready Rising t

E_DR

Full IV 2.6 3.4 4.6 ns

+ t

ENCH

@ 65 MSPS (50% Duty Cycle) Full IV 10.3 11.1 12.3 ns @ 40 MSPS (50% Duty Cycle) Full IV 15.1 15.9 17.1 ns

ENCODE/DATA (D13:0), OVR

ENC to DATA Falling Low t ENC to DATA Rising Low t ENCODE to DATA Delay (Hold Time) ENCODE to DATA Delay (Setup Time)

E_FL

E_RL

H_E

S_E

Full IV 3.8 5.5 9.2 ns Full IV 3.0 4.3 6.4 ns Full IV 3.0 4.3 6.4 ns

– t

ENC

E_FL

Encode = 65 MSPS (50% Duty Cycle) Full IV 6.2 9.8 11.6 ns Encode = 40 MSPS (50% Duty Cycle) Full IV 15.9 19.4 21.2 ns

REV. 0

–3–

Page 90

AD6644–SPECIFICATIONS

Test AD6644AST-40/65

Parameter Name Temp Level Min Typ Max Unit

DATA READY (DRY

Data Ready to DATA Delay (Hold Time)

Encode = 65 MSPS (50% Duty Cycle) Full IV 8.0 8.6 9.4 ns Encode = 40 MSPS (50% Duty Cycle) Full IV 12.8 13.4 14.2 ns

Data Ready to DATA Delay (Setup Time)

@ 65 MSPS (50% Duty Cycle) Full IV 3.2 5.5 6.5 ns @ 40 MSPS (50% Duty Cycle) Full IV 8.0 10.3 11.3 ns

APERTURE DELAY t

APERTURE UNCERTAINTY (JITTER) t

NOTES

Several timing parameters are a function of t

To compensate for a change in duty cycle for t

Newt

= (t

H_DR

Newt

ENCODE to DATA Delay (Hold Time) is the absolute minimum propagation delay through the analog-to-digital converter.

ENCODE to DATA Delay (Setup Time) is calculated relative to 65 MSPS (50% duty cycle). In order to calculate t

Newt

DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.

Data Ready to DATA Delay(t and t

Newt Newt

Specifications subject to change without notice.

H_DR

= (t

S_DR

= t

S_E

ENC(NEW)

for a given encode use the following equations:

S_DR

= t

H_DR

ENC(NEW)

= t

S_DR

ENC(NEW)

)/DATA, OVR

– % Change(t

– t

+ t

ENC

/2 – t

ENCH

/2 – t

ENCH

and t

ENC

)) × t

ENCH

)) × t

ENCH

(i.e., for 40 MSPS: Newt

S_E

and t

H_DR

+ t

H_DR

+ t

S_DR

H_DR

ENC

/2.

ENC

) is calculated relative to 65 MSPS (50% duty cycle) and is dependent on t

S_DR

(i.e., for 40 MSPS: Newt (i.e., for 40 MSPS: Newt

and t

H_DR

S_DR

ENCH

use the following equation:

S_DR

= 25 × 10–9 – 15.38 × 10–9 + 9.8 × 10–9 = 19.4 × 10 –9).

S_E(TYP)

= 12.5 × 10–9 – 7.69 × 10–9 + 8.6 × 10–9 = 13.4 × 10

H_DR(TYP)

= 12.5 × 10–9 – 7.69 × 10–9 + 5.5 × 10–9 = 10.3 × 10–9.

S_DR(TYP)

Note 6

25°C V 100 ps

25°C V 0.2 ps rms

for a given encode use the following equation:

S_E

and duty cycle. In order to calculate t

ENC

–9

H_DR

AIN

ENC, ENC

D[13:0], OVR

DRY

Nⴙ3

Nⴙ1

Nⴙ2

E_FL

E_RL

ENC

N–3

ENCH

Nⴙ1

ENCL

N–2

Nⴙ2Nⴙ3Nⴙ4

E_DR

N–1

S_DR

H_DR

S_E

Nⴙ4

H_E

Figure 1. Timing Diagram

–4–

REV. 0

Page 91

AD6644

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS Test Level

Parameter Min Max Unit

ELECTRICAL

Voltage 0 7 V

Analog Input Voltage 0 AV

V Analog Input Current 25 mA Digital Input Voltage 0 AV

V Digital Output Current 4 mA

ENVIRONMENTAL

I 100% production tested. II 100% production tested at 25°C, and guaranteed by

design and characterization at temperature extremes. III Sample tested only. IV Parameter is guaranteed by design and characterization

testing. V Parameter is a typical value only.

Operating Temperature Range

(Ambient) –25 +85 °C Maximum Junction Temperature 150 °C Lead Temperature (Soldering, 10 sec) 300 °C Storage Temperature Range (Ambient) –65 +150 °C

NOTES

Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.

Typical thermal impedances (52-terminal LQFP); θJA = 33°C/W; θJC = 11°C/W. These measurements were taken on a 6 layer board in still air with a solid ground plane.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD6644AST-40 –25°C to +85°C (Ambient) 52-Terminal LQFP (Low-Profile Quad Plastic Flatpack) ST-52 AD6644AST-65 –25°C to +85°C (Ambient) 52-Terminal LQFP (Low-Profile Quad Plastic Flatpack) ST-52 AD6644ST/PCB Evaluation Board with AD6644AST–65

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6644 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

Page 92

AD6644

PIN FUNCTION DESCRIPTIONS

Pin No. Name Function

1, 33, 43 DV

2, 4, 7, 10, 13, 15, 17, 19, 21, 23, GND Ground. 25, 27, 29, 34, 42

REF

5 ENCODE Encode Input; conversion initiated on rising edge. 6 ENCODE Complement of ENCODE; differential input. 8, 9, 14, 16, 18, 22, 26, 28, 30 AV

11 AIN Analog Input. 12 AIN Complement of AIN; Differential Analog Input. 20 C1 Internal Voltage Reference; bypass to ground with 0.1 µF microwave

24 C2 Internal Voltage Reference; bypass to ground with 0.1 µF microwave

31 DNC Do not connect this pin. 32 OVR Overrange Bit; high indicates analog input exceeds ± FS. 35 DMID Output Data Voltage Midpoint; approximately equal to (DVCC)/2. 36 D0 (LSB) Digital Output Bit (Least Significant Bit); Two’s Complement 37–41, 44–50 D1–D5, D6–D12 Digital Output Bits in Two’s Complement. 51 D13 (MSB) Digital Output Bit (Most Significant Bit); Two’s Complement. 52 DRY Data Ready Output.

3.3 V Power Supply (Digital) Output Stage Only.

2.4 V (Analog Reference). Bypass to ground with 0.1 µF microwave chip capacitor.

5 V Analog Power Supply.

chip capacitor.

GND V

REF

GND

ENCODE

GND

AIN

GND

PIN CONFIGURATION

D10

D11

D12

D13 (MSB)

DRY

PIN 1 IDENTIFIER

14 151617 18

GND

AD6644

TOP VIEW

(Not to Scale)

19 20 21 22 23 24 25 26

DNC = DO NOT CONNECT

GND

40414243444546474849505152

D3 D2

D1 D0 (LSB)

DMID

GND DV

OVR

DNC AV

GND AV

GND

–6–

REV. 0

Page 93

AD6644

DEFINITIONS OF SPECIFICATIONS Analog Bandwidth

The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. The difference is then computed between both peak measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Encode Pulsewidth/Duty Cycle

Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing t

in text. At a given clock rate, these specs define

ENCH

an acceptable ENCODE duty cycle.

Full-Scale Input Power

Expressed in dBm. Computed using the following equation:

Power

Harmonic Distortion, 2nd

Full Scale

log



    

Full Scalerms

0 001

Input

     

The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.

Harmonic Distortion, 3rd

The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least-square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels.

Noise (For Any Range Within the ADC)

=××

NOISE

|| .–0 001 10



FS Signal

dBm dBFS

 

 



Where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value for the particular input level and Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in power supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc.

Signal-to-Noise Ratio (Without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or dBFS (always related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale).

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the 2nd and 3rd harmonic) reported in dBc.

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AD6644

EQUIVALENT CIRCUITS

AIN

500⍀

AIN

Figure 2. Analog Input Stage

10k⍀

ENCODE

10k⍀

LOADS

BUF

10k⍀

CURRENT

MIRROR

T/H

REF

CURRENT

MIRROR

REF

D0–D13, OVR, DRY

Figure 5. Digital Output Stage

ENCODE

2.4V

100␮A

REF

LOADS

Figure 3. ENCODE Inputs

REF

CURRENT

MIRROR

C1 OR C2

Figure 4. Compensation Pin, C1 or C2

Figure 6. 2.4 V Reference

10k⍀

DMID

Figure 7. DMID Reference

–8–

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Typical Performance Characteristics–

AD6644

ENCODE = 65MSPS

–10

AIN = 2.2MHz @ –1dBFS SNR = 74.5dB

–20

SFDR = 92dBc

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

5 101520

FREQUENCY – MHz

Figure 8. Single Tone at 2.2 MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

5 101520

FREQUENCY – MHz

ENCODE = 65MSPS AIN = 15.5MHz @ –1dBFS SNR = 74dB SFDR = 90dBc

Figure 9. Single Tone at 15.5 MHz

25 30

75.0

ENCODE = 65MSPS, AIN = –1dBFS

SNR – dB

74.5

74.0

73.5

73.0

72.5

72.0

TEMP = –25

T = ⴙ85 C

5 10 152025

FREQUENCY – MHz

C, ⴙ25 C, ⴙ85 C

T = –25 C

T = ⴙ25 C

Figure 11. Noise vs. Analog Frequency (Nyquist)

WORST-CASE HARMONIC – dBc

T = ⴚ25 C, ⴙ85 C

510152025

ENCODE = 65MSPS, AIN = –1dBFS

TEMP = ⴚ25

ANALOG INPUT FREQUENCY – MHz

C, ⴙ25 C, ⴙ85 C

T = ⴙ25 C

Figure 12. Harmonics vs. Analog Frequency (Nyquist)

ENCODE = 65MSPS

–10

AIN = 30MHz @ –1dBFS SNR = 73.5dB

–20

SFDR = 85dBc

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

5 101520

FREQUENCY – MHz

Figure 10. Single Tone at 30 MHz

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25 30

–9–

PHASE NOISE OF ANALOG SOURCE

SNR – dB

DEGRADES PERFORMANCE

10 20 50 70 80

LOW NOISE ANALOG SOURCE

AIN = –1dBFS ENCODE = 65MSPS

30 40 60 90 ANALOG FREQUENCY – MHz

Figure 13. Noise vs. Analog Frequency (IF)

100

Page 96

AD6644

100

WORST OTHER SPUR

HARMONICS – dBc

HARMONICS (2nd, 3rd)

10 20 50 70 80

30 40 60 90

ANALOG FREQUENCY – MHz

ENCODE = 65MSPS AIN = –1dBFS

100

Figure 14. Harmonics vs. Analog Frequency (IF)

120

110

100

ENCODE = 65MSPS

AIN = 15.5MHz

WORST-CASE SPURIOUS – dBFS and dBc

–70

–80 0

–60 –50 –30

ANALOG INPUT POWER LEVEL – dBFS

–40

dBFS

dBc

SFDR = 90dB REFERENCE LINE

–20 –10

Figure 15. Single Tone SFDR

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

5 101520

FREQUENCY – MHz

ENCODE = 65MSPS AIN = 15MHz,

15.5MHz @ –7dBFS NO DITHER

25 30

Figure 17. Two Tones at 15 MHz and 15.5 MHz

110

100

ENCODE = 65MSPS

F1 = 15MHz

F2 = 15.5MHz

WORST-CASE SPURIOUS – dBFS and dBc

–67 –27 –17

–77

dBc

SFDR = 90dB REFERENCE LINE

–57 –47 –37

INPUT POWER LEVEL – (F1 = F2) dBFS

dBFS

–7

Figure 18. Two-Tone SFDR

ENCODE = 65MSPS

–10

AIN = 19MHz,

19.5MHz @ –7dBFS

–20

NO DITHER

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

5 101520

FREQUENCY – MHz

Figure 16. Two Tones at 19 MHz and 19.5 MHz

25 30

–10–

100

SNR, WORST SPURIOUS – dB and dBc

WORST SPUR

10 60 70

20 40 50

30 80 90

ENCODE FREQUENCY – MHz

AIN = 2.2MHz @ –1dBFS

SNR

Figure 19. SNR, Worst Spurious vs. Encode

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AD6644

ENCODE = 65MSPS

–10

AIN = 15.5MHz @ –29.5dBFS NO DITHER

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

0 5 10 15 20

FREQUENCY – MHz

25 30

Figure 20. 1M FFT Without Dither

100

ENCODE = 65MSPS

AIN = 15.5MHz NO DITHER

WORST-CASE SPURIOUS – dBc

–90 0

–80 –30 –10

–60 –20

–70 –50 –40

ANALOG INPUT POWER LEVEL – dBFS

SFDR = 90dB REFERENCE LINE

Figure 21. SFDR Without Dither

ENCODE = 65MSPS

–10

AIN = 15.5MHz @ –29.5dBFS DITHER @ –19dBm

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

5 101520

Figure 23. 1M FFT with Dither

100

ENCODE = 65MSPS

AIN = 15.5MHz DITHER = –19dBm

WORST-CASE SPURIOUS – dBc

–80 –30 –10

–90

Figure 24. SFDR with Dither

FREQUENCY – MHz

SFDR = 90dB REFERENCE LINE

–60 –20

–70 –50 –40

ANALOG INPUT POWER LEVEL – dBFS

25 30

SFDR = 100dB REFERENCE LINE

WORST SPUR

SNR, WORST SPURIOUS – dB and dBc

65 –15.0

30.5MHz

–10.0

ENCODE INPUT POWER – dBm

2.2MHz

30.5MHz

–5.0 10.0

Figure 22. SNR, Worst Spurious vs. Clamped Encode Power (See Figure 25)

REV. 0

ENCODE = 65MSPS

SNR

5.0

15.0

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Page 98

AD6644

THEORY OF OPERATION

The AD6644 analog-to-digital converter (ADC) employs a three stage subrange architecture. This design approach achieves the required accuracy and speed while maintaining low power and small die size.

As shown in the functional block diagram, the AD6644 has complementary analog input pins, AIN and AIN . Each analog input is centered at 2.4 V and should swing ± 0.55 V around this reference (Figure 2). Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.2 V peakto-peak.

Both analog inputs are buffered prior to the first track-and-hold, TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives a 5-bit digitalto-analog converter, DAC1. DAC1 requires 14 bits of precision which is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1.

The first residue signal is applied to a second conversion stage consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The second DAC requires 10 bits of precision which is met by the process with no trim. The input to TH5 is a second residue signal generated by subtracting the quantized output of DAC2 from the first residue signal held by TH4. TH5 drives a final 6-bit ADC3.

The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS-compatible word, coded as two's complement.

APPLYING THE AD6644 Encoding the AD6644

The AD6644 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz input signals when using a high-jitter clock source. See Analog Devices’ Application Note AN-501, “Aperture Uncertainty and ADC System Performance” for complete details.

For optimum performance, the AD6644 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias.

Shown below is one preferred method for clocking the AD6644. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD6644 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD6644, and limits the noise presented to the ENCODE inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limiting resistor (typically 100 Ω) is placed in the series with the primary.

CLOCK

SOURCE

0.1␮F

100⍀

T1–4T

HSMS2812

DIODES

ENCODE

AD6644

ENCODE

Figure 25. Crystal Clock Oscillator – Differential Encode

If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown below. A device that offers excellent jitter performance is the MC100LVEL16 (or same family) from Motorola.

ECL/

PECL

0.1␮F

ENCODE

AD6644

ENCODE

Figure 26. Differential ECL for Encode

Analog Input

As with most new high-speed, high dynamic range analog-todigital converters, the analog input to the AD6644 is differential. Differential inputs allow much improvement in performance on-chip as signals are processed through the analog stages. Most of the improvement is a result of differential analog stages having high rejection of even order harmonics. There are also benefits at the PCB level. First, differential inputs have high commonmode rejection to stray signals such as ground and power noise. Also, they provide good rejection to common-mode signals such as local oscillator feedthrough.

The AD6644 input voltage range is offset from ground by 2.4 V. Each analog input connects through a 500 Ω resistor to a 2.4 V bias voltage and to the input of a differential buffer (Figure 2). The resistor network on the input properly biases the followers for maximum linearity and range. Therefore, the analog source driving the AD6644 should be ac-coupled to the input pins. Since the differential input impedance of the AD6644 is 1 kΩ, the analog input power requirement is only –2 dBm, simplifying the driver amplifier in many cases. To take full advantage of this high-input impedance, a 20:1 transformer would be required. This is a large ratio and could result in unsatisfactory performance. In this case, a lower step-up ratio could be used. The recommended method for driving the analog input of the AD6644 is to use a 4:1 RF transformer. For example, if R

were set to 60.4 Ω and RS were set

to 25 Ω, along with a 4:1 transformer, the input would match to a 50 Ω source with a full-scale drive of 4.8 dBm. Series resistors (R

) on the secondary side of the transformer should be

used to isolate the transformer from A/D. This will limit the amount of dynamic current from the A/D flowing back into the secondary of the transformer. The terminating resistor (RT) should be placed on the primary side of the transformer.

ANALOG INPUT

SIGNAL

T1–4T

0.1␮F

AIN

AD6644

AIN

–12–

Figure 27. Transformer-Coupled Analog Input Circuit

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AD6644

JITTER – ps

SNR – dB

0.1

0.2 0.3 0.4 0.5 0.6

AIN = 190MHz

AIN = 150MHz

AIN = 110MHz

AIN = 30MHz

AIN = 70MHz

In applications where dc-coupling is required, a new differential output op amp from Analog Devices, the AD8138, can be used to drive the AD6644 (Figure 28). The AD8138 op amp provides single-ended-to-differential conversion, which reduces overall system cost and minimizes layout requirements.

499⍀

25⍀

AD8138

25⍀

499⍀

0.1␮F

499⍀

OCM

Figure 28. DC-Coupled Analog Input Circuit

Power Supplies

Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that may be “received” by the AD6644. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 µF chip capacitors.

The AD6644 has separate digital and analog power supply pins. The analog supplies are denoted AV pins are denoted DV

. AVCC and DV

power supplies. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that AV fied for DV

must be held within 5% of 5 V. The AD6644 is speci-

= 3.3 V as this is a common supply for digital ASICs.

Output Loading

Care must be taken when designing the data receivers for the AD6644. It is recommended that the digital outputs drive a series resistor (e.g. 100 Ω) followed by a gate like 74LCX574. To minimize capacitive loading, there should only be one gate on each output pin. An example of this is shown in the evaluation board schematic shown in Figure 30. The digital outputs of the AD6644 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace will have a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF ⫻ 1 V ⫼ 1 ns) of dynamic current per bit will flow in or out of the device. A full scale transition can cause up to 140 mA (14 bits ⫻ 10 mA/bit) of current to flow through the output stages. The series resistors should be placed as close to the AD6644 as possible to limit the amount of current that can flow into the output stage. These switching currents are confined between ground and the DV

pin. Standard TTL gates should be avoided since

they can appreciably add to the dynamic switching currents of the AD6644. It should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. Digital output timing is guaranteed with 10 pF loads.

Layout Information

The schematic of the evaluation board (Figure 30) represents a

typical implementation of the AD6644. A multilayer board is recommended to achieve the best results. It is highly recommended that high-quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. The pinout of the AD6644 facilitates ease of use in the implementa-

REV. 0

AIN

AD6644

AIN

REF

DIGITAL OUTPUTS

and the digital supply

should be separate

tion of high frequency, high resolution design practices. All of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes.

Care should be taken when routing the digital output traces. To prevent coupling through the digital outputs into the analog portion of the AD6644, minimal capacitive loading should be placed on these outputs. It is recommended that a fan-out of only one gate be used for all AD6644 digital outputs.

The layout of the Encode circuit is equally critical. Any noise received on this circuitry will result in corruption in the digitization process and lower overall performance. The Encode clock must be isolated from the digital outputs and the analog inputs.

Jitter Considerations

The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter.





()

– log

SNR f t

=×

ANALOG

J RMS





()

+×× × +





ANALOG RMS

= analog input frequency.

= rms jitter of the encode (rms sum of encode



 

NOISE RMS

 



 

(1)

 

source and internal encode circuitry).

ε = average DNL of the ADC (typically 0.41 LSB).

N = Number of bits in the ADC.

NOISE RMS

= V rms thermal noise referred to the analog input

of the ADC (typically 2.5 LSB).

For a 14-bit analog-to-digital converter like the AD6644, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrates the expected SNR performance of the AD6644 as jitter increases. The chart is derived from the above equation.

For a complete discussion of aperture jitter, please consult Analog Devices’ Application Note AN-501, “Aperture Uncertainty and ADC System Performance.”

Figure 29. SNR vs. Jitter

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AD6644

EVALUATION BOARD

The evaluation board for the AD6644 is straightforward, containing all required circuitry for evaluating the device. The only external connections required are power supplies, clock, and the analog inputs. The evaluation board includes the option for an onboard clock oscillator for ENCODE.

Power to the analog supply pins of the AD6644 is connected via the power terminal block (PCTB2). Power for the digital interface is supplied via pin 1 of J6. The J2 connector mates directly with SoftCell boards, allowing complete evaluation of system performance.

The analog input is connected via a BNC connector AIN, which is transformer-coupled to the AD6644 inputs. The transformer has a turns ratio of 1:4 to reduce the amount of input power required to drive the AD6644.

Item Quantity Reference Description

1 2 C1, C2 Tantalum Chip Capacitor 10 µF 2 19 C3, C7, C8, C9, C10, C11, C16, C30, C31, Ceramic Chip Capacitor 0508, 0.1 µF

3 8 C12, C13, C14, C17, C18, C19, C20, C21 Ceramic Chip Capacitor 0508, 0.01 µF 4 1 CR1 HSMS2812 Surface Mount Diode 5 1 E3, E4, E5 3-Pin Header 6 4 F1, F2, F3, F4 Ferrite (Optional) 7 2 J1, J6 PCTB2 8 1 J2 50-Pin Double Row Header 9 1 J3 SMA Connector 10 2 J4, J5 BNC Connector 11 1 R1 Surface-Mount Resistor 1206, 100 Ω 12 1 R2 Surface-Mount Resistor 1206, 60.4 Ω 13 4 R3, R4, R5, R8 Surface-Mount Resistor 0805, 499 Ω (Optional,

14 2 R6, R7 Surface-Mount Resistor 0805, 25 Ω 15 1 R9 Surface-Mount Resistor 0805, 348 Ω 16 1 R10 Surface-Mount Resistor 0805, 615 Ω 17 1 R35 Surface-Mount Resistor 0805, 49.9 Ω 18 30 R36, R37, R38, R39, R40, R41, R42, R43, Surface-Mount Resistor 0402, 100 Ω

19 2 T2, T3 Surface-Mount Transformer Mini-Circuits T4–1, 1:4 Ratio 20 1 U1 AD6644AST 14-Bit 65 MSPS A/D Converter 21 2 U2, U7 74LCX574 Octal Latch 22 1 U3 AD8138 Single-to-Differential Amplifier (Optional – DC

23 2 U4, U6 NC7SZ32 Two Input OR Gate 24 1 U5 CTS Reeves Full-Size MX045 Crystal Clock Oscillator

Receive Signal Processor (AD6620, AD6624) evaluation

AD6644ST/PCB Bill of Material

C32, C4, C22, C23, C24, C25, C26, C27, C28, C29

R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65

The Encode signal may be generated using an onboard crystal oscillator, U5. The on-board oscillator may be replaced by an external encode source via the SMA connector labeled OPT_CLK or BNC connector labeled ENCODE. If an external source is used, it must be a high-quality and very low-phase noise source.

The AD6644 output data is latched using 74LCX574 (U7, U2) latches. The clock for these latches is determined by selecting jumper E3–E4 or E4–E5. E3 to E5 is a just a gate delayed version of the clock, while connecting E4 to E5 utilizes the Data Ready of the AD6644 to latch the output data. A clock is also distributed with the output data (J2) that is labeled BUFLAT (Pin 19 and 20, J2).

DC-Coupling Only)

Coupling Only)

–14–

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