NCP1030
NCP1030, NCP1031
Low Power PWM Controller with On-Chip Power Switch and Startup Circuits for 48 V Telecom Systems
The NCP1030 and NCP1031 are a family of miniature high−voltage monolithic switching regulators with on−chip Power Switch and Startup Circuits. The NCP103x family incorporates in a single IC all the active power, control logic and protection circuitry required to implement, with minimal external components, several switching regulator applications, such as a secondary side bias supply or a low power dc−dc converter. This controller family is ideally suited for 48 V telecom, 42 V automotive and 12 V input applications. The NCP103x can be configured in any single−ended topology such as forward or flyback. The NCP1030 is targeted for applications requiring up to 3 W, and the NCP1031 is targeted for applications requiring up to 6 W.
The internal error amplifier allows the NCP103x family to be easily configured for secondary or primary side regulation operation in isolated and non−isolated configurations. The fixed frequency oscillator is optimized for operation up to 1 MHz and is capable of external frequency synchronization, providing additional design flexibility. In addition, the NCP103x incorporates individual line undervoltage and overvoltage detectors, cycle by cycle current limit and thermal shutdown to protect the controller under fault conditions. The preset current limit thresholds eliminate the need for external sensing components.
Features
•On Chip High 200 V Power Switch Circuit and Startup Circuit
•Internal Startup Regulator with Auxiliary Winding Override
•Operation up to 1 MHz
•External Frequency Synchronization Capability
•Frequency Fold−down Under Fault Conditions
•Trimmed ± 2% Internal Reference
•Line Undervoltage and Overvoltage Detectors
•Cycle by Cycle Current Limit Using SENSEFET
•Active LEB Circuit
•Overtemperature Protection
•Internal Error Amplifier
Typical Applications
•Secondary Side Bias Supply for Isolated dc−dc Converters
•Stand Alone Low Power dc−dc Converter
•Low Power Bias Supply
•Low Power Boost Converter
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MARKING |
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DIAGRAMS |
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8 |
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8 |
Micro8 |
1030 |
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DM SUFFIX |
AYW |
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1 |
CASE 846A |
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1 |
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SO−8 |
8 |
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N1031 |
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8 |
D SUFFIX |
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CASE 751 |
ALYW |
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1 |
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1 |
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1030/N1031 = Specific Device Code |
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A |
= Assembly Location |
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L |
= Wafer Lot |
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Y |
= Year |
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W |
= Work Week |
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PIN CONNECTIONS |
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1 |
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8 |
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GND |
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VDRAIN |
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2 |
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7 |
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CT |
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VCC |
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3 |
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6 |
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VFB |
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UV |
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4 |
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5 |
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COMP |
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OV |
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(Top View) |
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ORDERING INFORMATION |
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Device |
Package |
Shipping² |
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NCP1030DMR2 |
Micro8 |
4000/Tape & Reel |
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NCP1031DR2 |
SO−8 |
2500/Tape & Reel |
²For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2004 |
1 |
Publication Order Number: |
August, 2004 − Rev. 4 |
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NCP1030/D |
NCP1030, NCP1031
GND
Internal Bias
I1
CT
10 V
I2 = 3I1
Error Amplifier
VFB
−
+
10 V +
− 2.5 V
COMP
2 k |
10 V |
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RSENSE |
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Current Limit |
LEB |
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Comparator |
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− |
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CT Ramp |
+ |
+ |
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− 50 mV |
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3.0 V/3.5 V −
I |
One Shot |
O |
S |
Reset Q |
Pulse |
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Dominant |
− |
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R |
Latch |
+ |
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PWM Latch |
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PWM Comparator |
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4.5 V |
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Disable |
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+ |
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ISTART |
7.5 V/10 V |
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− |
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Thermal |
+ |
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16 V |
Shutdown |
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− |
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Reset S |
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+ |
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Q Dominant |
10 V− |
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Latch |
− |
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R |
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+ |
+ |
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− 6.5 V |
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− |
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+ |
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+ |
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10 V |
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− 2.5 V |
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− |
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+ |
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10 V |
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VDRAIN
VCC
UV
OV
Figure 1. NCP1030/31 Functional Block Diagram
FUNCTIONAL PIN DESCRIPTION
Pin |
Name |
Function |
Description |
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1 |
GND |
Ground |
Ground reference pin for the circuit. |
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2 |
CT |
Oscillator Frequency |
An external capacitor connected to this pin sets the oscillator frequency up to 1 MHz. |
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Selection |
The oscillator can be synchronized to a higher frequency by charging or discharging |
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CT to trip the internal 3.0 V/3.5 V comparator. If a fault condition exists, the power |
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switch is disabled and the frequency is reduced by a factor of 7. |
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3 |
VFB |
Feedback Input |
The regulated voltage is scaled down to 2.5 V by means of a resistor divider. |
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Regulation is achieved by comparing the scaled voltage to an internal 2.5 V reference. |
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4 |
COMP |
Error Amplifier Compensation |
Requires external compensation network between COMP and VFB pins. This pin is |
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effectively grounded if faults are present. |
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5 |
OV |
Line Overvoltage Shutdown |
Line voltage (Vin) is scaled down using an external resistor divider such that the OV |
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voltage reaches 2.5 V when line voltage reaches its maximum operating voltage. |
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6 |
UV |
Line Undervoltage Shutdown |
Line voltage is scaled down using an external resistor divider such that the UV |
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voltage reaches 2.5 V when line voltage reaches its minimum operating voltage. |
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7 |
VCC |
Supply Voltage |
This pin is connected to an external capacitor for energy storage. During Turn−On, the |
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startup circuit sources current to charge the capacitor connected to this pin. When the |
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supply voltage reaches VCC(on), the startup circuit turns OFF and the power switch is |
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enabled if no faults are present. An external winding is used to supply power after |
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initial startup to reduce power dissipation. VCC should not exceed 16 V. |
8 |
VDRAIN |
Power Switch and |
This pin directly connects the Power Switch and Startup Circuits to one of the |
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Startup Circuits |
transformer windings. The internal High Voltage Power Switch Circuit is connected |
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between this pin and ground. VDRAIN should not exceed 200 V. |
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NCP1030, NCP1031 |
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CT Ramp |
COMP Voltage |
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CT Charge |
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Signal |
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PWM |
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Comparator |
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Output |
Current Limit |
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Propagation Delay |
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PWM Latch |
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Output |
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Power Switch |
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Circuit Gate Drive |
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Leading Edge |
Current Limit |
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Threshold |
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Blanking Output |
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Normal PWM Operating Range |
Output Overload |
Figure 2. Pulse Width Modulation Timing Diagram
VCC(on)
VCC(off)
VCC(reset)
0 V
ISTART
0 mA
3.0 V
VUV
0 V
2.5 V
VFB
0 V
VDRAIN
0 V
Power−up & |
Normal Operation |
Output Overload |
standby Operation |
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Figure 3. Auxiliary Winding Operation with Output Overload Timing Diagram
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NCP1030, NCP1031
MAXIMUM RATINGS
Rating |
Symbol |
Value |
Unit |
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Power Switch and Startup Circuits Voltage |
VDRAIN |
−0.3 to 200 |
V |
Power Switch and Startup Circuits Input Current |
IDRAIN |
1.0 |
A |
− NCP1030 |
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− NCP1031 |
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2.0 |
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VCC Voltage Range |
VCC |
−0.3 to 16 |
V |
All Other Inputs/Outputs Voltage Range |
VIO |
−0.3 to 10 |
V |
VCC and All Other Inputs/Outputs Current |
IIO |
100 |
mA |
Operating Junction Temperature |
TJ |
−40 to 125 |
°C |
Storage Temperature |
Tstg |
−55 to 150 |
°C |
Power Dissipation (TJ = 25°C, 2.0 Oz., 1.0 Sq Inch Printed Circuit Copper Clad) |
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0.69 |
W |
DM Suffix, Plastic Package Case 846A |
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D Suffix, Plastic Package Case 751 |
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0.93 |
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Thermal Resistance, Junction to Air (2.0 Oz. Printed Circuit Copper Clad) |
R JA |
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°C/W |
DM Suffix, Plastic Package Case 846A |
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181 |
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0.36 Sq. Inch |
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1.0 Sq. Inch |
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162 |
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D Suffix, Plastic Package Case 751 |
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135 |
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0.36 Sq. Inch |
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1.0 Sq. Inch |
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117 |
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Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
A.This device contains ESD protection circuitry and exceeds the following tests: Pins 1−7: Human Body Model 2000V per MIL−STD−883, Method 3015.
Machine Model Method 200 V.
Pin 8 is connected to the High Voltage Startup and Power Switch Circuits and rated only to the maximum voltage rating of the part, or 200 V.
B.This device contains Latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1030, NCP1031
DC ELECTRICAL CHARACTERISTICS (VDRAIN = 48 V, VCC = 12 V, CT = 560 pF, VUV = 3 V, VOV = 2 V, VFB = 2.3 V, VCOMP = 2.5 V, TJ = −40 °C to 125°C, typical values shown are for TJ = 25°C unless otherwise noted.) (Note 1)
Characteristics |
Symbol |
Min |
Typ |
Max |
Unit |
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STARTUP CONTROL |
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Startup Circuit Output Current (VFB = VCOMP) |
ISTART |
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mA |
NCP1030 |
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TJ = 25°C |
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VCC = 0 V |
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10 |
12.5 |
15 |
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VCC = VCC(on) − 0.2 V |
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6.0 |
8.6 |
12 |
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TJ = −40 °C to 125°C |
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8.0 |
− |
16 |
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VCC = 0 V |
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2.0 |
− |
13 |
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VCC = VCC(on) − 0.2 V |
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NCP1031 |
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TJ = 25°C |
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VCC = 0 V |
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13 |
16 |
19 |
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VCC = VCC(on) − 0.2 V |
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8.0 |
12 |
16 |
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TJ = −40 °C to 125°C |
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VCC = 0 V |
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11 |
− |
21 |
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VCC = VCC(on) − 0.2 V |
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4.0 |
− |
18 |
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VCC Supply Monitor (VFB = 2.7 V) |
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V |
Startup Threshold Voltage (VCC Increasing) |
VCC(on) |
9.6 |
10.2 |
10.6 |
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Minimum Operating VCC After Turn−on (V CC Increasing) |
VCC(off) |
7.0 |
7.6 |
8.0 |
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Hysteresis Voltage |
VCC(hys) |
− |
2.6 |
− |
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Undervoltage Lockout Threshold Voltage, VCC Decreasing (VFB = VCOMP) |
VCC(reset) |
6.0 |
6.6 |
7.0 |
V |
Minimum Startup Voltage (Pin 8) |
VSTART(min) |
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V |
ISTART = 0.5 mA, VCC =VCC(on) − 0.2 V |
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− |
16.8 |
18.5 |
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ERROR AMPLIFIER |
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Reference Voltage (VCOMP = VFB, Follower Mode) |
VREF |
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V |
TJ = 25°C |
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2.45 |
2.5 |
2.55 |
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TJ = −40 °C to 125°C |
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2.40 |
2.5 |
2.60 |
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Line Regulation (VCC = 8 V to 16 V, TJ = 25°C) |
REGLINE |
− |
1.0 |
5.0 |
mV |
Input Bias Current (VFB = 2.3 V) |
IVFB |
− |
0.1 |
1.0 |
A |
COMP Source Current |
ISRC |
80 |
110 |
140 |
A |
COMP Sink Current (VFB = 2.7 V) |
ISNK |
200 |
550 |
900 |
A |
COMP Maximum Voltage (ISRC = 0 A) |
VC(max) |
4.5 |
− |
− |
V |
COMP Minimum Voltage (ISNK = 0 A, VFB = 2.7 V) |
VC(min) |
− |
− |
1.0 |
V |
Open Loop Voltage Gain |
AVOL |
− |
80 |
− |
dB |
Gain Bandwidth Product |
GBW |
− |
1.0 |
− |
MHz |
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LINE UNDER/OVERVOLTAGE DETECTOR |
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Undervoltage Lockout (VFB = VCOMP) |
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Voltage Threshold (Vin Increasing) |
VUV |
2.400 |
2.550 |
2.700 |
V |
Voltage Hysteresis |
VUV(hys) |
0.075 |
0.175 |
0.275 |
V |
Input Bias Current |
IUV |
− |
0 |
1.0 |
A |
Overvoltage Lockout (VFB = VCOMP) |
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Voltage Threshold (Vin Increasing) |
VOV |
2.400 |
2.550 |
2.700 |
V |
Voltage Hysteresis |
VOV(hys) |
0.075 |
0.175 |
0.275 |
V |
Input Bias Current |
IOV |
− |
0 |
1.0 |
A |
1. Production testing for NCP1030DMR2 is performed at 25°C only; limits at −40 °C and 125°C are guaranteed by design.
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NCP1030, NCP1031
DC ELECTRICAL CHARACTERISTICS (VDRAIN = 48 V, VCC = 12 V, CT = 560 pF, VUV = 3 V, VOV = 2 V, VFB = 2.3 V, VCOMP = 2.5 V, TJ = −40 °C to 125°C, typical values shown are for TJ = 25°C unless otherwise noted.) (Note 2)
Characteristics |
Symbol |
Min |
Typ |
Max |
Unit |
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OSCILLATOR |
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Frequency (CT = 560 pF, Note 3) |
fOSC1 |
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kHz |
TJ = 25°C |
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275 |
300 |
325 |
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TJ = −40 °C to 125°C |
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260 |
− |
325 |
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Frequency (CT = 100 pF) |
fOSC2 |
− |
800 |
− |
kHz |
Charge Current (VCT = 3.25 V) |
ICT(C) |
− |
215 |
− |
A |
Discharge Current (VCT = 3.25 V) |
ICT(D) |
− |
645 |
− |
A |
Oscillator Ramp |
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V |
Peak |
Vrpk |
− |
3.5 |
− |
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Valley |
Vrvly |
− |
3.0 |
− |
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PWM COMPARATOR |
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Maximum Duty Cycle |
DCMAX |
70 |
75 |
80 |
% |
POWER SWITCH CIRCUIT |
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Power Switch Circuit On−State Resistance (I D = 100 mA) |
RDS(on) |
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NCP1030 |
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TJ = 25°C |
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− |
4.1 |
7.0 |
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TJ = 125°C |
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− |
6.0 |
12 |
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NCP1031 |
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TJ = 25°C |
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− |
2.1 |
3.0 |
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TJ = 125°C |
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− |
3.5 |
6.0 |
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Power Switch Circuit and Startup Circuit Breakdown Voltage |
V(BR)DS |
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V |
(ID = 100 A, TJ = 25°C) |
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200 |
− |
− |
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Power Switch Circuit and Startup Circuit Off−State Leakage Current |
IDS(off) |
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A |
(VDRAIN = 200 V, VUV = 2.0 V) |
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TJ = 25°C |
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− |
13 |
25 |
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TJ = −40 to 125 °C |
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− |
− |
50 |
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Switching Characteristics (VDS = 48 V, RL = 100 ) |
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ns |
Rise Time |
tr |
− |
22 |
− |
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Fall Time |
tf |
− |
24 |
− |
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CURRENT LIMIT AND OVER TEMPERATURE PROTECTION |
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Current Limit Threshold (TJ = 25°C) |
ILIM |
350 |
515 |
680 |
mA |
NCP1030 (di/dt = 0.5 A/ s) |
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NCP1031 (di/dt = 1.0 A/ s) |
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700 |
1050 |
1360 |
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Propagation Delay, Current Limit Threshold to Power Switch Circuit Output |
tPLH |
− |
100 |
− |
ns |
(Leading Edge Blanking plus Current Limit Delay) |
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Thermal Protection (Note 4) |
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°C |
Shutdown Threshold (TJ Increasing) |
TSHDN |
125 |
150 |
− |
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Hysteresis |
THYS |
− |
45 |
− |
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TOTAL DEVICE |
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Supply Current After UV Turn−On |
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mA |
Power Switch Enabled |
ICC1 |
2.0 |
3.0 |
4.0 |
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Power Switch Disabled |
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Non−Fault condition (V FB = 2.7 V) |
ICC2 |
− |
1.5 |
2.0 |
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Fault Condition (VFB = 2.7 V, VUV = 2.0 V) |
ICC3 |
− |
0.65 |
1.2 |
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2.Production testing for NCP1030DMR2 is performed at 25°C only; limits at −40 °C and 125°C are guaranteed by design.
3.Oscillator frequency can be externally synchronized to the maximum frequency of the device.
4.Guaranteed by design only.
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