ON Semiconductor NBC12430, NBC12430A Technical data

NBC12430

NBC12430, NBC12430A

3.3V/5V Programmable PLL

Synthesized Clock

Generator

50 MHz to 800 MHz

The NBC12430 and NBC12430A are general purpose, PLL based synthesized clock sources. The VCO will operate over a frequency range of 400 MHz to 800 MHz. The VCO frequency is sent to the N−output divider, where it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. Output frequency steps of 250 KHz, 500 KHz, 1.0 MHz, 2.0 MHz can be achieved using a 16 MHz crystal, depending on the output dividers settings. The PLL loop filter is fully integrated and does not require any external components.

•Best−in−Class Output Jitter Performance, ±20 ps Peak−to−Peak

•50 MHz to 800 MHz Programmable Differential PECL Outputs

•Fully Integrated Phase−Lock−Loop with Internal Loop Filter

•Parallel Interface for Programming Counter and Output Dividers During Powerup

•Minimal Frequency Overshoot

•Serial 3−Wire Programming Interface

•Crystal Oscillator Interface

•Operating Range: VCC = 3.135 V to 5.25 V

•CMOS and TTL Compatible Control Inputs

•Pin and Function Compatible with Motorola MC12430 and MPC9230

•0°C to 70°C Ambient Operating Temperature (NBC12430)

•−40 °C to 85°C Ambient Operating Temperature (NBC12430A)

•Pb−Free Packages are Available*

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MARKING

DIAGRAMS

1 28

NBC12430x

AWLYYWW

PLCC−28

FN SUFFIX

CASE 776

		NBC12430x
	LQFP−32	AWLYYWW
	FA SUFFIX	32
	CASE 873A
		1

x = Blank or A

A = Assembly Location WL = Wafer Lot

YY = Year

WW = Work Week

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2004	1	Publication Order Number:
December, 2004 − Rev. 5		NBC12430/D

			NBC12430, NBC12430A
						+3.3 or 5.0 V
							1
			1 MHz FREF				PLL_VCC
			with
		16	16 MHz Crystal	PHASE
			DETECTOR						+3.3 or 5.0 V
	3
XTAL_SEL
					VCO			21, 25
	2
FREF_EXT								VCC
	4		9−BIT M				N	24	FOUT
		XTAL1		2				23
			COUNTER		400−800	(1, 2, 4, 8)			FOUT
10−20MHz		OSC			MHz
	5							20	TEST
		XTAL2
				LATCH			LATCH
	6
OE
	28
S_LOAD
								LATCH
	7
P_LOAD
			0	1		0	1
S_DATA	27		9−BIT SR		2−BIT SR			3−BIT SR
S_CLOCK	26
			8 → 16				17, 18	22, 19
				9			2
				M[8:0]			N[1:0]

Figure 1. Block Diagram (PLCC−28)

Table 1. Output Division

N [1:0]	Output Division
0 0	2
0 1	4
1 0	8
1 1	1

Table 2. XTAL_SEL And OE

Input	0	1
XTAL_SEL	FREF_EXT	XTAL
OE	Outputs Disabled	Outputs Enabled

	V	F		F	GND	V	TEST	GND				V	F		F	GND	V	V	TEST	GND
	CC	OUT		OUT		CC						CC	OUT		OUT		CC	CC
	25	24	23		22	21	20	19
S_CLOCK	26							18	N[1]		32		31	30		29	28	27	26	25
S_DATA	27							17	N[0]	S_CLOCK										24		N/C
												1
										S_DATA										23		N[1]
S_LOAD	28							16	M[8]
												2
										S_LOAD		3								22		N[0]
PLL_VCC	1							15	M[7] PLL_VCC			4								21		M[8]
FREF_EXT	2							14	M[6]	PLL_VCC		5								20		M[7]
										FREF_EXT		6								19		M[6]
XTAL_SEL
	3							13	M[5] XTAL_SEL			7								18		M[5]
XTAL1	4							12	M[4]	XTAL1		8								17		M[4]
											9		10	11		12	13	14	15	16
	5	6	7		8	9	10	11
	XTAL2	OE		P LOAD	M[0]	M[1]	M[2]	M[3]				XTAL2	OE		P LOAD	M[0]	M[1]	M[2]	M[3]	N/C
	Figure 2. 28−Lead PLCC (Top View)										Figure 3. 32−Lead LQFP (Top View)

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NBC12430, NBC12430A

The following gives a brief description of the functionality of the NBC12430 and NBC12430A Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable of driving two series terminated 50 transmission lines on the incident edge.

PIN FUNCTION DESCRIPTION

	Pin Name				Function	Description
INPUTS
	XTAL1, XTAL2				Crystal Inputs	These pins form an oscillator when connected to an external series−resonant
						crystal.
	S_LOAD*				CMOS/TTL Serial Latch Input	This pin loads the configuration latches with the contents of the shift registers. The
					(Internal Pulldown Resistor)	latches will be transparent when this signal is HIGH; thus, the data must be stable
						on the HIGH−to−LOW transition of S_LOAD for proper operation.
	S_DATA*				CMOS/TTL Serial Data Input	This pin acts as the data input to the serial configuration shift registers.
					(Internal Pulldown Resistor)
	S_CLOCK*				CMOS/TTL Serial Clock Input	This pin serves to clock the serial configuration shift registers. Data from S_DATA
					(Internal Pulldown Resistor)	is sampled on the rising edge.
					CMOS/TTL Parallel Latch Input	This pin loads the configuration latches with the contents of the parallel inputs
	P_LOAD**
					(Internal Pullup Resistor)	.The latches will be transparent when this signal is LOW; therefore, the parallel
								for proper opera-
						data must be stable on the LOW−to−HIGH transition of P_LOAD
						tion.
	M[8:0]**				CMOS/TTL PLL Loop Divider	These pins are used to configure the PLL loop divider. They are sampled on the
					Inputs (Internal Pullup Resistor)	LOW−to−HIGH transition of P_LOAD . M[8] is the MSB, M[0] is the LSB.
	N[1:0]**				CMOS/TTL Output Divider Inputs	These pins are used to configure the output divider modulus. They are sampled
					(Internal Pullup Resistor)	on the LOW−to−HIGH transition of P_LOAD .
	OE**				CMOS/TTL Output Enable Input	Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
					(Internal Pullup Resistor)	runt pulse generation on the FOUT output.
	FREF_EXT*				CMOS/TTL Input	This pin can be used as the PLL Reference
					(Internal Pulldown Resistor)
	XTAL_SEL**				CMOS/TTL Input	This pin selects between the crystal and the FREF_EXT source for the PLL refer-
					(Internal Pullup Resistor)	ence signal. A HIGH selects the crystal input.
OUTPUTS
	FOUT,	FOUT			PECL Differential Outputs	These differential, positive−referenced ECL signals (PECL) are the outputs of the
						synthesizer.
	TEST				PECL Output	The function of this output is determined by the serial configuration bits T[2:0].
POWER
	VCC				Positive Supply for the Logic	The positive supply for the internal logic and output buffer of the chip, and is con-
						nected to +3.3 V or +5.0 V.
	PLL_VCC				Positive Supply for the PLL	This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.
	GND				Negative Power Supply	These pins are the negative supply for the chip and are normally all connected to
						ground.

*When left Open, these inputs will default LOW.

**When left Open, these inputs will default HIGH.

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NBC12430, NBC12430A

ATTRIBUTES

Characteristics		Value
Internal Input Pulldown Resistor		75 k
Internal Input Pullup Resistor		37.5 k
ESD Protection	Human Body Model	> 2 kV
	Machine Model	> 150 V
	Charged Device Model	> 1 kV
Moisture Sensitivity (Note 1)		Level 1
	PLCC	Level 2
	LQFP
Flammability Rating	Oxygen Index: 28 to 34	UL 94 V−0 @
		0.125 in
Transistor Count		2011
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.

MAXIMUM RATINGS

Symbol	Parameter	Condition 1	Condition 2	Rating	Units
VCC	Positive Supply	GND = 0 V		6	V
VI	Input Voltage	GND = 0 V	VI VCC	6	V
Iout	Output Current	Continuous		50	mA
		Surge		100	mA
TA	Operating Temperature Range			0 to 70	°C
	NBC12430
	NBC12430A			−40 to +85
Tstg	Storage Temperature Range			−65 to +150	°C
JA	Thermal Resistance (Junction−to−Ambient)	0 lfpm	PLCC−28	63.5	°C/W
		500 lfpm	PLCC−28	43.5	°C/W
JC	Thermal Resistance (Junction−to−Case)	Standard Board	PLCC−28	22 to 26	°C/W
JA	Thermal Resistance (Junction−to−Ambient)	0 lfpm	LQFP−32	80	°C/W
		500 lfpm	LQFP−32	55	°C/W
JC	Thermal Resistance (Junction−to−Case)	Standard Board	LQFP−32	12 to 17	°C/W
Tsol	Wave Solder	<3 sec @ 248°C			°C
	Pb			265
	Pb−Free	<3 sec @ 260°C		265

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

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NBC12430, NBC12430A

DC CHARACTERISTICS (VCC = 3.3 V ± 5%; TA = 0°C to 70°C (NBC12430), TA = −40 °C to 85°C (NBC12430A))

Symbol	Characteristic			Condition	Min	Typ	Max	Unit
VIH	Input HIGH Voltage			VCC = 3.3 V	2.0			V
LVCMOS/
LVTTL
VIL	Input LOW Voltage			VCC = 3.3 V			0.8	V
LVCMOS/
LVTTL
IIN	Input Current						1.0	mA
VOH	Output HIGH Voltage			VCC = 3.3 V	2.155		2.405	V
PECL		FOUT		(Notes 2, 3)
		FOUT
	TEST
VOL	Output LOW Voltage			VCC = 3.3 V	1.355		1.605	V
PECL		FOUT		(Notes 2, 3)
		FOUT
		TESt
ICC	Power Supply Current				45	58	80	mA
		VCC
	PLL_VCC				17	25	30	mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

2.FOUT/FOUT and TEST output levels will vary 1:1 with VCC variation.

3.FOUT/FOUT and TEST outputs are terminated through a 50 resistor to VCC − 2.0 V.

DC CHARACTERISTICS (VCC = 5.0 V ± 5%; TA = 0°C to 70°C (NBC12430), TA = −40 °C to 85°C (NBC12430A))

Symbol	Characteristic			Condition	Min	Typ	Max	Unit
VIH	Input HIGH Voltage			VCC = 5.0 V	2.0			V
CMOS/
TTL
VIL	Input LOW Voltage			VCC = 5.0 V			0.8	V
CMOS/
TTL
IIN	Input Current						1.0	mA
VOH	Output HIGH Voltage			VCC = 5.0 V	3.855		4.105	V
PECL		FOUT		(Notes 4, 5)
		FOUT
	TEST
VOL	Output LOW Voltage			VCC = 5.0 V	3.055		3.305	V
PECL		FOUT		(Notes 4, 5)
		FOUT
	TEST
ICC	Power Supply Current				50	60	85	mA
		VCC
	PLL_VCC				18	24	30	mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

4.FOUT/FOUT and TEST output levels will vary 1:1 with VCC variation.

5.FOUT/FOUT and TEST outputs are terminated through a 50 resistor to VCC − 2.0 V.

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NBC12430, NBC12430A

AC CHARACTERISTICS (VCC = 3.135 V to 5.25 V ± 5%; TA = 0°C to 70°C (NBC12430), TA = −40 °C to 85°C (NBC12430A)) (Note 7)

Symbol	Characteristic							Condition	Min	Max	Unit
FMAXI	Maximum Input Frequency			S_CLOCK				(Note 6)		10	MHz
			XTAL Oscillator						10	20
			FREF_EXT (Note 8)						10	20
FMAXO	Maximum Output Frequency		VCO (Internal)						400	800	MHz
					FOUT				50	800
tLOCK	Maximum PLL Lock Time									10	ms
tjitter(pd)	Period Jitter (RMS)				(1 )			50 MHz fOUT < 100 MHz		8	ps
								100 MHz fOUT < 800 MHz		5
tjitter(cyc−cyc)	Cycle−to−Cycle Jitter (Peak−to−Peak)				(8 )			50 MHz fOUT < 100 MHz		40	ps
								100 MHz fOUT < 800 MHz		20
ts	Setup Time	S_DATA to S_CLOCK							20		ns
		S_CLOCK to S_LOAD							20
			M, N to						20
					P_LOAD
th	Hold Time	S_DATA to S_CLOCK							20		ns
			M, N to		P_LOAD				20
tpwMIN	Minimum Pulse Width				S_LOAD				50		ns
									50
					P_LOAD
DCO	Output Duty Cycle								47.5	52.5	%
tr, tf	Output Rise/Fall				FOUT			20%−80%	175	425	ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

6.10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as a test clock in TEST_MODE 6.

7.FOUT/FOUT and TEST outputs are terminated through a 50 resistor to VCC − 2.0 V.

8.Maximum frequency on FREF_EXT is a function of setting the appropriate M counter value, 160 M 511, for the VCO to operate within the valid range of 400 MHz fVCO 800 MHz. (See Table 5)

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