ON Semiconductor MC74VHC32 User Manual

Page 1

Quad 2-Input OR Gate

MC74VHC32

The MC74VHC32 is an advanced high speed CMOS 2−input OR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.

Features

• High Speed: t

• Low Power Dissipation: I

• High Noise Immunity: V

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Designed for 2.0 V to 5.5 V Operating Range

• Low Noise: V

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300 mA

• ESD Performance:

• Chip Complexity: 48 FETs or 12 Equivalent Gates

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable

• These Devices are Pb−Free and are RoHS Compliant

Figure 1. Logic Diagram

B4 A4 Y4 B3 A3 Y3

1314 12 11 10 9 8

= 3.8 ns (Typ) at VCC = 5.0 V

= 2.0 mA (Max) at TA = 25°C

= 0.8 V (Max)

OLP

NIH

= V

= 28% V

NIL

Human Body Model > 2000 V; Machine Model > 200 V

Y = A+B

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MARKING

DIAGRAMS

SOIC−14

D SUFFIX

CASE 751A

TSSOP

DT SUFFIX

CASE 948G

A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or  = Pb−Free Package

(Note: Microdot may be in either location)

VHC32G

AWLYWW

VHC

ALYW 



FUNCTION TABLE

Inputs Output

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.

21 34567

A1 B1 Y1 A2 B2 Y2 GND

(Top View)

Figure 2. Pinout: 14−Lead Packages

February, 2021 − Rev. 8

1 Publication Order Number:

MC74VHC32/D

Page 2

MC74VHC32

MAXIMUM RATINGS

Symbol Parameter Value Unit

DC Supply Voltage –0.5 to +7.0 V

DC Input Voltage –0.5 to +7.0 V

DC Output Voltage –0.5 to VCC +0.5 V

out

Input Diode Current −20 mA

Output Diode Current ±20 mA

DC Output Current, per Pin ±25 mA

out

DC Supply Current, VCC and GND Pins ±50 mA

Power Dissipation in Still Air, SOIC Package

TSSOP Package

Storage Temperature –65 to +150 °C

stg

†

500 450

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating − SOIC Package: – 7 mW/°C from 65° to 125°C

TSSOP Package: − 6.1 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

tr, t

DC Supply Voltage 2.0 5.5 V

DC Input Voltage 0 5.5 V

DC Output Voltage 0 V

out

Operating Temperature −40 +125 °C

Input Rise and Fall Time VCC = 3.3 V ±0.3 V

= 5.0 V ±0.5 V

0 0

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Conditions

Minimum High−Level

Input Voltage

Maximum Low−Level

Input Voltage

Minimum High−Level

Output Voltage

Vin = VIH or V IOH = −50 mA

Vin = VIH or V

IOH = −4.0 mA I

= −8.0 mA

Maximum Low−Level

Output Voltage

Vin = VIH or V IOL = 50 mA

Vin = VIH or V

IOL = 4.0 mA I

= 8.0 mA

Maximum Input

Leakage Current

Maximum Quiescent

Supply Current

Vin = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0

Vin = VCC or GND 5.5 2.0 20.0

2.0

3.0 to 5.5

2.0

3.0 to 5.5

2.0

3.0

4.5

3.0

4.5

2.0

3.0

4.5

3.0

4.5

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

TA = 25°C TA = −40°C to 125°C

Min Typ Max Min Max

1.50 x 0.7

0.50

x 0.3

1.9

2.9

4.4

2.0

3.0

4.5

2.58

3.94

0.0

0.1

0.36

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V V

should be constrained to the

out

range GND v (V

or V

) v VCC.

out

and

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V

Unused outputs must be left open.

100

ns/V

Unit

1.50

x 0.7

0.50

x 0.3

1.9

2.9

4.4

2.48

3.80

0.1

0.44

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Page 3

MC74VHC32

AC ELECTRICAL CHARACTERISTICS (Input t

= t

= 3.0 ns)

TA = 25°C TA = −40°C to 125°C

Symbol

PLH

PHL

Parameter Test Conditions

Maximum Propagation Delay, A or B to Y

VCC = 3.3 ± 0.3 V CL = 15 pF

= 50 pF

VCC = 5.0 ± 0.5 V CL = 15 pF

= 50 pF

Maximum Input Capacitance 4 10 10 pF

Min Typ Max Min Max

5.5

8.0

3.8

5.3

7.9

11.4

5.5

7.5

1.0

9.5

13.0

6.5

8.5

Unit

Typical @ 25°C, VCC = 5.0 V

Power Dissipation Capacitance (Note 1)

1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I no−load dynamic power consumption; P

NOISE CHARACTERISTICS (Input t

= CPD  V

= tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)

 fin + ICC  VCC.

= CPD  VCC  fin + ICC/ 4 (per gate). CPD is used to determine the

)

CC(OPR

TA = 25°C

Symbol

OLP

OLV

IHD

ILD

Characteristic

Quiet Output Maximum Dynamic V

Quiet Output Minimum Dynamic V

Minimum High Level Dynamic Input Voltage 3.5 V

Maximum Low Level Dynamic Input Voltage 1.5 V

Typ Max

Unit

0.3 0.8 V

−0.3 −0.8 V

A or B

TEST

50%

GND

DEVICE

OUTPUT

UNDER

PLH

50% V

PHL

TEST

POINT

CL*

*Includes all probe and jig capacitance

Figure 3. Switching Waveforms

Figure 4. Test Circuit

INPUT

Figure 5. Input Equivalent Circuit

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Page 4

MC74VHC32

ORDERING INFORMATION

Device Package Shipping

MC74VHC32DR2G

NLV74VHC32DR2G*

MC74VHC32DTG

MC74VHC32DTR2G

NLV74VHC32DTR2G*

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

SOIC−14

(Pb−Free)

TSSOP−14

(Pb−Free)

2500 Units / Tape & Reel

96 Units / Rail

2500 Units / Tape & Reel

†

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Page 5

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 1:1

SOIC−14 NB

CASE 751A−03

ISSUE L

DATE 03 FEB 2016

0.25 B

0.10

14X

0.58

13X

SOLDERING FOOTPRINT*

6.50

A B

0.25 B

SEATING

PLANE

14X

1.18

1.27 PITCH

DETAIL A

X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

DETAIL A

PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

DIM MIN MAX MIN MAX

A 1.35 1.75 0.054 0.068 A1 0.10 0.25 0.004 0.010 A3 0.19 0.25 0.008 0.010

b 0.35 0.49 0.014 0.019

D 8.55 8.75 0.337 0.344

E 3.80 4.00 0.150 0.157

e 1.27 BSC 0.050 BSC

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.019

L 0.40 1.25 0.016 0.049

M 0 7 0 7

__ __

INCHESMILLIMETERS

GENERIC

MARKING DIAGRAM*

XXXXXXXXXG

AWLYWW

XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week G = Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42565B

SOIC−14 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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Page 6

SOIC−14

CASE 751A−03

ISSUE L

DATE 03 FEB 2016

STYLE 1:

PIN 1. COMMON CATHODE

2. ANODE/CATHODE

3. ANODE/CATHODE

4. NO CONNECTION

5. ANODE/CATHODE

6. NO CONNECTION

7. ANODE/CATHODE

8. ANODE/CATHODE

9. ANODE/CATHODE

10. NO CONNECTION

11. ANODE/CATHODE

12. ANODE/CATHODE

13. NO CONNECTION

14. COMMON ANODE

STYLE 5:

PIN 1. COMMON CATHODE

2. ANODE/CATHODE

3. ANODE/CATHODE

4. ANODE/CATHODE

5. ANODE/CATHODE

6. NO CONNECTION

7. COMMON ANODE

8. COMMON CATHODE

9. ANODE/CATHODE

10. ANODE/CATHODE

11. ANODE/CATHODE

12. ANODE/CATHODE

13. NO CONNECTION

14. COMMON ANODE

STYLE 2:

CANCELLED

STYLE 6:

PIN 1. CATHODE

2. CATHODE

3. CATHODE

4. CATHODE

5. CATHODE

6. CATHODE

7. CATHODE

8. ANODE

9. ANODE

10. ANODE

11. ANODE

12. ANODE

13. ANODE

14. ANODE

STYLE 3:

PIN 1. NO CONNECTION

2. ANODE

3. ANODE

4. NO CONNECTION

5. ANODE

6. NO CONNECTION

7. ANODE

8. ANODE

9. ANODE

10. NO CONNECTION

11. ANODE

12. ANODE

13. NO CONNECTION

14. COMMON CATHODE

STYLE 7:

PIN 1. ANODE/CATHODE

2. COMMON ANODE

3. COMMON CATHODE

4. ANODE/CATHODE

5. ANODE/CATHODE

6. ANODE/CATHODE

7. ANODE/CATHODE

8. ANODE/CATHODE

9. ANODE/CATHODE

10. ANODE/CATHODE

11. COMMON CATHODE

12. COMMON ANODE

13. ANODE/CATHODE

14. ANODE/CATHODE

STYLE 4:

PIN 1. NO CONNECTION

2. CATHODE

3. CATHODE

4. NO CONNECTION

5. CATHODE

6. NO CONNECTION

7. CATHODE

8. CATHODE

9. CATHODE

10. NO CONNECTION

11. CATHODE

12. CATHODE

13. NO CONNECTION

14. COMMON ANODE

STYLE 8:

PIN 1. COMMON CATHODE

2. ANODE/CATHODE

3. ANODE/CATHODE

4. NO CONNECTION

5. ANODE/CATHODE

6. ANODE/CATHODE

7. COMMON ANODE

8. COMMON ANODE

9. ANODE/CATHODE

10. ANODE/CATHODE

11. NO CONNECTION

12. ANODE/CATHODE

13. ANODE/CATHODE

14. COMMON CATHODE

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42565B

SOIC−14 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

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Page 7

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 2:1

0.10 (0.004)

SEATING

−T−

PLANE

U0.15 (0.006) T

2X L/2

PIN 1 IDENT.

U0.15 (0.006) T

SOLDERING FOOTPRINT

14X REFK

0.10 (0.004) V

−V−

7.06

TSSOP−14 WB

−U−

CASE 948G

ISSUE C

DETAIL E

SECTION N−N

DETAIL E

0.25 (0.010)

DATE 17 FEB 2016

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

INCHESMILLIMETERS

−W−

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

GENERIC

MARKING DIAGRAM*

XXXX XXXX

ALYWG

A = Assembly Location L = Wafer Lot Y = Year

0.65 PITCH

W = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

*This information is generic. Please refer to

14X

0.36

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

14X

1.26

98ASH70246A

TSSOP−14 WB

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

PAGE 1 OF 1

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Page 8

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