April 2000
Geode™ GXLV Processor Series
Low Power Integrated x86 Solutions
General Description
The National Semiconductor® Geode™ GXLV processor series is a new line of integrated processors specifically designed to power information appliances for entertainment, education, and business. Serving the needs of consumers and business professionals alike, it is the perfect solution for information appliance applications such as thin clients, interactive set top boxes, and personal internet access devices.
The GXLV processor series is divided into three main categories as defined by the core operating voltage. Available with core voltages of 2.2V, 2.5V, and 2.9V, it offers extremely low typical power consumption (1.0W to 2.5W)
leading to longer battery life and enabling small form-fac- tor, fanless designs. Each core voltage is offered in frequencies that are enabled by specific system clock and multiplier settings. This allows the user to select the device(s) that best fit their power and performance requirements. This flexibility makes the GXLV processor series ideally suited for applications where power consumption and performance (speed) are equally important.
Typical power consumption is defined as an average, measured running Microsoft’s Windows at 80% Active Idle (Suspend-on-Halt) with a display resolution of 800x600x8 bpp at 75 Hz.
Internal Block Diagram |
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multiplied by |
Clocks |
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Control |
INTR |
Companion |
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Clock Module |
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SYSCLK |
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SYSCLK |
Core |
X86 Compatible Core |
INT/NMI |
Interrupt |
IRQ13 |
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A |
X-Bus |
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Integer |
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SMI# |
I/O |
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Clocks |
TLB |
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Unit |
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Scratchpad |
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FP_Error |
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16 KB |
(128) |
Instruction |
MMU |
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Floating Point |
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Unified L1 |
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Fetch |
Load/Store |
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Cache |
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C-Bus (64) |
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SUSP# |
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Core Suspend |
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Write Buffers |
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X-Bus Controller |
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Power |
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Core Acknowledge |
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SUSPA# |
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Management |
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Arbiter |
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Control |
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X-Bus Suspend |
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X-Bus Acknowledge |
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Read Buffers |
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X-Bus (32) |
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PCI Host |
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2D Accelerator |
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X-Bus Clk ÷ B |
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Display Controller |
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Arbiter |
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VGA |
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Compression Buffer |
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Controller |
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BLT Engine |
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Palette RAM |
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ROP Unit |
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Timing Generator |
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PCI Bus |
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4 |
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64-bit SDRAM |
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RGB |
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YUV |
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REQ/GNT |
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SDRAM |
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Pairs |
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Video Companion Interface |
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Clocks |
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National Semiconductor is a registered trademark of National Semiconductor Corporation.
Geode and WebPAD are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
Solutions X86 Integrated Power Low Series Processor GXLV Geode™
© 2000 National Semiconductor® Corporation |
www.national.com |
Geode™ GXLV Processor Series
While the x86 core provides maximum compatibility with the vast amount of internet content available, the intelligent integration of several other functions, such as memory controller and graphics, offer a true system-level multimedia solution.
The GXLV processor core is a proven x86 design that offers competitive performance. It contains integer and floating point execution units based on sixth-generation technology. The integer core contains a single, five-stage execution pipeline and offers advanced features such as operand forwarding, branch target buffers, and extensive write buffering. Accesses to the 16 KB write-back L1 cache are dynamically reordered to eliminate pipeline stalls when fetching operands.
In addition to the advanced CPU features, the GXLV processor integrates a host of functions typically implemented with external components. A full function graphics accelerator contains a Video Graphics Array (VGA) controller, bitBLT engine, and a Raster Operations (ROP) unit for complete Graphical User Interface (GUI) acceleration under most operating systems. A display controller contains additional video buffering to enable >30 fps MPEG1 playback and video overlay when used with a National Semiconductor I/O Companion chip such as the CS5530. Graphics and system memory accesses are supported by a tightly coupled SDRAM controller which eliminates the need for an external L2 cache. A PCI host controller supports up to three bus masters for additional connectivity and multimedia capabilities.
The GXLV processor also incorporates Virtual System Architecture® (VSA™) technology. VSA technology enables the XpressGRAPHICS and XpressAUDIO subsystems. Software handlers are available that provide full compatibility for industry standard VGA and 16-bit audio functions that are transparent at the operating system level.
The GXLV processor is designed to be used with the CS5530 I/O Companion, also supplied by National Semiconductor. Together they provide a scalable, flexible, lowpower, system-level solution well suited for a wide array of information appliances ranging from hand-held personal information access devices to digital set top boxes and thin clients.
Features
General Features
Packaging:
—352-Terminal Ball Grid Array (BGA) or
—320-Pin Staggered Pin Grid Array (SPGA)
0.25-micron four layer metal CMOS process
Split rail design:
—Available 2.2V, 2.5V, or 2.9V core
—3.3V I/O interface (5V tolerant)
Low typical power consumption:
—1.0W @ 2.2V/166 MHz
—2.5W @ 2.9V/266 MHz
Note: Typical power consumption is defined as an average, measured running Windows at 80% Active Idle (Suspend-on-Halt) with a display resolution of 800x600x8 bpp @ 75 Hz.
Speeds offered up to 266 MHz
Unified Memory Architecture:
—Frame buffer and video memory reside in main memory
—Minimizes Printed Circuit Board (PCB) area requirements
—Reduces system cost
Compatible with multiple Geode I/O companion devices provided by National Semiconductor
32-Bit x86 Processor
Supports Intel’s MMX instruction set extension for the acceleration of multimedia applications
16 KB unified L1 cache
Five-stage pipelined integer unit
Integrated Floating Point Unit (FPU)
Memory Management Unit (MMU) adheres to standard paging mechanisms and optimizes code fetch performance:
—Load-store reordering gives priority to memory reads
—Memory-read bypassing eliminates unnecessary or redundant memory reads
Re-entrant System Management Mode (SMM) enhanced for VSA technology
Fully Static Design
Flexible Power Management
Supports a wide variety of standards:
—APM for Legacy power management
—ACPI for Windows power management
–Direct support for all standard processor (C0-C4) states
—OnNOW specification compliant
Supports a wide variety of hardware and software controlled modes:
—Fully Active
—Active Idle (core stopped, display active)
—Standby (core and all integrated functions halted)
—Sleep (core and integrated functions halted and all external clocks stopped)
—Suspend Modulation (automatic throttling of CPU core)
–Programmable duty cycle for optimal performance/thermal balancing
—Several dedicated and programmable wake-up events (via Geode I/O companion chip)
www.national.com |
2 |
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PCI Host Controller
Several arbitration schemes supported
Supports up to three PCI bus masters
Synchronous to CPU core
Allows external PCI master accesses to main memory concurrent with CPU accesses to L1 cache
Virtual Systems Architecture Technology
Innovative architecture allowing OS independent (software) virtualization of hardware functions
Provides XpressGRAPHICS subsystem:
— High performance legacy VGA core compatibility
Note: Uses 2D Graphics Accelerator.
Provides 16-bit XpressAUDIO subsystem:
—16-bit stereo FM synthesis
—OPL3 emulation
—Supports MPU-401 MIDI interface
—Hardware assist provided via Geode I/O companion chip
Additional hardware functions can be supported as needed
2D Graphics Accelerator
Accelerates BitBLTs, line draw, text
Bresenham vector engine
Supports all 256 ROPs
Supports transparent BLTs and page flipping for Microsoft’s DirectDraw
Runs at core clock frequency
Full VGA and VESA mode support
Special "driver level” instructions utilize internal scratchpad for enhanced performance
Display Controller
Display Compression Technology (DCT) architecture greatly reduces memory bandwidth consumption of display refresh
Supports a separate video buffer and data path to enable video acceleration in Geode I/O companion devices
Internal palette RAM for gamma correction
Direct interface to Geode I/O companion devices for CRT and TFT flat panel support eliminates the need for an external RAMDAC
Hardware cursor
Supports up to 1280x1024x8 bpp and 1024x768x16 bpp
XpressRAM Subsystem
SDRAM interface tightly coupled to CPU core and graphics subsystem for maximum efficiency
64-Bit wide memory bus
Support for:
—Two 168-pin unbuffered DIMMs
—Up to 16 simultaneously open banks
—16-byte reads (burst length of two)
—Up to 256 MB total memory supported
Diverse Operating System Support
Microsoft’s Windows 2000, 9X, NT, and CE
Sun Microsystems’ Java
WindRiver Systems’ VxWorks
QNX Software Systems’ QNX
Linux
Series Processor GXLV Geode™
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Geode™ GXLV Processor Series
Table of Contents
1.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 |
INTEGER UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
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1.2 |
FLOATING POINT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
|
1.3 |
WRITE-BACK CACHE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
|
1.4 |
MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
|
1.5 |
INTERNAL BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
|
1.6 |
INTEGRATED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
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|
1.6.1 |
Graphics Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
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1.6.2 |
Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
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1.6.3 |
XpressRAM Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
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1.6.4 |
PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
1.7 |
GEODE GXLV/CS5530 SYSTEM DESIGNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
13 |
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|
1.7.1 |
Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
16 |
2.0 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.1 System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.2 PCI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.3 Memory Controller Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.4 Video Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.5 Power, Ground, and No Connect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.6 Internal Test and Measurement Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.0 Processor Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.1 CORE PROCESSOR INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 INSTRUCTION SET OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.1 Lock Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3 REGISTER SETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.1 Application Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.1.1 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.1.2 Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.1.3 Instruction Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.1.4 EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.2 |
System Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
47 |
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3.3.2.1 |
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
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3.3.2.2 |
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
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3.3.2.3 |
Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
55 |
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3.3.2.4 |
TLB Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
57 |
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3.3.2.5 |
Cache Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
59 |
3.3.3 Model Specific Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.3.4 Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.4 ADDRESS SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.1 I/O Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.2 Memory Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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Table of Contents (Continued)
3.5 OFFSET, SEGMENT, AND PAGING MECHANISMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.5.1 Offset Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.5.2 Segment Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.5.2.1 Real Mode Segment Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
66 |
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3.5.2.2 Virtual 8086 Mode Segment Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
66 |
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3.5.2.3 |
Segment Mechanism in Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
67 |
3.5.2.4 |
Segment Selectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
67 |
3.5.3 Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.5.3.1 Global and Local Descriptor Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
70 |
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3.5.3.2 |
Segment Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
70 |
3.5.3.3 |
Task, Gate, Interrupt, and Application and System Descriptors . . . . . . . . . . . . . . |
71 |
3.5.4 Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.6 INTERRUPTS AND EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.6.2 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.6.3 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.6.3.1 Interrupt Vector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.6.3.2 Interrupt Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.6.4 Interrupt and Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.6.5 Exceptions in Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.6.6 Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.7 SYSTEM MANAGEMENT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.7.1 SMM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.7.2 SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.7.3 SMM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.7.4 SMM Memory Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.7.5 SMM Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.7.6 SMM Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.7.7 SMI Generation for Virtual VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.7.8 SMM Service Routine Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7.8.1 SMI Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.7.8.2 CPU States Related to SMM and Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.8 |
HALT AND SHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
91 |
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3.9 |
PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
91 |
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3.9.1 |
Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
91 |
|
3.9.2 |
I/O Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
91 |
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3.9.3 |
Privilege Level Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
92 |
3.9.3.1 Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.9.4 Initialization and Transition to Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.10 VIRTUAL 8086 MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.10.1 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.10.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.10.3 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.10.4 Entering and Leaving Virtual 8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.11 FLOATING POINT UNIT OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.11.1 FPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.11.2 FPU Tag Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.11.3 FPU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.11.4 FPU Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Series Processor GXLV Geode™
Revision 1.1 |
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Geode™ GXLV Processor Series
Table of Contents (Continued)
4.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.1 INTEGRATED FUNCTIONS PROGRAMMING INTERFACE . . . . . . . . . . . . . . . . . . . . . . . 97 4.1.1 Graphics Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.1.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.1.3 Graphics Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.1.4 Scratchpad RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.1 Initialization of Scratchpad RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.1.4.2 Scratchpad RAM Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.1.4.3 BLT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.5 Display Driver Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.1.6 CPU_READ/CPU_WRITE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.2 INTERNAL BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.2.1 FPU Error Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.2.2 A20M Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.2.3 SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.2.4 640 KB to 1 MB Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.2.5 Internal Bus Interface Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.3 MEMORY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.3.1 Memory Array Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.3.2 Memory Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.3.3 SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.3.3.1 SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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4.3.4 |
Memory Controller Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
112 |
|
4.3.5 |
Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
117 |
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4.3.5.1 High Order Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
117 |
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4.3.5.2 Auto Low Order Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
117 |
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4.3.5.3 Physical Address to DRAM Address Conversion . . . . . . . . . . . . . . . . . . . . . . . . |
117 |
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4.3.6 |
Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
120 |
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4.3.7 |
SDRAM Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
123 |
4.4 |
GRAPHICS PIPELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
125 |
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4.4.1 |
BitBLT/Vector Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
125 |
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4.4.2 |
Master/Slave Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
126 |
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4.4.3 |
Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
126 |
4.4.3.1 Monochrome Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.3.2 Dither Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.3.3 Color Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.4 Source Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.5 Raster Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.4.6 Graphics Pipeline Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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4.5 |
DISPLAY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
134 |
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4.5.1 |
Display FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
135 |
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4.5.2 |
Compression Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
135 |
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4.5.3 |
Hardware Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
136 |
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4.5.4 |
Display Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
136 |
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4.5.5 Dither and Frame Rate Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
136 |
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4.5.6 |
Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
136 |
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4.5.7 |
Graphics Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
140 |
4.5.7.1 DC Memory Organization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4.5.7.2 Frame Buffer and Compression Buffer Organization . . . . . . . . . . . . . . . . . . . . . . 140
4.5.7.3 VGA Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.5.8 Display Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.5.8.1 Configuration and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
4.5.9 Memory Organization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
4.5.10 Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
4.5.11 Cursor Position and Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
4.5.12 Palette Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
4.5.13 FIFO Diagnostic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
4.5.14 CS5530 Display Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.5.14.1 CS5530 Video Port Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
4.6 VIRTUAL VGA SUBSYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
4.6.1 Traditional VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
4.6.1.1 VGA Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
4.6.1.2 VGA Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
4.6.1.3 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
4.6.1.4 Video Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
4.6.1.5 VGA Video BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
4.6.2 Virtual VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
159 |
4.6.2.1 Datapath Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
4.6.2.2 GXLV VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
4.6.2.3 SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.6.2.4 VGA Range Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.6.2.5 VGA Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.6.2.6 VGA Write/Read Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.6.2.7 VGA Address Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.6.2.8 VGA Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.6.3 VGA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.6.4 Virtual VGA Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.7 PCI CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.7.1 X-Bus PCI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.7.2 X-Bus PCI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.7.3 PCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.7.4 Generating Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.7.5 Generating Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.7.6 PCI Configuration Space Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.7.7 PCI Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.7.8 PCI Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.7.8.1 PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.7.8.2 PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4.7.8.3 PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
4.7.8.4 PCI Halt Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Series Processor GXLV Geode™
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Geode™ GXLV Processor Series
Table of Contents (Continued)
5.0 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
5.1 |
POWER MANAGEMENT FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
176 |
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5.1.1 |
System Management Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
176 |
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5.1.2 Suspend-on-Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
176 |
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5.1.3 |
CPU Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
176 |
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5.1.3.1 Suspend Modulation for Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . |
177 |
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5.1.3.2 Suspend Modulation for Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . |
177 |
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5.1.4 |
3 Volt Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
177 |
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5.1.5 GXLV Processor Serial Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
177 |
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5.1.6 Advanced Power Management (APM) Support . . . . . . . . . . . . . . . . . . . . . . . . . . |
177 |
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5.2 SUSPEND MODES AND BUS CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
178 |
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5.2.1 Timing Diagram for Suspend-on-Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
178 |
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5.2.2 Initiating Suspend with SUSP# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
179 |
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5.2.3 Stopping the Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
180 |
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5.2.4 |
Serial Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
180 |
5.3 |
POWER MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
181 |
6.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.1 PART NUMBERS/PERFORMANCE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 184 6.2 ELECTRICAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.2.1 Power/Ground Connections and Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.2.1.1 Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.2.2 NC-Designated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.3 Pull-Up and Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.4 Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
6.3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.4 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.5 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 6.5.1 Input/Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 6.5.2 DC Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.5.2.1 Definition of CPU Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 6.5.2.2 Definition and Measurement Techniques of CPU Current Parameters . . . . . . . . 190 6.5.2.3 Definition of System Conditions for Measuring "On" Parameters . . . . . . . . . . . . 191 6.5.2.4 DC Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.6 I/O CURRENT DE-RATING CURVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 6.6.1 Display Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 6.6.2 Memory Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 6.6.3 I/O Current De-rating Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.7 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
7.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7.1 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 7.1.1 Heatsink Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 7.2 MECHANICAL PACKAGE OUTLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
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Table of Contents (Continued)
8.0 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
8.1 GENERAL INSTRUCTION SET FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 8.1.1 Prefix (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 8.1.2 Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
8.1.2.1 w Field (Operand Size) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 8.1.2.2 d Field (Operand Direction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 8.1.2.3 s Field (Immediate Data Field Size) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 8.1.2.4 eee Field (MOV-Instruction Register Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.1.3 mod and r/m Byte (Memory Addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 8.1.4 reg Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
8.1.4.1 sreg2 Field (ES, CS, SS, DS Register Selection) . . . . . . . . . . . . . . . . . . . . . . . . 216 8.1.4.2 sreg3 Field (FS and GS Segment Register Selection) . . . . . . . . . . . . . . . . . . . . 216
8.1.5 s-i-b Byte (Scale, Indexing, Base) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
8.1.5.1 ss Field (Scale Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 8.1.5.2 index Field (Index Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 8.1.5.3 Base Field (s-i-b Present) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
8.2 CPUID INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 8.2.1 Standard CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.2.1.1 CPUID Instruction with EAX = 0000 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 8.2.1.2 CPUID Instruction with EAX = 00000001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 8.2.1.3 CPUID Instruction with EAX = 00000002h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
8.2.2 Extended CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.2.2.1 CPUID Instruction with EAX = 80000000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 8.2.2.2 CPUID Instruction with EAX = 80000001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 8.2.2.3 CPUID Instruction with EAX = 80000002h, 80000003h, 80000004h . . . . . . . . . 221 8.2.2.4 CPUID Instruction with EAX = 80000005h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.3 PROCESSOR CORE INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 8.3.1 Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 8.3.2 Clock Counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 8.3.3 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
8.4 FPU INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 8.5 MMX INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 8.6 EXTENDED MMX INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Appendix A Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
A.1 Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
A.2 Data Book Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Series Processor GXLV Geode™
Revision 1.1 |
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Geode™ GXLV Processor Series
1.0Architecture Overview
The Geode GXLV processor series represents the sixth generation of x86-compatible 32-bit processors with sixthgeneration features. The decoupled load/store unit allows reordering of load/store traffic to achieve higher performance. Other features include single-cycle execution, sin- gle-cycle instruction decode, 16 KB write-back cache, and clock rates up to 266 MHz. These features are made possible by the use of advanced-process technologies and pipelining.
The GXLV processor has low power consumption at all clock frequencies. Where additional power savings are required, designers can make use of Suspend Mode, Stop Clock capability, and System Management Mode (SMM).
The GXLV processor is divided into major functional blocks (as shown in Figure 1-1):
•Integer Unit
•Floating Point Unit (FPU)
•Write-Back Cache Unit
•Memory Management Unit (MMU)
•Internal Bus Interface Unit
•Integrated Functions
Instructions are executed in the integer unit and in the floating point unit. The cache unit stores the most recently used data and instructions and provides fast access to this information for the integer and floating point units.
Write-Back |
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MMU |
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SDRAM Port |
CS5530 |
PCI Bus |
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(CRT/LCD TFT) |
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Figure 1-1. Internal Block Diagram
www.national.com |
10 |
Revision 1.1 |
Architecture Overview (Continued)
1.1 INTEGER UNIT
The integer unit consists of:
•Instruction Buffer
•Instruction Fetch
•Instruction Decoder and Execution
The pipelined integer unit fetches, decodes, and executes x86 instructions through the use of a five-stage integer pipeline.
The instruction fetch pipeline stage generates, from the on-chip cache, a continuous high-speed instruction stream for use by the processor. Up to 128 bits of code are read during a single clock cycle.
Branch prediction logic within the prefetch unit generates a predicted target address for unconditional or conditional branch instructions. When a branch instruction is detected, the instruction fetch stage starts loading instructions at the predicted address within a single clock cycle. Up to 48 bytes of code are queued prior to the instruction decode stage.
The instruction decode stage evaluates the code stream provided by the instruction fetch stage and determines the number of bytes in each instruction and the instruction type. Instructions are processed and decoded at a maximum rate of one instruction per clock.
The address calculation function is pipelined and contains two stages, AC1 and AC2. If the instruction refers to a memory operand, AC1 calculates a linear memory address for the instruction.
The AC2 stage performs any required memory management functions, cache accesses, and register file accesses. If a floating point instruction is detected by AC2, the instruction is sent to the floating point unit for processing.
The execution stage, under control of microcode, executes instructions using the operands provided by the address calculation stage.
Write-back, the last stage of the integer unit, updates the register file within the integer unit or writes to the load/store unit within the memory management unit.
1.2FLOATING POINT UNIT
The floating point unit (FPU) interfaces to the integer unit and the cache unit through a 64-bit bus. The FPU is x87- instruction-set compatible and adheres to the IEEE-754 standard. Because almost all applications that contain FPU instructions also contain integer instructions, the GXLV processor’s FPU achieves high performance by completing integer and FPU operations in parallel.
FPU instructions are dispatched to the pipeline within the integer unit. The address calculation stage of the pipeline checks for memory management exceptions and accesses memory operands for use by the FPU. Once the instructions and operands have been provided to the FPU, the FPU completes instruction execution independently of the integer unit.
1.3WRITE-BACK CACHE UNIT
The 16 KB write-back unified (data/instruction) cache is configured as four-way set associative. The cache stores up to 16 KB of code and data in 1024 cache lines.
The GXLV processor provides the ability to allocate a portion of the L1 cache as a scratchpad, which is used to accelerate the Virtual Systems Architecture technology algorithms as well as for some graphics operations.
1.4MEMORY MANAGEMENT UNIT
The memory management unit (MMU) translates the linear address supplied by the integer unit into a physical address to be used by the cache unit and the internal bus interface unit. Memory management procedures are x86compatible, adhering to standard paging mechanisms.
The MMU also contains a load/store unit that is responsible for scheduling cache and external memory accesses. The load/store unit incorporates two performanceenhancing features:
•Load-store reordering that gives memory reads required by the integer unit a priority over writes to external memory.
•Memory-read bypassing that eliminates unnecessary memory reads by using valid data from the execution unit.
1.5INTERNAL BUS INTERFACE UNIT
The internal bus interface unit provides a bridge from the GXLV processor to the integrated system functions (i.e., memory subsystem, display controller, graphics pipeline) and the PCI bus interface.
When external memory access is required, the physical address is calculated by the memory management unit and then passed to the internal bus interface unit, which translates the cycle to an X-Bus cycle (the X-Bus is a proprietary internal bus which provides a common interface for all of the integrated functions). The X-Bus memory cycle is arbitrated between other pending X-Bus memory requests to the SDRAM controller before completing.
In addition, the internal bus interface unit provides configuration control for up to 20 different regions within system memory with separate controls for read access, write access, cacheability, and PCI access.
Series Processor GXLV Geode™
Revision 1.1 |
11 |
www.national.com |
Geode™ GXLV Processor Series
Architecture Overview (Continued)
1.6INTEGRATED FUNCTIONS
The GXLV processor integrates the following functions traditionally implemented using external devices:
•High-performance 2D graphics accelerator
•Separate CRT and TFT control from the display controller
•SDRAM memory controller
•PCI bridge
The processor has also been enhanced to support VSA technology implementation.
The GXLV processor implements a Unified Memory Architecture (UMA). By using DCT (Display Compression Technology) architecture, the performance degradation inherent in traditional UMA systems is eliminated.
1.6.1Graphics Accelerator
The graphics accelerator is a full-featured GUI accelerator. The graphics pipeline implements a bitBLT engine for frame buffer bitBLTs and rectangular fills. Additional instructions in the integer unit may be processed, as the bitBLT engine assists the CPU in the bitBLT operations that take place between system memory and the frame buffer. This combination of hardware and software is used by the display driver to provide very fast bidirectional transfers between system memory and the frame buffer. The bitBLT engine also draws randomly oriented vectors, and scanlines for polygon fill. All of the pipeline operations described in the following list can be applied to any bitBLT operation.
•Pattern Memory: Render with 8x8 dither, 8x8 monochrome, or 8x1 color pattern.
•Color Expansion: Expand monochrome bitmaps to full depth 8- or 16-bit colors.
•Transparency: Suppresses drawing of background pixels for transparent text.
•Raster Operations: Boolean operation combines source, destination, and pattern bitmaps.
1.6.2Display Controller
The display port is a direct interface to the Geode I/O companion (i.e., CS5530, part number 25420-03) which drives a TFT flat panel display, LCD panel, or a CRT display.
The display controller (video generator) retrieves image data from the frame buffer, performs a color-look-up if required, inserts the cursor overlay into the pixel stream, generates display timing, and formats the pixel data for output to a variety of display devices. The display controller contains DCT architecture that allows the GXLV processor to refresh the display from a compressed copy of the frame buffer. DCT architecture typically decreases the screen refresh bandwidth requirement by a factor of 15 to 20, minimizing bandwidth contention.
1.6.3XpressRAM Memory Subsystem
The memory controller drives a 64-bit SDRAM port directly. The SDRAM memory array contains both the main system memory and the graphics frame buffer. Up to four module banks of SDRAM are supported. Each module bank can have two or four component banks depending on the memory size and organization. The maximum configuration is four module banks with four component banks, each providing a total of 16 open banks. The maximum memory size is 256 MB.
The memory controller handles multiple requests for memory data from the GXLV processor, the graphics accelerator and the display controller. The memory controller contains extensive buffering logic that helps minimize contention for memory bandwidth between graphics and CPU requests. The memory controller cooperates with the internal bus controller to determine the cacheability of all memory references.
1.6.4PCI Controller
The GXLV processor incorporates a full-function PCI interface module that includes the PCI arbiter. All accesses to external I/O devices are sent over the PCI bus, although most memory accesses are serviced by the SDRAM controller. The internal bus interface unit contains address mapping logic that determines if memory accesses are targeted for the SDRAM or for the PCI bus.
www.national.com |
12 |
Revision 1.1 |
Architecture Overview (Continued)
1.7 GEODE GXLV/CS5530 SYSTEM DESIGNS
A GXLV processor and Geode CS5530 I/O companion based design provides high performance using 32-bit x86 processing. The two chips integrate video, audio and memory interface functions normally performed by external hardware. The CS5530 enables the full features of the GXLV processor with MMX support. These features include full VGA and VESA video, 16-bit stereo sound, IDE interface, ISA interface, SMM power management, and IBM’s AT compatibility logic. In addition, the CS5530 provides an Ultra DMA/33 interface, MPEG1 assist, and AC97 Version 2.0 compliant audio.
Figure 1-2 shows a basic block system diagram which also includes the Geode CS9210 graphics companion for
designs that need to interface to a Dual Scan Super Twisted Pneumatic (DSTN) panel (instead of a TFT panel).
Figure 1-3 shows an example of a CS9210 interface in a typical GXLV/CS5530 based system design. The CS9210 converts the digital RGB output of the CS5530 to the digital output suitable for driving a color DSTN flat panel LCD. It can drive all standard color DSTN flat panels up to a 1024x768 resolution.
Figures 1-4 and 1-5 show the signal connections between the GXLV processor and the CS5530. For connections to the CS9210, refer to the CS9210 data book.
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Figure 1-2. Geode™ GXLV/CS5530 System Block Diagram
Series Processor GXLV Geode™
Revision 1.1 |
13 |
www.national.com |
Geode™ GXLV Processor Series
Architecture Overview (Continued)
.
Pixel Data 18
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Figure 1-3. Geode™ CS9210 Interface System Diagram |
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DCLK |
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DCLK |
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Exclusive |
CRT_HSYNC |
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HSYNC |
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CRT_VSYNC |
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VSYNC |
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Interconnect |
(Note) |
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PIXEL[17:0] |
PIXEL[23:0] |
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Signals |
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Not needed if |
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(Do not connect to |
FP_HSYNC |
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FP_HSYNC |
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any other device) |
FP_VSYNC |
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FP_VSYNC CRT only (no TFT) |
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ENA_DISP |
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ENA_DISP |
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VID_VAL |
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VID_VAL |
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VID_CLK |
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VID_CLK |
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VID_DATA[7:0] |
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VID_DATA[7:0] |
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VID_RDY |
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VID_RDY |
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RESET |
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CPU_RST |
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Geode™ GXLV |
INTR |
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INTR |
Geode™ CS5530 |
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Processor |
SUSP# |
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SUSP# |
I/O Companion |
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SUSPA# |
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SUSPA# |
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AD[31:0] |
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AD[31:0] |
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C/BE[3:0]# |
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C/BE[3:0]# |
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Nonexclusive |
PAR |
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PAR |
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FRAME# |
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FRAME# |
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Interconnect |
IRDY# |
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IRDY# |
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Signals |
TRDY# |
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TRDY# |
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(May also connect |
STOP# |
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STOP# |
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to other circuitry) |
LOCK# |
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LOCK# |
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DEVSEL# |
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PERR# |
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PERR# |
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SERR# |
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SERR# |
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REQ0# |
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REQ# |
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GNT0# |
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GNT# |
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Note: Refer to Figure 1-5 for interconnection of the pixel lines.
Figure 1-4. Geode™ GXLV/CS5530 Signal Connections
www.national.com |
14 |
Revision 1.1 |
Architecture Overview (Continued) |
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GXLVGeode™ |
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Geode™ GXLV |
PIXEL17 |
PIXEL23 |
Geode™ CS5530 |
Processor |
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PIXEL16 |
PIXEL22 |
I/O Companion |
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Processor |
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PIXEL15 |
PIXEL21 |
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R |
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PIXEL14 |
PIXEL20 |
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PIXEL13 |
PIXEL19 |
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Series |
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PIXEL12 |
PIXEL18 |
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PIXEL17 |
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PIXEL16 |
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PIXEL11 |
PIXEL15 |
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PIXEL10 |
PIXEL14 |
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G |
PIXEL9 |
PIXEL13 |
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PIXEL8 |
PIXEL12 |
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PIXEL7 |
PIXEL11 |
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PIXEL6 |
PIXEL10 |
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PIXEL9 |
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PIXEL8 |
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PIXEL5 |
PIXEL7 |
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PIXEL4 |
PIXEL6 |
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B |
PIXEL3 |
PIXEL5 |
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PIXEL2 |
PIXEL4 |
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PIXEL1 |
PIXEL3 |
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PIXEL0 |
PIXEL2 |
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PIXEL1 |
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PIXEL0 |
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Figure 1-5. PIXEL Signal Connections |
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||
Revision 1.1 |
|
15 |
www.national.com |
|
Geode™ GXLV Processor Series
Architecture Overview (Continued)
1.7.1Reference Designs
As described previously, the GXLV series of integrated processors is designed specifically to work with National’s Geode I/O and graphics companion devices. To help define and drive the emerging information appliance market, several reference systems have been developed by National Semiconductor. These GXLV processor based reference systems provide optimized and targeted solu-
tions for three main segments of the information appliance market: Personal Internet Access, Thin Client, and Settop Box. Contact your local National Semiconductor sales or field support representative for further information on reference designs for the information appliance market.
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Control |
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GXLV |
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NSC |
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LM4549 |
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PCMCIA |
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Codec |
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PCI Bus |
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Embedded OS |
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Embedded OS |
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Linear |
Applications |
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Flash |
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Applications |
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Flash |
Bootloader |
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Bootloader |
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Card |
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RF Interface |
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(8 MB) |
Run-Time Diagnostics |
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Optional |
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Run-Time Diagnostics |
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Storage |
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Storage |
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ISA Bus
Geode™
Ultra DMA/33 CS5530
I/O
USB Port Companion
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Geode™ |
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Buttons |
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CS9210/11 |
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DSTN |
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Graphics |
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Pwr Mgmt |
Microcontroller |
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Backlight |
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Companion |
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DC Sense |
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Li Batteries/ |
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Touch |
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Charger |
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Control |
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512 KB DRAM |
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Figure 1-6. Example WebPAD™ System Diagram
www.national.com |
16 |
Revision 1.1 |
Architecture Overview (Continued) |
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|
GXLVGeode™ |
||
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TFT |
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USB (2x) |
Processor |
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CRT |
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SDRAM SO-DIMM |
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Series |
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Geode™ |
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Video |
Geode™ |
NSC |
MIC In |
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CS5530 |
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GXLV |
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LM4546 |
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I/O |
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Processor |
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PCI Bus |
Codec |
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Companion |
Audio Out |
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NSC |
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Termination |
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DP83815 |
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ISA Bus |
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Ethernet |
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Termination |
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Controller |
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64 MB Flash |
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NSC |
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PC97317IBW/VUL |
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SuperI/O |
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Reset |
CPU Core |
Clock |
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Generator |
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|||
PWR CTL |
Power |
Power |
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MK1491-06 |
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Figure 1-7. Example Thin Client System Diagram |
|
|||
Revision 1.1 |
|
|
17 |
|
www.national.com |
Geode™ GXLV Processor Series
Architecture Overview (Continued)
CPU Temp.
Sensor
NSC
LM75
Geode™
GXLV
Processor
SDRAM DIMM |
|
SDRAM DIMM |
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AC3 |
MIC MIC |
PCI Bus |
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Anlg |
1 |
2 |
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IN |
IN |
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DMA
Arbiter
PCI Slot
Riser Slot
Optional
LAN PCI
LAN /
Card
WAN
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C-CUBE |
IGS 50x5 |
VGA |
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Headphone |
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SDRAM |
S-Video |
|||
LM4548 |
“ZIVA” |
Graphics |
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Output |
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PAL or |
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Audio Line |
Codec |
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NTSC |
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Output |
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Geode™ |
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SGRAM |
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Tuner |
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CS5530 |
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Optional |
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SGRAM |
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FM In |
CD In |
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I/O |
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V .90 |
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Companion |
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Modem |
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Video Port |
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ISA Slot |
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Composite |
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SAA7112 |
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Riser Slot |
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Video In |
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Flash |
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ISA Bus |
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CATV In |
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TV Tuner |
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BIOS |
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TV |
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2.5” UDMA-33 |
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ROM Slot |
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9638 |
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Tuner |
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SPDIF |
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Hard Drive |
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WinCE ROM |
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Audio |
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TDA9851 |
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AC3 |
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Digital |
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Line |
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Out |
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Notebook DVD |
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Notebook |
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NSC |
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Floppy |
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PC97317VUL-ICF |
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Drive |
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Drive |
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SuperI/O |
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PCM1723 |
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Tuner FM Out |
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Internal Assembly Options |
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LPT |
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Mouse |
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Front |
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TDA8006 |
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AC3 |
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(IR) |
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Panel |
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Anlg |
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Smartcard |
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COM |
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Keybd |
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USB |
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(IR) |
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Ports |
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Figure 1-8. Example Set-Top Box System Diagram
www.national.com |
18 |
Revision 1.1 |
2.0 Signal Definitions
This section describes the external interface of the Geode |
by their functional interface groups (internal test and elec- |
GXLV processor. Figure 2-1 shows the signals organized |
trical pins are not shown). |
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SYSCLK |
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MD[63:0] |
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CLKMODE[2:0] |
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MA[12:0] |
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System |
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RESET |
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BA[1:0] |
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INTR |
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RASA#, RASB# |
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Interface |
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IRQ13 |
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CASA#, CASB# |
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Memory |
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Signals |
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SMI# |
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CS[3:0]# |
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Controller |
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SUSP# |
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WEA#, WEB# |
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Interface |
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SUSPA# |
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DQM[7:0] |
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SERIALP |
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CKEA, CKEB |
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Signals |
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Geode™ |
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SDCLK[3:0] |
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AD[31:0] |
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SDCLK_IN |
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GXLV |
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SDCLK_OUT |
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C/BE[3:0]# |
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PAR |
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Processor |
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PCLK |
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FRAME# |
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VID_CLK |
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IRDY# |
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DCLK |
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PCI |
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TRDY# |
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CRT_HSYNC |
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Interface |
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STOP# |
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CRT_VSYNC |
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Video |
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LOCK# |
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FP_HSYNC |
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Interface |
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DEVSEL# |
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FP_VSYNC |
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Signals |
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PERR# |
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ENA_DISP |
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SERR# |
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VID_RDY |
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REQ[2:0]# |
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VID_VAL |
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GNT[2:0]# |
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VID_DATA[7:0] |
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PIXEL[17:0] |
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Figure 2-1. Functional Block Diagram |
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|
Series Processor GXLV Geode™
Revision 1.1 |
19 |
www.national.com |
Geode™ GXLV Processor Series
Signal Definitions (Continued)
2.1PIN ASSIGNMENTS
The tables in this section use several common abbreviations. Table 2-1 lists the mnemonics and their meanings.
Figure 2-2 shows the pin assignment for the 352 BGA with Table 2-2 and Table 2-3 listing the pin assignments sorted by pin number and alphabetically by signal name, respectively.
Figure 2-3 shows the pin assignment for the 320 SPGA with Table 2-4 and Table 2-5 listing the pin assignments sorted by pin number and alphabetically by signal name, respectively.
In Section 2.2 “Signal Descriptions” on page 31 a description of each signal is provided within its associated functional group.
Table 2-1. Pin Type Definitions
Mnemonic |
Definition |
|
|
I |
Standard input pin. |
|
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I/O |
Bidirectional pin. |
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|
O |
Totem-pole output. |
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|
OD |
Open-drain output structure that |
|
allows multiple devices to share the |
|
pin in a wired-OR configuration. |
|
|
PU |
Pull-up resistor. |
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|
PD |
Pull-down resistor. |
|
|
s/t/s |
Sustained tri-state an active-low tri- |
|
state signal owned and driven by |
|
one and only one agent at a time. |
|
The agent that drives an s/t/s pin low |
|
must drive it high for at least one |
|
clock before letting it float. A new |
|
agent cannot start driving an s/t/s |
|
signal any sooner than one clock |
|
after the previous owner lets it float. |
|
A pull-up resistor on the mother- |
|
board is required to sustain the inac- |
|
tive state until another agent drives |
|
it. |
|
|
VCC (PWR) |
Power pin. |
|
|
VSS (GND) |
Ground pin. |
|
|
# |
The "#" symbol at the end of a signal |
|
name indicates that the active, or |
|
asserted state occurs when the sig- |
|
nal is at a low voltage level. When |
|
"#" is not present after the signal |
|
name, the signal is asserted when at |
|
a high voltage level. |
|
|
t/s |
Tri-state signal. |
|
|
www.national.com |
20 |
Revision 1.1 |
Signal Definitions (Continued)
Index Corner
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
A |
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
A |
VSS |
VSS |
AD27 |
AD24 |
AD21 |
AD16 |
VCC2 |
FRAM# |
DEVS# |
VCC3 |
PERR# |
AD15 |
VSS |
AD11 |
CBE0# |
AD6 |
VCC2 |
AD4 |
AD2 |
VCC3 |
AD0 |
AD1 |
TEST2 |
MD2 |
VSS |
VSS |
B |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B |
VSS |
VSS |
AD28 |
AD25 |
AD22 |
AD18 |
VCC2 |
CBE2# |
TRDY# |
VCC3 |
LOCK# |
PAR |
AD14 |
AD12 |
AD9 |
AD7 |
VCC2 |
INTR |
AD3 |
VCC3 |
TEST1 |
TEST3 |
MD1 |
MD33 |
VSS |
VSS |
C |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C |
AD29 |
AD31 |
AD30 |
AD26 |
AD23 |
AD19 |
VCC2 |
AD17 |
IRDY# |
VCC3 |
STOP# |
SERR# |
CBE1# |
AD13 |
AD10 |
AD8 |
VCC2 |
AD5 |
SMI# |
VCC3 |
TEST0 |
IRQ13 |
MD32 |
MD34 |
MD3 |
MD35 |
D |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
D |
GNT0# |
TDI |
REQ2# |
VSS |
CBE3# |
VSS |
VCC2 |
VSS |
VSS |
VCC3 |
VSS |
VSS |
VSS |
VSS |
VSS |
VSS |
VCC2 |
VSS |
VSS |
VCC3 |
VSS |
MD0 |
VSS |
MD4 |
MD36 |
NC |
E |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
E |
GNT2# SUSPA# REQ0# |
AD20 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MD6 |
NC |
MD5 |
MD37 |
||
F |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
F |
TD0 |
GNT1# |
TEST |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
MD38 |
MD7 |
MD39 |
G |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
G |
VCC3 |
VCC3 |
VCC3 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
VCC3 |
VCC3 |
VCC3 |
H |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H |
TMS |
SUSP# |
REQ1# |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
MD8 |
MD40 |
MD9 |
J |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
J |
FPVSY |
TCLK |
RESET |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
MD41 |
MD10 |
MD42 |
K |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
K |
VCC2 |
VCC2 |
VCC2 |
VCC2 |
|
|
|
|
|
|
Geode™ |
|
|
|
|
|
|
|
VCC2 |
VCC2 |
VCC2 |
VCC2 |
||||
L |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
|||||
CKM1 |
FPHSY |
SERLP |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
MD11 |
MD43 |
MD12 |
|||||
M |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
M |
|||||
|
|
|
|
|
|
|
|
|
|
GXLV |
|
|
|
|
|
|
|
|
|
|
|||||
CKM2 |
VIDVAL |
CKM0 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
MD44 |
MD13 |
MD45 |
||||
N |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
N |
||||
VSS |
PIX1 |
PIX0 |
VSS |
|
|
|
|
|
|
Processor |
|
|
|
|
|
|
VSS |
MD14 |
MD46 |
MD15 |
|||||
P |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P |
||||||
VIDCLK |
PIX3 |
PIX2 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
MD47 |
CASA# SYSCLK |
|
R |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
R |
PIX4 |
PIX5 |
PIX6 |
VSS |
|
|
|
|
352 BGA - Top View |
|
|
|
|
VSS |
WEB# |
WEA# |
CASB# |
|||||||||
T |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
T |
||||||||||
PIX7 |
PIX8 |
PIX9 |
VSS |
|
|
|
|
|
|
|
|
VSS |
DQM0 |
DQM4 |
DQM1 |
||||||||||
U |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U |
VCC3 |
VCC3 |
VCC3 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
VCC3 |
VCC3 |
VCC3 |
V |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
V |
PIX10 |
PIX11 |
PIX12 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
DQM5 |
CS2# |
CS0# |
W |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
W |
PIX13 |
CRTHSY |
PIX14 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
RASA# |
RASB# |
MA0 |
Y |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Y |
VCC2 |
VCC2 |
VCC2 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
VCC2 |
VCC2 |
VCC2 |
AA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AA |
PIX15 |
PIX16 |
CRTVSY |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
MA1 |
MA2 |
MA3 |
AB |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB |
DCLK |
PIX17 |
VDAT6 |
VDAT7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MA4 |
MA5 |
MA6 |
MA7 |
AC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC |
PCLK |
FLT# |
VDAT4 |
VSS |
NC |
VSS |
VCC2 |
VSS |
VSS |
VCC3 |
VSS |
VSS |
VSS |
VSS |
VSS |
VSS |
VCC2 |
VSS |
VSS |
VCC3 |
VSS |
DQM6 |
VSS |
MA8 |
MA9 |
MA10 |
AD |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD |
VRDY |
VDAT5 |
VDAT3 |
VDAT0 |
EDISP |
MD63 |
VCC2 |
MD62 |
MD29 |
VCC3 |
MD59 |
MD26 |
MD56 |
MD55 |
MD22 |
CKEB |
VCC2 |
MD51 |
MD18 |
VCC3 |
MD48 |
DQM3 |
CS1# |
MA11 |
BA0 |
BA1 |
AE |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AE |
VSS |
VSS |
VDAT2 |
SCLK3 |
SCLK1 |
RWCLK |
VCC2 |
SCKIN |
MD61 |
VCC3 |
MD28 |
MD58 |
MD25 |
MD24 |
MD54 |
MD21 |
VCC2 |
MD20 |
MD50 |
VCC3 |
MD17 |
DQM7 |
CS3# |
MA12 |
VSS |
VSS |
AF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AF |
VSS |
VSS |
VDAT1 |
SCLK0 |
SCLK2 |
MD31 |
VCC2 SCKOUT MD30 |
VCC3 |
MD60 |
MD27 |
MD57 |
VSS |
MD23 |
MD53 |
VCC2 |
MD52 |
MD19 |
VCC3 |
MD49 |
MD16 |
DQM2 |
CKEA |
VSS |
VSS |
||
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
Note: Signal names have been abbreviated in this figure due to space constraints.
= GND terminal
= PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)
Figure 2-2. 352 BGA Pin Assignment Diagram
For order information, refer to Section A.1 “Order Information” on page 246.
Series Processor GXLV Geode™
Revision 1.1 |
21 |
www.national.com |
Geode™ GXLV Processor Series
Signal Definitions (Continued)
Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number
Pin |
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A1 |
VSS |
|
B23 |
MD1 |
|
D19 |
VSS |
|
K1 |
VCC2 |
|
T1 |
PIXEL7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A2 |
VSS |
|
B24 |
MD33 |
|
D20 |
VCC3 |
|
K2 |
VCC2 |
|
T2 |
PIXEL8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A3 |
AD27 |
|
B25 |
VSS |
|
D21 |
VSS |
|
K3 |
VCC2 |
|
T3 |
PIXEL9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A4 |
AD24 |
|
B26 |
VSS |
|
D22 |
MD0 |
|
K4 |
VCC2 |
|
T4 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A5 |
AD21 |
|
C1 |
AD29 |
|
D23 |
VSS |
|
K23 |
VCC2 |
|
T23 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A6 |
AD16 |
|
C2 |
AD31 |
|
D24 |
MD4 |
|
K24 |
VCC2 |
|
T24 |
DQM0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A7 |
VCC2 |
|
C3 |
AD30 |
|
D25 |
MD36 |
|
K25 |
VCC2 |
|
T25 |
DQM4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A8 |
FRAME# |
|
C4 |
AD26 |
|
D26 |
NC |
|
K26 |
VCC2 |
|
T26 |
DQM1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A9 |
DEVSEL# |
|
C5 |
AD23 |
|
E1 |
GNT2# |
|
L1 |
CLKMODE1 |
|
U1 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A10 |
VCC3 |
|
C6 |
AD19 |
|
E2 |
SUSPA# |
|
L2 |
FP_HSYNC |
|
U2 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A11 |
PERR# |
|
C7 |
VCC2 |
|
E3 |
REQ0# |
|
L3 |
SERIALP |
|
U3 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A12 |
AD15 |
|
C8 |
AD17 |
|
E4 |
AD20 |
|
L4 |
VSS |
|
U4 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A13 |
VSS |
|
C9 |
IRDY# |
|
E23 |
MD6 |
|
L23 |
VSS |
|
U23 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A14 |
AD11 |
|
C10 |
VCC3 |
|
E24 |
NC |
|
L24 |
MD11 |
|
U24 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A15 |
C/BE0# |
|
C11 |
STOP# |
|
E25 |
MD5 |
|
L25 |
MD43 |
|
U25 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A16 |
AD6 |
|
C12 |
SERR# |
|
E26 |
MD37 |
|
L26 |
MD12 |
|
U26 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A17 |
VCC2 |
|
C13 |
C/BE1# |
|
F1 |
TDO |
|
M1 |
CLKMODE2 |
|
V1 |
PIXEL10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A18 |
AD4 |
|
C14 |
AD13 |
|
F2 |
GNT1# |
|
M2 |
VID_VAL |
|
V2 |
PIXEL11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A19 |
AD2 |
|
C15 |
AD10 |
|
F3 |
TEST |
|
M3 |
CLKMODE0 |
|
V3 |
PIXEL12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A20 |
VCC3 |
|
C16 |
AD8 |
|
F4 |
VSS |
|
M4 |
VSS |
|
V4 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A21 |
AD0 |
|
C17 |
VCC2 |
|
F23 |
VSS |
|
M23 |
VSS |
|
V23 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A22 |
AD1 |
|
C18 |
AD5 |
|
F24 |
MD38 |
|
M24 |
MD44 |
|
V24 |
DQM5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A23 |
TEST2 |
|
C19 |
SMI# |
|
F25 |
MD7 |
|
M25 |
MD13 |
|
V25 |
CS2# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A24 |
MD2 |
|
C20 |
VCC3 |
|
F26 |
MD39 |
|
M26 |
MD45 |
|
V26 |
CS0# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A25 |
VSS |
|
C21 |
TEST0 |
|
G1 |
VCC3 |
|
N1 |
VSS |
|
W1 |
PIXEL13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A26 |
VSS |
|
C22 |
IRQ13 |
|
G2 |
VCC3 |
|
N2 |
PIXEL1 |
|
W2 |
CRT_HSYNC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B1 |
VSS |
|
C23 |
MD32 |
|
G3 |
VCC3 |
|
N3 |
PIXEL0 |
|
W3 |
PIXEL14 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B2 |
VSS |
|
C24 |
MD34 |
|
G4 |
VCC3 |
|
N4 |
VSS |
|
W4 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B3 |
AD28 |
|
C25 |
MD3 |
|
G23 |
VCC3 |
|
N23 |
VSS |
|
W23 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B4 |
AD25 |
|
C26 |
MD35 |
|
G24 |
VCC3 |
|
N24 |
MD14 |
|
W24 |
RASA# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B5 |
AD22 |
|
D1 |
GNT0# |
|
G25 |
VCC3 |
|
N25 |
MD46 |
|
W25 |
RASB# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B6 |
AD18 |
|
D2 |
TDI |
|
G26 |
VCC3 |
|
N26 |
MD15 |
|
W26 |
MA0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B7 |
VCC2 |
|
D3 |
REQ2# |
|
H1 |
TMS |
|
P1 |
VID_CLK |
|
Y1 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B8 |
C/BE2# |
|
D4 |
VSS |
|
H2 |
SUSP# |
|
P2 |
PIXEL3 |
|
Y2 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B9 |
TRDY# |
|
D5 |
C/BE3# |
|
H3 |
REQ1# |
|
P3 |
PIXEL2 |
|
Y3 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B10 |
VCC3 |
|
D6 |
VSS |
|
H4 |
VSS |
|
P4 |
VSS |
|
Y4 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B11 |
LOCK# |
|
D7 |
VCC2 |
|
H23 |
VSS |
|
P23 |
VSS |
|
Y23 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B12 |
PAR |
|
D8 |
VSS |
|
H24 |
MD8 |
|
P24 |
MD47 |
|
Y24 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B13 |
AD14 |
|
D9 |
VSS |
|
H25 |
MD40 |
|
P25 |
CASA# |
|
Y25 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B14 |
AD12 |
|
D10 |
VCC3 |
|
H26 |
MD9 |
|
P26 |
SYSCLK |
|
Y26 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B15 |
AD9 |
|
D11 |
VSS |
|
J1 |
FP_VSYNC |
|
R1 |
PIXEL4 |
|
AA1 |
PIXEL15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B16 |
AD7 |
|
D12 |
VSS |
|
J2 |
TCLK |
|
R2 |
PIXEL5 |
|
AA2 |
PIXEL16 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B17 |
VCC2 |
|
D13 |
VSS |
|
J3 |
RESET |
|
R3 |
PIXEL6 |
|
AA3 |
CRT_VSYNC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B18 |
INTR |
|
D14 |
VSS |
|
J4 |
VSS |
|
R4 |
VSS |
|
AA4 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B19 |
AD3 |
|
D15 |
VSS |
|
J23 |
VSS |
|
R23 |
VSS |
|
AA23 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B20 |
VCC3 |
|
D16 |
VSS |
|
J24 |
MD41 |
|
R24 |
WEB# |
|
AA24 |
MA1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B21 |
TEST1 |
|
D17 |
VCC2 |
|
J25 |
MD10 |
|
R25 |
WEA# |
|
AA25 |
MA2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B22 |
TEST3 |
|
D18 |
VSS |
|
J26 |
MD42 |
|
R26 |
CASB# |
|
AA26 |
MA3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
www.national.com |
22 |
Revision 1.1 |
Signal Definitions (Continued)
Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number (Continued)
Pin |
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB1 |
DCLK |
|
AC16 |
VSS |
|
AD13 |
MD56 |
|
AE10 |
VCC3 |
|
AF7 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB2 |
PIXEL17 |
|
AC17 |
VCC2 |
|
AD14 |
MD55 |
|
AE11 |
MD28 |
|
AF8 |
SDCLK_OUT |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB3 |
VID_DATA6 |
|
AC18 |
VSS |
|
AD15 |
MD22 |
|
AE12 |
MD58 |
|
AF9 |
MD30 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB4 |
VID_DATA7 |
|
AC19 |
VSS |
|
AD16 |
CKEB |
|
AE13 |
MD25 |
|
AF10 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB23 |
MA4 |
|
AC20 |
VCC3 |
|
AD17 |
VCC2 |
|
AE14 |
MD24 |
|
AF11 |
MD60 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB24 |
MA5 |
|
AC21 |
VSS |
|
AD18 |
MD51 |
|
AE15 |
MD54 |
|
AF12 |
MD27 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB25 |
MA6 |
|
AC22 |
DQM6 |
|
AD19 |
MD18 |
|
AE16 |
MD21 |
|
AF13 |
MD57 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB26 |
MA7 |
|
AC23 |
VSS |
|
AD20 |
VCC3 |
|
AE17 |
VCC2 |
|
AF14 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC1 |
PCLK |
|
AC24 |
MA8 |
|
AD21 |
MD48 |
|
AE18 |
MD20 |
|
AF15 |
MD23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC2 |
FLT# |
|
AC25 |
MA9 |
|
AD22 |
DQM3 |
|
AE19 |
MD50 |
|
AF16 |
MD53 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC3 |
VID_DATA4 |
|
AC26 |
MA10 |
|
AD23 |
CS1# |
|
AE20 |
VCC3 |
|
AF17 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC4 |
VSS |
|
AD1 |
VID_RDY |
|
AD24 |
MA11 |
|
AE21 |
MD17 |
|
AF18 |
MD52 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC5 |
NC |
|
AD2 |
VID_DATA5 |
|
AD25 |
BA0 |
|
AE22 |
DQM7 |
|
AF19 |
MD19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC6 |
VSS |
|
AD3 |
VID_DATA3 |
|
AD26 |
BA1 |
|
AE23 |
CS3# |
|
AF20 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC7 |
VCC2 |
|
AD4 |
VID_DATA0 |
|
AE1 |
VSS |
|
AE24 |
MA12 |
|
AF21 |
MD49 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC8 |
VSS |
|
AD5 |
ENA_DISP |
|
AE2 |
VSS |
|
AE25 |
VSS |
|
AF22 |
MD16 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC9 |
VSS |
|
AD6 |
MD63 |
|
AE3 |
VID_DATA2 |
|
AE26 |
VSS |
|
AF23 |
DQM2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC10 |
VCC3 |
|
AD7 |
VCC2 |
|
AE4 |
SDCLK3 |
|
AF1 |
VSS |
|
AF24 |
CKEA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC11 |
VSS |
|
AD8 |
MD62 |
|
AE5 |
SDCLK1 |
|
AF2 |
VSS |
|
AF25 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC12 |
VSS |
|
AD9 |
MD29 |
|
AE6 |
RW_CLK |
|
AF3 |
VID_DATA1 |
|
AF26 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC13 |
VSS |
|
AD10 |
VCC3 |
|
AE7 |
VCC2 |
|
AF4 |
SDCLK0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC14 |
VSS |
|
AD11 |
MD59 |
|
AE8 |
SDCLK_IN |
|
AF5 |
SDCLK2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC15 |
VSS |
|
AD12 |
MD26 |
|
AE9 |
MD61 |
|
AF6 |
MD31 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Series Processor GXLV Geode™
Revision 1.1 |
23 |
www.national.com |
Geode™ GXLV Processor Series
Signal Definitions (Continued)
Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name
Signal Name |
Type |
Pin No. |
|
Signal Name |
Type |
Pin No. |
|
Signal Name |
Type |
Pin No. |
|
Signal Name |
Type |
Pin No. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD0 |
I/O |
A21 |
|
DQM0 |
O |
T24 |
|
MD20 |
I/O |
AE18 |
|
PIXEL3 |
O |
P2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD1 |
I/O |
A22 |
|
DQM1 |
O |
T26 |
|
MD21 |
I/O |
AE16 |
|
PIXEL4 |
O |
R1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD2 |
I/O |
A19 |
|
DQM2 |
O |
AF23 |
|
MD22 |
I/O |
AD15 |
|
PIXEL5 |
O |
R2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD3 |
I/O |
B19 |
|
DQM3 |
O |
AD22 |
|
MD23 |
I/O |
AF15 |
|
PIXEL6 |
O |
R3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD4 |
I/O |
A18 |
|
DQM4 |
O |
T25 |
|
MD24 |
I/O |
AE14 |
|
PIXEL7 |
O |
T1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD5 |
I/O |
C18 |
|
DQM5 |
O |
V24 |
|
MD25 |
I/O |
AE13 |
|
PIXEL8 |
O |
T2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD6 |
I/O |
A16 |
|
DQM6 |
O |
AC22 |
|
MD26 |
I/O |
AD12 |
|
PIXEL9 |
O |
T3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD7 |
I/O |
B16 |
|
DQM7 |
O |
AE22 |
|
MD27 |
I/O |
AF12 |
|
PIXEL10 |
O |
V1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD8 |
I/O |
C16 |
|
ENA_DISP |
O |
AD5 |
|
MD28 |
I/O |
AE11 |
|
PIXEL11 |
O |
V2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD9 |
I/O |
B15 |
|
FLT# |
I |
AC2 |
|
MD29 |
I/O |
AD9 |
|
PIXEL12 |
O |
V3 |
AD10 |
I/O |
C15 |
|
FP_HSYNC |
O |
L2 |
|
MD30 |
I/O |
AF9 |
|
PIXEL13 |
O |
W1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD11 |
I/O |
A14 |
|
FP_VSYNC |
O |
J1 |
|
MD31 |
I/O |
AF6 |
|
PIXEL14 |
O |
W3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD12 |
I/O |
B14 |
|
FRAME# |
s/t/s |
A8 (PU) |
|
MD32 |
I/O |
C23 |
|
PIXEL15 |
O |
AA1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD13 |
I/O |
C14 |
|
GNT0# |
O |
D1 |
|
MD33 |
I/O |
B24 |
|
PIXEL16 |
O |
AA2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD14 |
I/O |
B13 |
|
GNT1# |
O |
F2 |
|
MD34 |
I/O |
C24 |
|
PIXEL17 |
O |
AB2 |
AD15 |
I/O |
A12 |
|
GNT2# |
O |
E1 |
|
MD35 |
I/O |
C26 |
|
RASA# |
O |
W24 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD16 |
I/O |
A6 |
|
INTR |
I |
B18 |
|
MD36 |
I/O |
D25 |
|
RASB# |
O |
W25 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD17 |
I/O |
C8 |
|
IRDY# |
s/t/s |
C9 (PU) |
|
MD37 |
I/O |
E26 |
|
REQ0# |
I |
E3 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD18 |
I/O |
B6 |
|
IRQ13 |
O |
C22 |
|
MD38 |
I/O |
F24 |
|
REQ1# |
I |
H3 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD19 |
I/O |
C6 |
|
LOCK# |
s/t/s |
B11 (PU) |
|
MD39 |
I/O |
F26 |
|
REQ2# |
I |
D3 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD20 |
I/O |
E4 |
|
MA0 |
O |
W26 |
|
MD40 |
I/O |
H25 |
|
RESET |
I |
J3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD21 |
I/O |
A5 |
|
MA1 |
O |
AA24 |
|
MD41 |
I/O |
J24 |
|
RW_CLK |
O |
AE6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD22 |
I/O |
B5 |
|
MA2 |
O |
AA25 |
|
MD42 |
I/O |
J26 |
|
SDCLK_IN |
I |
AE8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD23 |
I/O |
C5 |
|
MA3 |
O |
AA26 |
|
MD43 |
I/O |
L25 |
|
SDCLK_OUT |
O |
AF8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD24 |
I/O |
A4 |
|
MA4 |
O |
AB23 |
|
MD44 |
I/O |
M24 |
|
SDCLK0 |
O |
AF4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD25 |
I/O |
B4 |
|
MA5 |
O |
AB24 |
|
MD45 |
I/O |
M26 |
|
SDCLK1 |
O |
AE5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD26 |
I/O |
C4 |
|
MA6 |
O |
AB25 |
|
MD46 |
I/O |
N25 |
|
SDCLK2 |
O |
AF5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD27 |
I/O |
A3 |
|
MA7 |
O |
AB26 |
|
MD47 |
I/O |
P24 |
|
SDCLK3 |
O |
AE4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD28 |
I/O |
B3 |
|
MA8 |
O |
AC24 |
|
MD48 |
I/O |
AD21 |
|
SERIALP |
O |
L3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD29 |
I/O |
C1 |
|
MA9 |
O |
AC25 |
|
MD49 |
I/O |
AF21 |
|
SERR# |
OD |
C12 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD30 |
I/O |
C3 |
|
MA10 |
O |
AC26 |
|
MD50 |
I/O |
AE19 |
|
SMI# |
I |
C19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD31 |
I/O |
C2 |
|
MA11 |
O |
AD24 |
|
MD51 |
I/O |
AD18 |
|
STOP# |
s/t/s |
C11 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BA0 |
O |
AD25 |
|
MA12 |
O |
AE24 |
|
MD52 |
I/O |
AF18 |
|
SUSP# |
I |
H2 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BA1 |
O |
AD26 |
|
MD0 |
I/O |
D22 |
|
MD53 |
I/O |
AF16 |
|
SUSPA# |
O |
E2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CASA# |
O |
P25 |
|
MD1 |
I/O |
B23 |
|
MD54 |
I/O |
AE15 |
|
SYSCLK |
I |
P26 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CASB# |
O |
R26 |
|
MD2 |
I/O |
A24 |
|
MD55 |
I/O |
AD14 |
|
TCLK |
I |
J2 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE0# |
I/O |
A15 |
|
MD3 |
I/O |
C25 |
|
MD56 |
I/O |
AD13 |
|
TDI |
I |
D2 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE1# |
I/O |
C13 |
|
MD4 |
I/O |
D24 |
|
MD57 |
I/O |
AF13 |
|
TDO |
O |
F1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE2# |
I/O |
B8 |
|
MD5 |
I/O |
E25 |
|
MD58 |
I/O |
AE12 |
|
TEST |
I |
F3 (PD) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE3# |
I/O |
D5 |
|
MD6 |
I/O |
E23 |
|
MD59 |
I/O |
AD11 |
|
TEST0 |
O |
C21 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CKEA |
O |
AF24 |
|
MD7 |
I/O |
F25 |
|
MD60 |
I/O |
AF11 |
|
TEST1 |
O |
B21 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CKEB |
O |
AD16 |
|
MD8 |
I/O |
H24 |
|
MD61 |
I/O |
AE9 |
|
TEST2 |
O |
A23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKMODE0 |
I |
M3 |
|
MD9 |
I/O |
H26 |
|
MD62 |
I/O |
AD8 |
|
TEST3 |
O |
B22 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKMODE1 |
I |
L1 |
|
MD10 |
I/O |
J25 |
|
MD63 |
I/O |
AD6 |
|
TMS |
I |
H1 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKMODE2 |
I |
M1 |
|
MD11 |
I/O |
L24 |
|
NC |
-- |
D26 |
|
TRDY# |
s/t/s |
B9 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CRT_HSYNC |
O |
W2 |
|
MD12 |
I/O |
L26 |
|
NC |
-- |
E24 |
|
VCC2 |
PWR |
A7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CRT_VSYNC |
O |
AA3 |
|
MD13 |
I/O |
M25 |
|
NC |
-- |
AC5 |
|
VCC2 |
PWR |
A17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS0# |
O |
V26 |
|
MD14 |
I/O |
N24 |
|
PAR |
I/O |
B12 |
|
VCC2 |
PWR |
B7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS1# |
O |
AD23 |
|
MD15 |
I/O |
N26 |
|
PCLK |
O |
AC1 |
|
VCC2 |
PWR |
B17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS2# |
O |
V25 |
|
MD16 |
I/O |
AF22 |
|
PERR# |
s/t/s |
A11 (PU) |
|
VCC2 |
PWR |
C7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS3# |
O |
AE23 |
|
MD17 |
I/O |
AE21 |
|
PIXEL0 |
O |
N3 |
|
VCC2 |
PWR |
C17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DCLK |
I |
AB1 |
|
MD18 |
I/O |
AD19 |
|
PIXEL1 |
O |
N2 |
|
VCC2 |
PWR |
D7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DEVSEL# |
s/t/s |
A9 (PU) |
|
MD19 |
I/O |
AF19 |
|
PIXEL2 |
O |
P3 |
|
VCC2 |
PWR |
D17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
www.national.com |
24 |
Revision 1.1 |
Signal Definitions (Continued)
Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)
Signal Name |
Type |
Pin No. |
|
Signal Name |
Type |
Pin No. |
|
Signal Name |
Type |
Pin No. |
|
Signal Name |
Type |
Pin No. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K1 |
|
VCC3 |
PWR |
G23 |
|
VSS |
GND |
B1 |
|
VSS |
GND |
T23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K2 |
|
VCC3 |
PWR |
G24 |
|
VSS |
GND |
B2 |
|
VSS |
GND |
V4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K3 |
|
VCC3 |
PWR |
G25 |
|
VSS |
GND |
B25 |
|
VSS |
GND |
V23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K4 |
|
VCC3 |
PWR |
G26 |
|
VSS |
GND |
B26 |
|
VSS |
GND |
W4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K23 |
|
VCC3 |
PWR |
U1 |
|
VSS |
GND |
D4 |
|
VSS |
GND |
W23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K24 |
|
VCC3 |
PWR |
U2 |
|
VSS |
GND |
D6 |
|
VSS |
GND |
AA4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K25 |
|
VCC3 |
PWR |
U3 |
|
VSS |
GND |
D8 |
|
VSS |
GND |
AA23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K26 |
|
VCC3 |
PWR |
U4 |
|
VSS |
GND |
D9 |
|
VSS |
GND |
AC4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
Y1 |
|
VCC3 |
PWR |
U23 |
|
VSS |
GND |
D11 |
|
VSS |
GND |
AC6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
Y2 |
|
VCC3 |
PWR |
U24 |
|
VSS |
GND |
D12 |
|
VSS |
GND |
AC8 |
VCC2 |
PWR |
Y3 |
|
VCC3 |
PWR |
U25 |
|
VSS |
GND |
D13 |
|
VSS |
GND |
AC9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
Y4 |
|
VCC3 |
PWR |
U26 |
|
VSS |
GND |
D14 |
|
VSS |
GND |
AC11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
Y23 |
|
VCC3 |
PWR |
AC10 |
|
VSS |
GND |
D15 |
|
VSS |
GND |
AC12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
Y24 |
|
VCC3 |
PWR |
AC20 |
|
VSS |
GND |
D16 |
|
VSS |
GND |
AC13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
Y25 |
|
VCC3 |
PWR |
AD10 |
|
VSS |
GND |
D18 |
|
VSS |
GND |
AC14 |
VCC2 |
PWR |
Y26 |
|
VCC3 |
PWR |
AD20 |
|
VSS |
GND |
D19 |
|
VSS |
GND |
AC15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AC7 |
|
VCC3 |
PWR |
AE10 |
|
VSS |
GND |
D21 |
|
VSS |
GND |
AC16 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AC17 |
|
VCC3 |
PWR |
AE20 |
|
VSS |
GND |
D23 |
|
VSS |
GND |
AC18 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AD7 |
|
VCC3 |
PWR |
AF10 |
|
VSS |
GND |
F4 |
|
VSS |
GND |
AC19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AD17 |
|
VCC3 |
PWR |
AF20 |
|
VSS |
GND |
F23 |
|
VSS |
GND |
AC21 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AE7 |
|
VID_CLK |
O |
P1 |
|
VSS |
GND |
H4 |
|
VSS |
GND |
AC23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AE17 |
|
VID_DATA0 |
O |
AD4 |
|
VSS |
GND |
H23 |
|
VSS |
GND |
AE1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AF7 |
|
VID_DATA1 |
O |
AF3 |
|
VSS |
GND |
J4 |
|
VSS |
GND |
AE2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AF17 |
|
VID_DATA2 |
O |
AE3 |
|
VSS |
GND |
J23 |
|
VSS |
GND |
AE25 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
PWR |
A10 |
|
VID_DATA3 |
O |
AD3 |
|
VSS |
GND |
L4 |
|
VSS |
GND |
AE26 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
PWR |
A20 |
|
VID_DATA4 |
O |
AC3 |
|
VSS |
GND |
L23 |
|
VSS |
GND |
AF1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
PWR |
B10 |
|
VID_DATA5 |
O |
AD2 |
|
VSS |
GND |
M4 |
|
VSS |
GND |
AF2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
PWR |
B20 |
|
VID_DATA6 |
O |
AB3 |
|
VSS |
GND |
M23 |
|
VSS |
GND |
AF14 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
PWR |
C10 |
|
VID_DATA7 |
O |
AB4 |
|
VSS |
GND |
N1 |
|
VSS |
GND |
AF25 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
PWR |
C20 |
|
VID_RDY |
I |
AD1 |
|
VSS |
GND |
N4 |
|
VSS |
GND |
AF26 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
PWR |
D10 |
|
VID_VAL |
O |
M2 |
|
VSS |
GND |
N23 |
|
WEA# |
O |
R25 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
PWR |
D20 |
|
VSS |
GND |
A1 |
|
VSS |
GND |
P4 |
|
WEB# |
O |
R24 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
PWR |
G1 |
|
VSS |
GND |
A2 |
|
VSS |
GND |
P23 |
|
Note: PU/PD indicates pin is |
||
VCC3 |
PWR |
G2 |
|
VSS |
GND |
A13 |
|
VSS |
GND |
R4 |
|
internally connected to a |
||
VCC3 |
PWR |
G3 |
|
VSS |
GND |
A25 |
|
VSS |
GND |
R23 |
|
weak (> 20-kohm) pull- |
||
|
|
|
|
|
|
|
|
|
|
|
|
up/-down resistor. |
||
VCC3 |
PWR |
G4 |
|
VSS |
GND |
A26 |
|
VSS |
GND |
T4 |
||||
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Series Processor GXLV Geode™
Revision 1.1 |
25 |
www.national.com |
Geode™ GXLV Processor Series
Signal Definitions (Continued)
Index Corner |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1 |
2 |
3 |
|
4 |
5 |
|
6 |
|
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
|
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
28 |
29 |
30 |
31 |
32 |
33 |
34 |
35 |
36 |
37 |
|
A |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A |
|
|
VCC3 |
|
AD25 |
|
|
|
VSS |
|
VCC2 |
AD16 |
VCC3 |
STOP# |
SERR# |
VSS |
|
AD11 |
|
AD8 |
|
VCC3 |
|
AD2 |
|
VCC2 |
|
VSS |
TEST0 |
|
VCC3 |
|
VSS |
|||||||||
B |
VSS |
|
|
AD27 |
CBE3# |
|
AD21 |
|
AD19 |
CBE2# |
TRDY# |
LOCK# |
CBE1# |
AD13 |
|
AD9 |
|
AD6 |
|
AD3 |
|
SMI# |
|
AD1 |
|
TEST2 |
MD33 |
|
MD2 |
B |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||||||||||||||
C |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C |
VCC3 |
|
AD31 |
|
AD26 |
|
|
|
AD23 |
|
VCC2 |
AD18 |
FRAME# |
VSS |
|
|
PAR |
|
VCC3 |
|
AD10 |
|
VSS |
|
AD4 |
|
AD0 |
|
VCC2 |
|
IRQ13 |
|
MD1 |
|
MD34 |
|
VCC3 |
|||||
D |
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D |
AD30 |
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AD29 |
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AD24 |
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AD22 |
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AD20 |
|
AD17 |
|
IRDY# |
|
PERR# |
AD14 |
|
AD12 |
|
AD7 |
|
INTR |
|
TEST1 |
TEST3 |
|
MD0 |
|
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MD32 |
|
MD3 |
|
MD35 |
|
||||||
E |
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E |
REQ0# |
|
REQ2# |
AD28 |
|
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VSS |
|
VCC2 |
VCC2 |
|
VSS |
DEVSEL# |
|
AD15 |
|
VSS |
CBE0# |
AD5 |
|
VSS |
|
VCC2 |
|
VCC2 |
|
VSS |
|
MD4 |
|
MD36 |
|
NC |
||||||||
F |
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F |
GNT0# |
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TDI |
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MD5 |
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NC |
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G |
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G |
VSS |
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CKMD2 |
VSS |
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VSS |
|
MD37 |
|
VSS |
||
H |
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MD6 |
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MD38 |
H |
GNT2# |
SUSPA# |
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||||||
J |
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J |
TDO |
|
VSS |
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TEST |
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VCC2 |
|
VSS |
|
MD7 |
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K |
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MD39 |
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MD8 |
K |
REQ1# |
GNT1# |
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||||||
L |
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L |
VCC2 |
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VCC2 |
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VCC2 |
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VCC2 |
|
VCC2 |
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VCC2 |
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M |
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MD40 |
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MD9 |
M |
RESET |
SUSP# |
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||||||
N |
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N |
VCC3 |
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TMS |
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VSS |
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VSS |
|
MD41 |
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VCC3 |
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P |
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Geode™ |
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MD10 |
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MD42 |
P |
||||||
FPVSYNC |
|
TCLK |
NC |
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MD11 |
VSS |
MD43 |
|||||||||||
SERIALP |
VSS |
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|||||||||||||
Q |
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Q |
R |
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GXLV |
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MD44 |
|
MD12 |
R |
||||
CKMD1 |
FPHSYNC |
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|||||||||||
S |
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S |
|||||
CKMD0 |
VID_VAL |
PIX0 |
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MD14 |
|
MD13 |
|
MD45 |
|||
T |
PIX1 |
VCC3 |
PIX2 |
VSS |
|
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|
Processor |
|
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VSS |
MD15 |
VCC3 |
MD46 |
T |
|||||||||
VSS |
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VSS |
||||||||||||||||||
U |
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U |
V |
PIX3 |
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VID_CLK |
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SYSCLK |
MD47 |
V |
||||
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||||||||
W |
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W |
PIX6 |
|
PIX5 |
|
PIX4 |
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|
320 SPGA - Top View |
|
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WEA# |
|
WEB# |
CASA# |
||||||||||||||||||
Y |
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Y |
|||||||||||||||||
X |
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X |
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NC |
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PIX9 |
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|
DQM0 |
CASB# |
|||
PIX8 |
|
VSS |
|
PIX7 |
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DQM1 |
|
VSS |
|
DQM4 |
|
Z |
NC |
|
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PIX10 |
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CS2# |
|
DQM5 |
Z |
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|||||
AA |
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AA |
VCC3 |
|
PIX11 |
|
VSS |
|
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VSS |
|
CS0# |
|
VCC3 |
|
AB |
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AB |
PIX12 |
|
PIX13 |
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|
RASB# RASA# |
|||||||
AC |
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AC |
VCC2 |
|
VCC2 |
|
VCC2 |
|
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VCC2 |
|
VCC2 |
|
VCC2 |
|
AD |
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MA2 |
|
MA0 |
AD |
CRTHSYNC |
|
DCLK |
|
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|||||
AE |
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AE |
PIX14 |
|
VSS |
|
VCC2 |
|
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VCC2 |
|
VSS |
|
MA1 |
|
AF |
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MA4 |
|
MA3 |
AF |
PIX15 |
|
PIX16 |
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|||||
AG |
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AG |
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||
VSS |
|
PIX17 |
|
VSS |
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VSS |
|
MA5 |
|
VSS |
|
AH |
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MA10 |
|
MA8 |
|
MA6 |
AH |
CRTVSYNC |
VDAT6 |
|
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|||||||
AJ |
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|
AJ |
PCLK |
|
FLT# |
|
VDAT5 |
|
|
VSS |
|
VCC2 |
MD31 |
|
VSS |
|
MD60 |
MD57 |
|
VSS |
|
MD22 |
|
MD52 |
|
VSS |
|
VCC2 |
|
VCC2 |
|
VSS |
|
BA1 |
|
MA9 |
|
MA7 |
||||||
AK |
|
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|
AK |
VRDY |
|
VSS |
VDAT0 |
SDCLK0 SDCLK2 |
SDCLKIN |
MD29 |
|
MD27 |
|
MD56 |
|
MD55 |
|
MD21 |
|
MD20 |
|
MD50 |
|
MD16 |
|
DQM3 |
CS3# |
|
VSS |
|
BA0 |
|
|||||||||||||
AL |
|
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AL |
VCC2 |
|
VDAT4 |
VDAT2 |
SDCLK1 |
VCC2 |
RWCLK SDCLKOUT |
VSS |
|
MD58 |
|
VCC3 |
|
MD23 |
|
VSS |
|
MD19 |
|
MD49 |
|
VCC2 |
|
DQM6 |
|
CKEA |
|
MA11 |
|
VCC3 |
||||||||||||
AM |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AM |
VDAT7 |
VDAT3 |
ENDIS |
SDCLK3 |
MD63 |
|
MD30 |
|
MD61 |
|
MD59 |
|
MD25 |
|
MD24 |
|
MD53 |
|
MD51 |
|
MD18 |
|
MD48 |
|
DQM7 |
DQM2 |
|
MA12 |
|
NC |
|
|||||||||||
AN |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AN |
VSS |
|
VCC2 |
|
VDAT1 |
|
|
VSS |
|
VCC2 |
MD62 |
VCC3 |
|
MD28 |
MD26 |
|
VSS |
|
MD54 |
|
CKEB |
|
VCC3 |
|
MD17 |
|
VCC2 |
|
VSS |
|
CS1# |
|
VCC3 |
|
VSS |
|||||||
1 |
2 |
3 |
|
4 |
5 |
|
6 |
|
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
|
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
28 |
29 |
30 |
31 |
32 |
33 |
34 |
35 |
36 |
37 |
Note: Signal names have been abbreviated in this figure due to space constraints.
= Denotes GND terminal
= Denotes PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)
Figure 2-3. 320 SPGA Pin Assignment Diagram
For order information, refer to Section A.1 “Order Information” on page 246.
www.national.com |
26 |
Revision 1.1 |
Signal Definitions (Continued)
Table 2-4. 320 SPGA Pin Assignments - Sorted by Pin Number
Pin |
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A3 |
VCC3 |
|
C25 |
AD4 |
|
G1 |
VSS |
|
R34 |
MD44 |
|
AB2 |
PIXEL12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A5 |
AD25 |
|
C27 |
AD0 |
|
G3 |
CLKMODE2 |
|
R36 |
MD12 |
|
AB4 |
PIXEL13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A7 |
VSS |
|
C29 |
VCC2 |
|
G5 |
VSS |
|
S1 |
CLKMODE0 |
|
AB34 |
RASB# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A9 |
VCC2 |
|
C31 |
IRQ13 |
|
G33 |
VSS |
|
S3 |
VID_VAL |
|
AB36 |
RASA# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A11 |
AD16 |
|
C33 |
MD1 |
|
G35 |
MD37 |
|
S5 |
PIXEL0 |
|
AC1 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A13 |
VCC3 |
|
C35 |
MD34 |
|
G37 |
VSS |
|
S33 |
MD14 |
|
AC3 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A15 |
STOP# |
|
C37 |
VCC3 |
|
H2 |
GNT2# |
|
S35 |
MD13 |
|
AC5 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A17 |
SERR# |
|
D2 |
AD30 |
|
H4 |
SUSPA# |
|
S37 |
MD45 |
|
AC33 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A19 |
VSS |
|
D4 |
AD29 |
|
H34 |
MD6 |
|
T2 |
PIXEL1 |
|
AC35 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A21 |
AD11 |
|
D6 |
AD24 |
|
H36 |
MD38 |
|
T4 |
PIXEL2 |
|
AC37 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A23 |
AD8 |
|
D8 |
AD22 |
|
J1 |
TDO |
|
T34 |
MD15 |
|
AD2 |
CRT_HSYNC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A25 |
VCC3 |
|
D10 |
AD20 |
|
J3 |
VSS |
|
T36 |
MD46 |
|
AD4 |
DCLK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A27 |
AD2 |
|
D12 |
AD17 |
|
J5 |
TEST |
|
U1 |
VSS |
|
AD34 |
MA2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A29 |
VCC2 |
|
D14 |
IRDY# |
|
J33 |
VCC2 |
|
U3 |
VCC3 |
|
AD36 |
MA0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A31 |
VSS |
|
D16 |
PERR# |
|
J35 |
VSS |
|
U5 |
VSS |
|
AE1 |
PIXEL14 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A33 |
TEST0 |
|
D18 |
AD14 |
|
J37 |
MD7 |
|
U33 |
VSS |
|
AE3 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A35 |
VCC3 |
|
D20 |
AD12 |
|
K2 |
REQ1# |
|
U35 |
VCC3 |
|
AE5 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A37 |
VSS |
|
D22 |
AD7 |
|
K4 |
GNT1# |
|
U37 |
VSS |
|
AE33 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B2 |
VSS |
|
D24 |
INTR |
|
K34 |
MD39 |
|
V2 |
PIXEL3 |
|
AE35 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B4 |
AD27 |
|
D26 |
TEST1 |
|
K36 |
MD8 |
|
V4 |
VID_CLK |
|
AE37 |
MA1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B6 |
C/BE3# |
|
D28 |
TEST3 |
|
L1 |
VCC2 |
|
V34 |
SYSCLK |
|
AF2 |
PIXEL15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B8 |
AD21 |
|
D30 |
MD0 |
|
L3 |
VCC2 |
|
V36 |
MD47 |
|
AF4 |
PIXEL16 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B10 |
AD19 |
|
D32 |
MD32 |
|
L5 |
VCC2 |
|
W1 |
PIXEL6 |
|
AF34 |
MA4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B12 |
C/BE2# |
|
D34 |
MD3 |
|
L33 |
VCC2 |
|
W3 |
PIXEL5 |
|
AF36 |
MA3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B14 |
TRDY# |
|
D36 |
MD35 |
|
L35 |
VCC2 |
|
W5 |
PIXEL4 |
|
AG1 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B16 |
LOCK# |
|
E1 |
REQ0# |
|
L37 |
VCC2 |
|
W33 |
WEA# |
|
AG3 |
PIXEL17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B18 |
C/BE1# |
|
E3 |
REQ2# |
|
M2 |
RESET |
|
W35 |
WEB# |
|
AG5 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B20 |
AD13 |
|
E5 |
AD28 |
|
M4 |
SUSP# |
|
W37 |
CASA# |
|
AG33 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B22 |
AD9 |
|
E7 |
VSS |
|
M34 |
MD40 |
|
X2 |
NC |
|
AG35 |
MA5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B24 |
AD6 |
|
E9 |
VCC2 |
|
M36 |
MD9 |
|
X4 |
PIXEL9 |
|
AG37 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B26 |
AD3 |
|
E11 |
VCC2 |
|
N1 |
VCC3 |
|
X34 |
DQM0 |
|
AH2 |
CRT_VSYNC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B28 |
SMI# |
|
E13 |
VSS |
|
N3 |
TMS |
|
X36 |
CASB# |
|
AH4 |
VID_DATA6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B30 |
AD1 |
|
E15 |
DEVSEL# |
|
N5 |
VSS |
|
Y1 |
PIXEL8 |
|
AH32 |
MA10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B32 |
TEST2 |
|
E17 |
AD15 |
|
N33 |
VSS |
|
Y3 |
VSS |
|
AH34 |
MA8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B34 |
MD33 |
|
E19 |
VSS |
|
N35 |
MD41 |
|
Y5 |
PIXEL7 |
|
AH36 |
MA6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B36 |
MD2 |
|
E21 |
C/BE0# |
|
N37 |
VCC3 |
|
Y33 |
DQM1 |
|
AJ1 |
PCLK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C1 |
VCC3 |
|
E23 |
AD5 |
|
P2 |
FP_VSYNC |
|
Y35 |
VSS |
|
AJ3 |
FLT# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C3 |
AD31 |
|
E25 |
VSS |
|
P4 |
TCLK |
|
Y37 |
DQM4 |
|
AJ5 |
VID_DATA5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C5 |
AD26 |
|
E27 |
VCC2 |
|
P34 |
MD10 |
|
Z2 |
NC |
|
AJ7 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C7 |
AD23 |
|
E29 |
VCC2 |
|
P36 |
MD42 |
|
Z4 |
PIXEL10 |
|
AJ9 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C9 |
VCC2 |
|
E31 |
VSS |
|
Q1 |
SERIALP |
|
Z34 |
CS2# |
|
AJ11 |
MD31 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C11 |
AD18 |
|
E33 |
MD4 |
|
Q3 |
VSS |
|
Z36 |
DQM5 |
|
AJ13 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C13 |
FRAME# |
|
E35 |
MD36 |
|
Q5 |
NC |
|
AA1 |
VCC3 |
|
AJ15 |
MD60 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C15 |
VSS |
|
E37 |
NC |
|
Q33 |
MD11 |
|
AA3 |
PIXEL11 |
|
AJ17 |
MD57 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C17 |
PAR |
|
F2 |
GNT0# |
|
Q35 |
VSS |
|
AA5 |
VSS |
|
AJ19 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C19 |
VCC3 |
|
F4 |
TDI |
|
Q37 |
MD43 |
|
AA33 |
VSS |
|
AJ21 |
MD22 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C21 |
AD10 |
|
F34 |
MD5 |
|
R2 |
CLKMODE1 |
|
AA35 |
CS0# |
|
AJ23 |
MD52 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C23 |
VSS |
|
F36 |
NC |
|
R4 |
FP_HSYNC |
|
AA37 |
VCC3 |
|
AJ25 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Series Processor GXLV Geode™
Revision 1.1 |
27 |
www.national.com |
Geode™ GXLV Processor Series
Signal Definitions (Continued)
|
Table 2-4. |
320 SPGA Pin Assignments - Sorted by Pin Number (Continued) |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AJ27 |
VCC2 |
|
AK24 |
MD20 |
|
AL21 |
MD23 |
|
AM18 |
MD25 |
|
AN15 |
MD28 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AJ29 |
VCC2 |
|
AK26 |
MD50 |
|
AL23 |
VSS |
|
AM20 |
MD24 |
|
AN17 |
MD26 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AJ31 |
VSS |
|
AK28 |
MD16 |
|
AL25 |
MD19 |
|
AM22 |
MD53 |
|
AN19 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AJ33 |
BA1 |
|
AK30 |
DQM3 |
|
AL27 |
MD49 |
|
AM24 |
MD51 |
|
AN21 |
MD54 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AJ35 |
MA9 |
|
AK32 |
CS3# |
|
AL29 |
VCC2 |
|
AM26 |
MD18 |
|
AN23 |
CKEB |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AJ37 |
MA7 |
|
AK34 |
VSS |
|
AL31 |
DQM6 |
|
AM28 |
MD48 |
|
AN25 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK2 |
VID_RDY |
|
AK36 |
BA0 |
|
AL33 |
CKEA |
|
AM30 |
DQM7 |
|
AN27 |
MD17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK4 |
VSS |
|
AL1 |
VCC2 |
|
AL35 |
MA11 |
|
AM32 |
DQM2 |
|
AN29 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK6 |
VID_DATA0 |
|
AL3 |
VID_DATA4 |
|
AL37 |
VCC3 |
|
AM34 |
MA12 |
|
AN31 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK8 |
SDCLK0 |
|
AL5 |
VID_DATA2 |
|
AM2 |
VID_DATA7 |
|
AM36 |
NC |
|
AN33 |
CS1# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK10 |
SDCLK2 |
|
AL7 |
SDCLK1 |
|
AM4 |
VID_DATA3 |
|
AN1 |
VSS |
|
AN35 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK12 |
SDCLK_IN |
|
AL9 |
VCC2 |
|
AM6 |
ENA_DISP |
|
AN3 |
VCC2 |
|
AN37 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK14 |
MD29 |
|
AL11 |
RW_CLK |
|
AM8 |
SDCLK3 |
|
AN5 |
VID_DATA1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK16 |
MD27 |
|
AL13 |
SDCLK_OUT |
|
AM10 |
MD63 |
|
AN7 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK18 |
MD56 |
|
AL15 |
VSS |
|
AM12 |
MD30 |
|
AN9 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK20 |
MD55 |
|
AL17 |
MD58 |
|
AM14 |
MD61 |
|
AN11 |
MD62 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK22 |
MD21 |
|
AL19 |
VCC3 |
|
AM16 |
MD59 |
|
AN13 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
www.national.com |
28 |
Revision 1.1 |
Signal Definitions (Continued)
Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name
Signal Name |
Type |
Pin. No. |
|
Signal Name |
Type |
Pin. No. |
|
Signal Name |
Type |
Pin. No. |
|
Signal Name |
Type |
Pin. No. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD0 |
I/O |
C27 |
|
DQM0 |
O |
X34 |
|
MD20 |
I/O |
AK24 |
|
PIXEL0 |
O |
S5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD1 |
I/O |
B30 |
|
DQM1 |
O |
Y33 |
|
MD21 |
I/O |
AK22 |
|
PIXEL1 |
O |
T2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD2 |
I/O |
A27 |
|
DQM2 |
O |
AM32 |
|
MD22 |
I/O |
AJ21 |
|
PIXEL2 |
O |
T4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD3 |
I/O |
B26 |
|
DQM3 |
O |
AK30 |
|
MD23 |
I/O |
AL21 |
|
PIXEL3 |
O |
V2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD4 |
I/O |
C25 |
|
DQM4 |
O |
Y37 |
|
MD24 |
I/O |
AM20 |
|
PIXEL4 |
O |
W5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD5 |
I/O |
E23 |
|
DQM5 |
O |
Z36 |
|
MD25 |
I/O |
AM18 |
|
PIXEL5 |
O |
W3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD6 |
I/O |
B24 |
|
DQM6 |
O |
AL31 |
|
MD26 |
I/O |
AN17 |
|
PIXEL6 |
O |
W1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD7 |
I/O |
D22 |
|
DQM7 |
O |
AM30 |
|
MD27 |
I/O |
AK16 |
|
PIXEL7 |
O |
Y5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD8 |
I/O |
A23 |
|
ENA_DISP |
O |
AM6 |
|
MD28 |
I/O |
AN15 |
|
PIXEL8 |
O |
Y1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD9 |
I/O |
B22 |
|
FLT# |
I |
AJ3 |
|
MD29 |
I/O |
AK14 |
|
PIXEL9 |
O |
X4 |
AD10 |
I/O |
C21 |
|
FP_HSYNC |
O |
R4 |
|
MD30 |
I/O |
AM12 |
|
PIXEL10 |
O |
Z4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD11 |
I/O |
A21 |
|
FP_VSYNC |
O |
P2 |
|
MD31 |
I/O |
AJ11 |
|
PIXEL11 |
O |
AA3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD12 |
I/O |
D20 |
|
FRAME# |
s/t/s |
C13 (PU) |
|
MD32 |
I/O |
D32 |
|
PIXEL12 |
O |
AB2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD13 |
I/O |
B20 |
|
GNT0# |
O |
F2 |
|
MD33 |
I/O |
B34 |
|
PIXEL13 |
O |
AB4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD14 |
I/O |
D18 |
|
GNT1# |
O |
K4 |
|
MD34 |
I/O |
C35 |
|
PIXEL14 |
O |
AE1 |
AD15 |
I/O |
E17 |
|
GNT2# |
O |
H2 |
|
MD35 |
I/O |
D36 |
|
PIXEL15 |
O |
AF2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD16 |
I/O |
A11 |
|
INTR |
I |
D24 |
|
MD36 |
I/O |
E35 |
|
PIXEL16 |
O |
AF4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD17 |
I/O |
D12 |
|
IRDY# |
s/t/s |
D14 (PU) |
|
MD37 |
I/O |
G35 |
|
PIXEL17 |
O |
AG3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD18 |
I/O |
C11 |
|
IRQ13 |
O |
C31 |
|
MD38 |
I/O |
H36 |
|
RASA# |
O |
AB36 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD19 |
I/O |
B10 |
|
LOCK# |
s/t/s |
B16 (PU) |
|
MD39 |
I/O |
K34 |
|
RASB# |
O |
AB34 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD20 |
I/O |
D10 |
|
MA0 |
O |
AD36 |
|
MD40 |
I/O |
M34 |
|
REQ0# |
I |
E1 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD21 |
I/O |
B8 |
|
MA1 |
O |
AE37 |
|
MD41 |
I/O |
N35 |
|
REQ1# |
I |
K2 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD22 |
I/O |
D8 |
|
MA2 |
O |
AD34 |
|
MD42 |
I/O |
P36 |
|
REQ2# |
I |
E3 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD23 |
I/O |
C7 |
|
MA3 |
O |
AF36 |
|
MD43 |
I/O |
Q37 |
|
RESET |
I |
M2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD24 |
I/O |
D6 |
|
MA4 |
O |
AF34 |
|
MD44 |
I/O |
R34 |
|
RW_CLK |
O |
AL11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD25 |
I/O |
A5 |
|
MA5 |
O |
AG35 |
|
MD45 |
I/O |
S37 |
|
SDCLK_IN |
I |
AK12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD26 |
I/O |
C5 |
|
MA6 |
O |
AH36 |
|
MD46 |
I/O |
T36 |
|
SDCLK_OUT |
O |
AL13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD27 |
I/O |
B4 |
|
MA7 |
O |
AJ37 |
|
MD47 |
I/O |
V36 |
|
SDCLK0 |
O |
AK8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD28 |
I/O |
E5 |
|
MA8 |
O |
AH34 |
|
MD48 |
I/O |
AM28 |
|
SDCLK1 |
O |
AL7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD29 |
I/O |
D4 |
|
MA9 |
O |
AJ35 |
|
MD49 |
I/O |
AL27 |
|
SDCLK2 |
O |
AK10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD30 |
I/O |
D2 |
|
MA10 |
O |
AH32 |
|
MD50 |
I/O |
AK26 |
|
SDCLK3 |
O |
AM8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD31 |
I/O |
C3 |
|
MA11 |
O |
AL35 |
|
MD51 |
I/O |
AM24 |
|
SERIALP |
O |
Q1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BA0 |
O |
AK36 |
|
MA12 |
O |
AM34 |
|
MD52 |
I/O |
AJ23 |
|
SERR# |
OD |
A17 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BA1 |
O |
AJ33 |
|
MD0 |
I/O |
D30 |
|
MD53 |
I/O |
AM22 |
|
SMI# |
I |
B28 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CASA# |
O |
W37 |
|
MD1 |
I/O |
C33 |
|
MD54 |
I/O |
AN21 |
|
STOP# |
s/t/s |
A15 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CASB# |
O |
X36 |
|
MD2 |
I/O |
B36 |
|
MD55 |
I/O |
AK20 |
|
SUSP# |
I |
M4 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE0# |
I/O |
E21 |
|
MD3 |
I/O |
D34 |
|
MD56 |
I/O |
AK18 |
|
SUSPA# |
O |
H4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE1# |
I/O |
B18 |
|
MD4 |
I/O |
E33 |
|
MD57 |
I/O |
AJ17 |
|
SYSCLK |
I |
V34 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE2# |
I/O |
B12 |
|
MD5 |
I/O |
F34 |
|
MD58 |
I/O |
AL17 |
|
TCLK |
I |
P4 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE3# |
I/O |
B6 |
|
MD6 |
I/O |
H34 |
|
MD59 |
I/O |
AM16 |
|
TDI |
I |
F4 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CKEA |
O |
AL33 |
|
MD7 |
I/O |
J37 |
|
MD60 |
I/O |
AJ15 |
|
TDO |
O |
J1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CKEB |
O |
AN23 |
|
MD8 |
I/O |
K36 |
|
MD61 |
I/O |
AM14 |
|
TEST |
I |
J5 (PD) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKMODE0 |
I |
S1 |
|
MD9 |
I/O |
M36 |
|
MD62 |
I/O |
AN11 |
|
TEST0 |
O |
A33 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKMODE1 |
I |
R2 |
|
MD10 |
I/O |
P34 |
|
MD63 |
I/O |
AM10 |
|
TEST1 |
O |
D26 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKMODE2 |
I |
G3 |
|
MD11 |
I/O |
Q33 |
|
NC |
-- |
E37 |
|
TEST2 |
O |
B32 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CRT_HSYNC |
O |
AD2 |
|
MD12 |
I/O |
R36 |
|
NC |
-- |
F36 |
|
TEST3 |
O |
D28 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CRT_VSYNC |
O |
AH2 |
|
MD13 |
I/O |
S35 |
|
NC |
-- |
Q5 |
|
TMS |
I |
N3 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS0# |
O |
AA35 |
|
MD14 |
I/O |
S33 |
|
NC |
-- |
X2 |
|
TRDY# |
s/t/s |
B14 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS1# |
O |
AN33 |
|
MD15 |
I/O |
T34 |
|
NC |
-- |
Z2 |
|
VCC2 |
PWR |
A9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS2# |
O |
Z34 |
|
MD16 |
I/O |
AK28 |
|
NC |
-- |
AM36 |
|
VCC2 |
PWR |
A29 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS3# |
O |
AK32 |
|
MD17 |
I/O |
AN27 |
|
PAR |
I/O |
C17 |
|
VCC2 |
PWR |
C9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DCLK |
I |
AD4 |
|
MD18 |
I/O |
AM26 |
|
PCLK |
O |
AJ1 |
|
VCC2 |
PWR |
C29 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DEVSEL# |
s/t/s |
E15 (PU) |
|
MD19 |
I/O |
AL25 |
|
PERR# |
s/t/s |
D16 (PU) |
|
VCC2 |
PWR |
E9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Series Processor GXLV Geode™
Revision 1.1 |
29 |
www.national.com |
Geode™ GXLV Processor Series
Signal Definitions (Continued)
Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)
Signal Name |
Type |
Pin. No. |
|
Signal Name |
Type |
Pin. No. |
|
Signal Name |
Type |
Pin. No. |
|
Signal Name |
Type |
Pin. No. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
E11 |
|
VCC3 |
PWR |
A25 |
|
VSS |
GND |
A31 |
|
VSS |
GND |
AE35 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
E27 |
|
VCC3 |
PWR |
A35 |
|
VSS |
GND |
A37 |
|
VSS |
GND |
AG1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
E29 |
|
VCC3 |
PWR |
C1 |
|
VSS |
GND |
B2 |
|
VSS |
GND |
AG5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
J33 |
|
VCC3 |
PWR |
C19 |
|
VSS |
GND |
C15 |
|
VSS |
GND |
AG33 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
L1 |
|
VCC3 |
PWR |
C37 |
|
VSS |
GND |
C23 |
|
VSS |
GND |
AG37 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
L3 |
|
VCC3 |
PWR |
N1 |
|
VSS |
GND |
E7 |
|
VSS |
GND |
AJ7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
L5 |
|
VCC3 |
PWR |
N37 |
|
VSS |
GND |
E13 |
|
VSS |
GND |
AJ13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
L33 |
|
VCC3 |
PWR |
U3 |
|
VSS |
GND |
E19 |
|
VSS |
GND |
AJ19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
L35 |
|
VCC3 |
PWR |
U35 |
|
VSS |
GND |
E25 |
|
VSS |
GND |
AJ25 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
L37 |
|
VCC3 |
PWR |
AA1 |
|
VSS |
GND |
E31 |
|
VSS |
GND |
AJ31 |
VCC2 |
PWR |
AC1 |
|
VCC3 |
PWR |
AA37 |
|
VSS |
GND |
G1 |
|
VSS |
GND |
AK4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AC3 |
|
VCC3 |
PWR |
AL19 |
|
VSS |
GND |
G5 |
|
VSS |
GND |
AK34 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AC5 |
|
VCC3 |
PWR |
AL37 |
|
VSS |
GND |
G33 |
|
VSS |
GND |
AL15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AC33 |
|
VCC3 |
PWR |
AN13 |
|
VSS |
GND |
G37 |
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VSS |
GND |
AL23 |
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VCC2 |
PWR |
AC35 |
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VCC3 |
PWR |
AN25 |
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VSS |
GND |
J3 |
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VSS |
GND |
AN1 |
VCC2 |
PWR |
AC37 |
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VCC3 |
PWR |
AN35 |
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VSS |
GND |
J35 |
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VSS |
GND |
AN7 |
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VCC2 |
PWR |
AE5 |
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VID_CLK |
O |
V4 |
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VSS |
GND |
N5 |
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VSS |
GND |
AN19 |
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VCC2 |
PWR |
AE33 |
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VID_DATA0 |
O |
AK6 |
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VSS |
GND |
N33 |
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VSS |
GND |
AN31 |
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VCC2 |
PWR |
AJ9 |
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VID_DATA1 |
O |
AN5 |
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VSS |
GND |
Q3 |
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VSS |
GND |
AN37 |
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VCC2 |
PWR |
AJ27 |
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VID_DATA2 |
O |
AL5 |
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VSS |
GND |
Q35 |
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WEA# |
O |
W33 |
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VCC2 |
PWR |
AJ29 |
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VID_DATA3 |
O |
AM4 |
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VSS |
GND |
U1 |
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WEB# |
O |
W35 |
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VCC2 |
PWR |
AL1 |
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VID_DATA4 |
O |
AL3 |
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VSS |
GND |
U5 |
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Note: PU/PD indicates pin is |
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VCC2 |
PWR |
AL9 |
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VID_DATA5 |
O |
AJ5 |
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VSS |
GND |
U33 |
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internally connected to a |
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VCC2 |
PWR |
AL29 |
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VID_DATA6 |
O |
AH4 |
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VSS |
GND |
U37 |
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weak (> 20-kohm) |
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VCC2 |
PWR |
AN3 |
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VID_DATA7 |
O |
AM2 |
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VSS |
GND |
Y3 |
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pull-up/down resistor. |
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VCC2 |
PWR |
AN9 |
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VID_RDY |
I |
AK2 |
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VSS |
GND |
Y35 |
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VCC2 |
PWR |
AN29 |
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VID_VAL |
O |
S3 |
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VSS |
GND |
AA5 |
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VCC3 |
PWR |
A3 |
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VSS |
GND |
A7 |
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VSS |
GND |
AA33 |
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VCC3 |
PWR |
A13 |
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VSS |
GND |
A19 |
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VSS |
GND |
AE3 |
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30 |
Revision 1.1 |