June 2000
ADC08031/ADC08032/ADC08034/ADC08038 8-Bit High-Speed Serial I/O A/D Converters with
Multiplexer Options, Voltage Reference, and Track/Hold
Function
General Description
The ADC08031/ADC08032/ADC08034/ADC08038 are 8-bit successive approximation A/D converters with serial I/O and configurable input multiplexers with up to 8 channels. The serial I/O is configured to comply with the NSC MICROWIRE™ serial data exchange standard for easy interface to the COPS™ family of controllers, and can easily interface with standard shift registers or microprocessors.
The ADC08034 and ADC08038 provide a 2.6V band-gap derived reference. For devices offering guaranteed voltage reference performance over temperature see ADC08131, ADC08134 and ADC08138.
A track/hold function allows the analog voltage at the positive input to vary during the actual A/D conversion.
The analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differential modes. In addition, input voltage spans as small as 1V can be accommodated.
Applications
nDigitizing automotive sensors
nProcess control monitoring
nRemote sensing in noisy environments
nInstrumentation
nTest systems
nEmbedded diagnostics
Features
nSerial digital data link requires few I/O pins
nAnalog input track/hold function
n2-, 4-, or 8-channel input multiplexer options with address logic
n0V to 5V analog input range with single 5V power supply
nNo zero or full scale adjustment required
nTTL/CMOS input/output compatible
nOn chip 2.6V band-gap reference
n0.3" standard width 8-, 14-, or 20-pin DIP package
n14-, 20-pin small-outline packages
Key Specifications
nResolution: 8 bits
nConversion time (fC = 1 MHz): 8µs (max)
nPower dissipation: 20mW (max)
nSingle supply: 5VDC (±5%)
nTotal unadjusted error: ±1¤2 LSB and ±1LSB
nNo missing codes over temperature
Ordering Information
Industrial (−40ÊC ≤ TA ≤ +85ÊC) |
Package |
ADC08031CIN* |
N08E |
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ADC08038CIN* |
N20A |
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ADC08031CIWM, |
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ADC08032CIWM, |
M14B |
ADC08034CIWM |
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ADC08038CIWM |
M20B |
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*Not recomended for new designs.
COPS™ microcontrollers and MICROWIRE™ are trademarks of National Semiconductor Corporation.
with Converters A/D I/O Serial Speed-High Bit-8 ADC08031/ADC08032/ADC08034/ADC08038
Function Track/Hold and Reference, Voltage Options, Multiplexer
© 2000 National Semiconductor Corporation |
DS010555 |
www.national.com |
ADC08031/ADC08032/ADC08034/ADC08038
Connection Diagrams
ADC08038
DS010555-2
ADC08031
Dual-In-Line Package
DS010555-5
ADC08031
Small Outline Package
DS010555-31
ADC08034
DS010555-3
ADC08032
Small Outline Package
DS010555-30
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2 |
Absolute Maximum Ratings (Notes 1, 3)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) |
6.5V |
Voltage at Inputs and Outputs |
−0.3V to V CC + 0.3V |
Input Current at Any Pin (Note 4) |
±5 mA |
Package Input Current (Note 4) |
±20 mA |
Power Dissipation at TA = 25ÊC |
|
(Note 5) |
800 mW |
ESD Susceptibility (Note 6) |
1500V |
Soldering Information |
|
N Package (10 sec.) |
235ÊC |
SO Package: |
|
Vapor Phase (60 sec.) |
215ÊC |
Infrared (15 sec.) (Note 7) |
220ÊC |
Storage Temperature −65ÊC to +150ÊC
Operating Ratings (Notes 2, 3)
Temperature Range |
TMIN ≤ TA ≤ TMAX |
ADC08031BIN, ADC08031CIN, |
−40ÊC ≤ TA ≤ +85ÊC |
ADC08032BIN, ADC08032CIN, |
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ADC08034BIN, ADC08034CIN, |
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ADC08038BIN, ADC08038CIN, |
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ADC08031BIWM, ADC08032BIWM, |
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ADC08034BIWM, ADC08038BIWM |
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ADC08031CIWM, ADC08032CIWM, |
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ADC08034CIWM, ADC08038CIWM |
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Supply Voltage (VCC) |
4.5 VDC to 6.3 VDC |
Electrical Characteristics
The following specifications apply for VCC = VREF = +5 VDC, and fCLK = 1 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25ÊC.
Symbol |
Parameter |
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Conditions |
Typical |
Limits |
Units |
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(Note 8) |
(Note 9) |
(Limits) |
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CONVERTER AND MULTIPLEXER CHARACTERISTICS |
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Total Unadjusted Error |
(Note 10) |
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BIN, BIWM |
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± 1¤2 |
LSB (max) |
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CIN, CIWM |
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± 1 |
LSB (max) |
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Differential |
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8 |
Bits (min) |
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Linearity |
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RREF |
Reference Input Resistance |
(Note 11) |
3.5 |
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kΩ |
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1.3 |
kΩ (min) |
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6.0 |
kΩ (max) |
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VIN |
Analog Input Voltage |
(Note 12) |
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(VCC + 0.05) |
V (max) |
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(GND − 0.05) |
V (min) |
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DC Common-Mode Error |
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±1¤4 |
LSB (max) |
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Power Supply Sensitivity |
V |
= 5V ±5%, |
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± 1¤4 |
LSB (max) |
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CC |
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VREF = 4.75V |
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On Channel Leakage |
On Channel = 5V, |
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0.2 |
µA (max) |
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Current (Note 13) |
Off Channel = 0V |
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1 |
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On Channel = 0V, |
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−0.2 |
µA (max) |
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Off Channel = 5V |
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−1 |
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Off Channel Leakage |
On Channel = 5V, |
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−0.2 |
µA (max) |
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Current (Note 13) |
Off Channel = 0V |
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−1 |
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On Channel = 0V, |
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0.2 |
µA (max) |
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Off Channel = 5V |
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1 |
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DIGITAL AND DC CHARACTERISTICS |
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V |
Logical ª1º Input Voltage |
V |
= 5.25V |
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2.0 |
V (min) |
IN(1) |
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CC |
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V |
Logical ª0º Input Voltage |
V |
= 4.75V |
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0.8 |
V (max) |
IN(0) |
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CC |
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I |
Logical ª1º Input Current |
V |
= 5.0V |
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1 |
µA (max) |
IN(1) |
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IN |
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I |
Logical ª0º Input Current |
V |
= 0V |
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−1 |
µA (max) |
IN(0) |
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IN |
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V |
Logical ª1º Output Voltage |
V |
= 4.75V: |
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OUT(1) |
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CC |
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IOUT = −360 µA |
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2.4 |
V (min) |
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IOUT = −10 µA |
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4.5 |
V (min) |
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V |
Logical ª0º Output Voltage |
V |
= 4.75V |
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0.4 |
V (max) |
OUT(0) |
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CC |
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IOUT = 1.6 mA |
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ADC08031/ADC08032/ADC08034/ADC08038
3 |
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ADC08031/ADC08032/ADC08034/ADC08038
Electrical Characteristics (Continued)
The following specifications apply for VCC = VREF = +5 VDC, and fCLK = 1 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25ÊC.
Symbol |
Parameter |
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Conditions |
Typical |
Limits |
Units |
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(Note 8) |
(Note 9) |
(Limits) |
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DIGITAL AND DC CHARACTERISTICS |
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I |
TRI-STATE® Output Current |
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V |
OUT |
= 0V |
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−3.0 |
µA (max) |
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OUT |
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VOUT = 5V |
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3.0 |
µA (max) |
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ISOURCE |
Output Source Current |
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VOUT = 0V |
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−6.5 |
mA (min) |
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ISINK |
Output Sink Current |
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VOUT = VCC |
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8.0 |
mA (min) |
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ICC |
Supply Current |
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ADC08031, ADC08034, |
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3.0 |
mA (max) |
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CS |
= HIGH |
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and ADC08038 |
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ADC08032 (Note 16) |
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7.0 |
mA (max) |
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REFERENCE CHARACTERISTICS |
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VREFOUT |
Nominal Reference Output |
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VREFOUT Option |
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Available Only on |
2.6 |
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V |
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ADC08034 and |
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ADC08038 |
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Electrical Characteristics
The following specifications apply for VCC = VREF = +5 VDC, and tr = tf = 20 ns unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25ÊC.
Symbol |
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Parameter |
Conditions |
Typical |
Limits |
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Units |
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(Note 8) |
(Note 9) |
(Limits) |
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fCLK |
Clock Frequency |
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10 |
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kHz (min) |
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1 |
MHz (max) |
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Clock Duty Cycle |
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40 |
% (min) |
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(Note 14) |
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60 |
% (max) |
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TC |
Conversion Time (Not Including |
fCLK = 1 MHz |
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8 |
1/fCLK (max) |
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MUX Addressing Time) |
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8 |
µs (max) |
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t |
Acquisition Time |
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1¤2 |
1/f |
CLK |
(max) |
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CA |
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tSELECT |
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CLK High while |
CS |
is High |
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50 |
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ns |
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tSET-UP |
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25 |
ns (min) |
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CS |
Falling Edge or Data Input |
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Valid to CLK Rising Edge |
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tHOLD |
Data Input Valid after CLK |
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20 |
ns (min) |
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Rising Edge |
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tpd1, tpd0 |
CLK Falling Edge to Output |
CL = 100 pF: |
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Data Valid (Note 15) |
Data MSB First |
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250 |
ns (max) |
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Data LSB First |
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200 |
ns (max) |
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t1H, t0H |
TRI-STATE Delay from Rising Edge |
CL = 10 pF, RL = 10 kΩ |
50 |
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ns |
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of |
CS |
to Data Output and SARS Hi-Z |
(see TRI-STATE Test Circuits) |
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CL = 100 pF, RL = 2 kΩ |
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180 |
ns (max) |
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CIN |
Capacitance of Logic Inputs |
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5 |
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pF |
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COUT |
Capacitance of Logic Outputs |
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5 |
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pF |
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to AGND = DGND = 0 VDC, unless otherwise specified.
Note 4: When the input voltage VIN at any pin exceeds the power supplies (VIN < (AGND or DGND) or VIN > VCC) the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − T A)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For these de-
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4 |
Electrical Characteristics (Continued)
vices, TJMAX = 125ÊC. The typical thermal resistances (qJA) of these parts when board mounted follow: ADC08031 and ADC08032 with BIN and CIN suffixes 120ÊC/W, ADC08038 with CIN suffix 80ÊC/W. ADC08031 with CIWM suffix 140ÊC/W, ADC08032 140ÊC/W, ADC08034 140ÊC/W, ADC08038 with CIWM suffix 91ÊC/W.
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kW resistor.
Note 7: See AN450 ªSurface Mounting Methods and Their Effect on Product Reliabilityº or Linear Data Book section ªSurface Mountº for other methods of soldering surface mount devices.
Note 8: Typicals are at TJ = 25ÊC and represent the most likely parametric norm.
Note 9: Guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error includes offset, full-scale, linearity, multiplexer.
Note 11: Cannot be tested for the ADC08032.
Note 12: For VIN(−) ³ VIN(+) the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. During testing at low VCC levels (e.g., 4.5V), high level analog inputs
(e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode; this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading.
Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following two cases are considered: one, with the selected channel tied high (5 VDC) and the remaining seven off channels tied low (0 VDC), total current flow through the off channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 µs.
Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for comparator response time.
Note 16: For the ADC08032 VREFIN is internally tied to VCC, therefore, for the ADC08032 reference current is included in the supply current.
Typical Performance Characteristics
Linearity Error vs |
Linearity Error vs |
Linearity Error vs |
Reference Voltage |
Temperature |
Clock Frequency |
DS010555-32 DS010555-33 DS010555-34
Power Supply Current vs |
Output Current vs |
Power Supply Current |
Temperature (ADC08038, |
Temperature |
vs Clock Frequency |
ADC08034, ADC08031) |
|
|
DS010555-36 |
DS010555-37 |
DS010555-35
Note: For ADC08032 add IREF
ADC08031/ADC08032/ADC08034/ADC08038
5 |
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ADC08031/ADC08032/ADC08034/ADC08038
Leakage Current Test Circuit
DS010555-7
TRI-STATE Test Circuits and Waveforms
t1H
DS010555-38
DS010555-39
t0H
DS010555-41
DS010555-40
Timing Diagrams
Data Input Timing
DS010555-10
*To reset these devices, CLK and CS must be simultaneously high for a period of tSELECT or greater. Otherwise these devices are compatible with industry standards ADC0831/2/4/8.
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6 |
Timing Diagrams (Continued)
Data Output Timing
DS010555-11
ADC08031 Start Conversion Timing
DS010555-12
ADC08031 Timing
DS010555-13
*LSB first output not available on ADC08031.
LSB information is maintained for remainder of clock periods until CS goes high.
ADC08032 Timing
DS010555-14
ADC08031/ADC08032/ADC08034/ADC08038
7 |
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ADC08031/ADC08032/ADC08034/ADC08038
Timing Diagrams (Continued)
ADC08034 Timing
DS010555-15
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8 |