December 1994
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
8-Bit mP Compatible A/D Converters
General Description
The ADC0801, ADC0802, ADC0803, ADC0804 and ADC0805 are CMOS 8-bit successive approximation A/D converters that use a differential potentiometric ladderÐ similar to the 256R products. These converters are designed to allow operation with the NSC800 and INS8080A derivative control bus with TRI-STATEÉ output latches directly driving the data bus. These A/Ds appear like memory locations or I/O ports to the microprocessor and no interfacing logic is needed.
Differential analog voltage inputs allow increasing the com- mon-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.
YDifferential analog voltage inputs
YLogic inputs and outputs meet both MOS and TTL voltage level specifications
YWorks with 2.5V (LM336) voltage reference
YOn-chip clock generator
Y0V to 5V analog input voltage range with single 5V supply
YNo zero adjust required
Y0.3× standard width 20-pin DIP package
Y20-pin molded chip carrier or small outline package
YOperates ratiometrically or with 5 VDC, 2.5 VDC, or analog span adjusted voltage reference
Key Specifications
Features |
Y Resolution |
8 bits |
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Compatible with 8080 mP derivativesÐno interfacing |
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Total error |
g(/4 LSB, g(/2 LSB and g1 LSB |
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logic needed - access time - 135 ns |
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Conversion time |
100 ms |
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Easy interface to all microprocessors, or operates |
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``stand alone'' |
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Typical Applications
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TL/H/5671 ± 1 |
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8080 Interface |
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Error Specification (Includes Full-Scale, |
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Zero Error, and Non-Linearity) |
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Part |
Full- |
VREF/2e2.500 VDC |
VREF/2eNo Connection |
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Scale |
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Number |
(No Adjustments) |
(No Adjustments) |
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Adjusted |
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ADC0801 |
g(/4 LSB |
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ADC0802 |
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g(/2 LSB |
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ADC0803 |
g(/2 LSB |
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ADC0804 |
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g1 LSB |
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TL/H/5671 ± 31 |
ADC0805 |
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g1 LSB |
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TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
Z-80É is a registered trademark of Zilog Corp.
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 Converters A/D Compatible Pm Bit-8
C1995 National Semiconductor Corporation |
TL/H/5671 |
RRD-B30M115/Printed in U. S. A. |
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VCC) (Note 3) |
6.5V |
Voltage |
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Logic Control Inputs |
b0.3V to a18V |
At Other Input and Outputs |
b0.3V to (VCCa0.3V) |
Lead Temp. (Soldering, 10 seconds) |
260§C |
Dual-In-Line Package (plastic) |
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Dual-In-Line Package (ceramic) |
300§C |
Surface Mount Package |
215§C |
Vapor Phase (60 seconds) |
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Infrared (15 seconds) |
220§C |
Storage Temperature Range |
b65§C to a150§C |
Package Dissipation at TAe25§C |
875 mW |
ESD Susceptibility (Note 10) |
800V |
Operating Ratings (Notes 1 & 2)
Temperature Range |
TMINsTAsTMAX |
ADC0801/02LJ, ADC0802LJ/883 |
b55§CsTAsa125§C |
ADC0801/02/03/04LCJ |
b40§CsTAsa85§C |
ADC0801/02/03/05LCN |
b40§CsTAsa85§C |
ADC0804LCN |
0§CsTAsa70§C |
ADC0802/03/04LCV |
0§CsTAsa70§C |
ADC0802/03/04LCWM |
0§CsTAsa70§C |
Range of VCC |
4.5 VDC to 6.3 VDC |
Electrical Characteristics
The following specifications apply for VCCe5 VDC, TMINsTAsTMAX and fCLKe640 kHz unless otherwise specified.
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
ADC0801: Total Adjusted Error (Note 8) |
With Full-Scale Adj. |
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g(/4 |
LSB |
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(See Section 2.5.2) |
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ADC0802: Total Unadjusted Error (Note 8) |
VREF/2e2.500 VDC |
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g(/2 |
LSB |
ADC0803: Total Adjusted Error (Note 8) |
With Full-Scale Adj. |
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g(/2 |
LSB |
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(See Section 2.5.2) |
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ADC0804: Total Unadjusted Error (Note 8) |
VREF/2e2.500 VDC |
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g1 |
LSB |
ADC0805: Total Unadjusted Error (Note 8) |
VREF/2-No Connection |
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g1 |
LSB |
VREF/2 Input Resistance (Pin 9) |
ADC0801/02/03/05 |
2.5 |
8.0 |
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kX |
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ADC0804 (Note 9) |
0.75 |
1.1 |
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kX |
Analog Input Voltage Range |
(Note 4) V(a) or V(b) |
Gnd ± 0.05 |
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VCCa0.05 |
VDC |
DC Common-Mode Error |
Over Analog Input Voltage |
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g(/16 |
g(/8 |
LSB |
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Range |
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Power Supply Sensitivity |
VCCe5 VDC g10% Over |
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g(/16 |
g(/8 |
LSB |
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Allowed VIN(a) and VIN(b) |
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Voltage Range (Note 4) |
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AC Electrical Characteristics
The following specifications apply for VCCe5 VDC and TAe25§C unless otherwise specified.
Symbol |
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Conditions |
Min |
Typ |
Max |
Units |
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TC |
Conversion Time |
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fCLKe640 kHz (Note 6) |
103 |
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114 |
ms |
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TC |
Conversion Time |
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(Note 5, 6) |
66 |
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73 |
1/fCLK |
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fCLK |
Clock Frequency |
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VCCe5V, (Note 5) |
100 |
640 |
1460 |
kHz |
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Clock Duty Cycle |
(Note 5) |
40 |
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60 |
% |
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CR |
Conversion Rate in Free-Running |
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INTR tied to WR with |
8770 |
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9708 |
conv/s |
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Mode |
CSe0 VDC, fCLKe640 kHz |
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Width of WR Input (Start Pulse Width) |
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CSe0 VDC (Note 7) |
100 |
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tW(WR)L |
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tACC |
Access Time (Delay from Falling |
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CLe100 pF |
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135 |
200 |
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Edge of RD to Output Data Valid) |
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t1H, t0H |
TRI-STATE Control (Delay |
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CLe10 pF, RLe10k |
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125 |
200 |
ns |
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from Rising Edge of RD to |
(See TRI-STATE Test |
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Hi-Z State) |
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Circuits) |
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tWI, tRI |
Delay from Falling Edge |
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300 |
450 |
ns |
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of WR or RD to Reset of INTR |
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CIN |
Input Capacitance of Logic |
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5 |
7.5 |
pF |
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Control Inputs |
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COUT |
TRI-STATE Output |
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5 |
7.5 |
pF |
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Capacitance (Data Buffers) |
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CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately] |
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VIN (1) |
Logical ``1'' Input Voltage |
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VCCe5.25 VDC |
2.0 |
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15 |
VDC |
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(Except Pin 4 CLK IN) |
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AC Electrical Characteristics (Continued)
The following specifications apply for VCC e 5VDC and TMIN s TA s TMAX, unless otherwise specified.
Symbol |
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Conditions |
Min |
Typ |
Max |
Units |
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CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately] |
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VIN (0) |
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Logical ``0'' Input Voltage |
VCCe4.75 VDC |
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0.8 |
VDC |
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(Except Pin 4 CLK IN) |
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IIN (1) |
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Logical ``1'' Input Current |
VINe5 VDC |
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0.005 |
1 |
mADC |
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(All Inputs) |
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IIN (0) |
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Logical ``0'' Input Current |
VINe0 VDC |
b1 |
b0.005 |
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mADC |
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(All Inputs) |
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CLOCK IN AND CLOCK R |
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VTa |
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CLK IN (Pin 4) Positive Going |
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2.7 |
3.1 |
3.5 |
VDC |
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Threshold Voltage |
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VTb |
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CLK IN (Pin 4) Negative |
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1.5 |
1.8 |
2.1 |
VDC |
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Going Threshold Voltage |
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VH |
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CLK IN (Pin 4) Hysteresis |
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0.6 |
1.3 |
2.0 |
VDC |
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(VTa)b(VTb) |
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VOUT (0) |
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Logical ``0'' CLK R Output |
IOe360 mA |
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0.4 |
VDC |
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Voltage |
VCCe4.75 VDC |
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VOUT (1) |
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Logical ``1'' CLK R Output |
IOeb360 mA |
2.4 |
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VDC |
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Voltage |
VCCe4.75 VDC |
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DATA OUTPUTS AND INTR |
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VOUT (0) |
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Logical ``0'' Output Voltage |
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Data Outputs |
IOUTe1.6 mA, VCCe4.75 VDC |
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0.4 |
VDC |
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IOUTe1.0 mA, VCCe4.75 VDC |
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INTR Output |
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0.4 |
VDC |
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VOUT (1) |
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Logical ``1'' Output Voltage |
IOeb360 mA, VCCe4.75 VDC |
2.4 |
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VDC |
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VOUT (1) |
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Logical ``1'' Output Voltage |
IOeb10 mA, VCCe4.75 VDC |
4.5 |
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VDC |
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IOUT |
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TRI-STATE Disabled Output |
VOUTe0 VDC |
b3 |
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mADC |
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Leakage (All Data Buffers) |
VOUTe5 VDC |
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3 |
mADC |
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ISOURCE |
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VOUT Short to Gnd, TAe25§C |
4.5 |
6 |
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mADC |
ISINK |
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VOUT Short to VCC, TAe25§C |
9.0 |
16 |
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mADC |
POWER SUPPLY |
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ICC |
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Supply Current (Includes |
fCLKe640 kHz, |
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Ladder Current) |
VREF/2eNC, TAe25§C |
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and CSe5V |
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ADC0801/02/03/04LCJ/05 |
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1.1 |
1.8 |
mA |
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ADC0804LCN/LCV/LCWM |
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1.9 |
2.5 |
mA |
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.
Note 3: A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC.
Note 4: For VIN(b)t VIN(a) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct±especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading.
Note 5: Accuracy is guaranteed at fCLK e 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The start request is internally latched, see Figure 2 and section 2.0.
Note 7: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams).
Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 5 .
Note 9: The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, and ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kX. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 kX.
Note 10: Human body model, 100 pF discharged through a 1.5 kX resistor.
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Typical Performance Characteristics
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Delay From Falling Edge of |
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Logic Input Threshold Voltage |
RD to Output Data Valid |
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vs. Supply Voltage |
vs. Load Capacitance |
CLK IN Schmitt Trip Levels vs. Supply Voltage
Error
TL/H/5671 ± 2
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TRI-STATE Test Circuits and Waveforms
t1H |
t1H, CLe10 pF |
t0H |
t0H, CLe10 pF |
tre20 ns |
tre20 ns |
TL/H/5671 ± 3 |
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Timing Diagrams (All timing is measured from the 50% voltage points)
TL/H/5671 ± 4
Note: Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to guarantee reset of INTR.
5
Typical Applications (Continued)
6800 Interface |
Ratiometric with Full-Scale Adjust |
TL/H/5671 ± 5
6
Typical Applications (Continued)
Directly Converting a Low-Level Signal |
A mP Interfaced Comparator |
TL/H/5671 ± 6
7
Typical Applications (Continued)
*
Self
*After of the
*
TL/H/5671 ± 7
8
Typical Applications (Continued)
mP Compatible Differential-Input Comparator with Pre-Set VOS (with or without Hysteresis)
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*Circuit
**Can A/D
TL/H/5671 ± 8
9
Typical Applications (Continued)
Handling g5V Analog Inputs |
Read-Only Interface |
TL/H/5671 ± 33
*Beckman Instruments Ý694-3-R10K resistor array
mP Interfaced Comparator with Hysteresis
TL/H/5671 ± 35
Analog Self-Test for a System
TL/H/5671 ± 36
TL/H/5671 ± 34
Protecting the Input
Diodes are 1N914
TL/H/5671 ± 9
A Low-Cost, 3-Decade Logarithmic Converter
TL/H/5671 ± 37
*LM389 transistors
A, B, C, D e LM324A quad op amp
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Typical Applications (Continued)
3-Decade Logarithmic A/D Converter
TL/H/5671 ± 10
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*A/D output data is updated 1 CLK period |
*Allows output data to set-up at falling edge of CS |
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prior to assertion of INTR |
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