NSC ADC0803LCWM, ADC0803LCV, ADC0803LCN, ADC0803LCJ, ADC0805LCN Datasheet

December 1994

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

8-Bit mP Compatible A/D Converters

General Description

The ADC0801, ADC0802, ADC0803, ADC0804 and ADC0805 are CMOS 8-bit successive approximation A/D converters that use a differential potentiometric ladderÐ similar to the 256R products. These converters are designed to allow operation with the NSC800 and INS8080A derivative control bus with TRI-STATEÉ output latches directly driving the data bus. These A/Ds appear like memory locations or I/O ports to the microprocessor and no interfacing logic is needed.

Differential analog voltage inputs allow increasing the com- mon-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.

YDifferential analog voltage inputs

YLogic inputs and outputs meet both MOS and TTL voltage level specifications

YWorks with 2.5V (LM336) voltage reference

YOn-chip clock generator

Y0V to 5V analog input voltage range with single 5V supply

YNo zero adjust required

Y0.3× standard width 20-pin DIP package

Y20-pin molded chip carrier or small outline package

YOperates ratiometrically or with 5 VDC, 2.5 VDC, or analog span adjusted voltage reference

Key Specifications

Features		Y Resolution		8 bits
Y	Compatible with 8080 mP derivativesÐno interfacing	Y	Total error	g(/4 LSB, g(/2 LSB and g1 LSB
	logic needed - access time - 135 ns	Y	Conversion time	100 ms
Y	Easy interface to all microprocessors, or operates
	``stand alone''

Typical Applications

				TL/H/5671 ± 1
8080 Interface		Error Specification (Includes Full-Scale,
		Zero Error, and Non-Linearity)
	Part	Full-	VREF/2e2.500 VDC	VREF/2eNo Connection
		Scale
	Number		(No Adjustments)	(No Adjustments)
		Adjusted
	ADC0801	g(/4 LSB
	ADC0802		g(/2 LSB
	ADC0803	g(/2 LSB
	ADC0804		g1 LSB
TL/H/5671 ± 31	ADC0805			g1 LSB

TRI-STATEÉ is a registered trademark of National Semiconductor Corp.

Z-80É is a registered trademark of Zilog Corp.

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 Converters A/D Compatible Pm Bit-8

C1995 National Semiconductor Corporation

TL/H/5671

RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1 & 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (VCC) (Note 3)	6.5V
Voltage
Logic Control Inputs	b0.3V to a18V
At Other Input and Outputs	b0.3V to (VCCa0.3V)
Lead Temp. (Soldering, 10 seconds)	260§C
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)	300§C
Surface Mount Package	215§C
Vapor Phase (60 seconds)
Infrared (15 seconds)	220§C

Storage Temperature Range	b65§C to a150§C
Package Dissipation at TAe25§C	875 mW
ESD Susceptibility (Note 10)	800V

Operating Ratings (Notes 1 & 2)

Temperature Range	TMINsTAsTMAX
ADC0801/02LJ, ADC0802LJ/883	b55§CsTAsa125§C
ADC0801/02/03/04LCJ	b40§CsTAsa85§C
ADC0801/02/03/05LCN	b40§CsTAsa85§C
ADC0804LCN	0§CsTAsa70§C
ADC0802/03/04LCV	0§CsTAsa70§C
ADC0802/03/04LCWM	0§CsTAsa70§C
Range of VCC	4.5 VDC to 6.3 VDC

Electrical Characteristics

The following specifications apply for VCCe5 VDC, TMINsTAsTMAX and fCLKe640 kHz unless otherwise specified.

Parameter	Conditions	Min	Typ	Max	Units
ADC0801: Total Adjusted Error (Note 8)	With Full-Scale Adj.			g(/4	LSB
	(See Section 2.5.2)
ADC0802: Total Unadjusted Error (Note 8)	VREF/2e2.500 VDC			g(/2	LSB
ADC0803: Total Adjusted Error (Note 8)	With Full-Scale Adj.			g(/2	LSB
	(See Section 2.5.2)
ADC0804: Total Unadjusted Error (Note 8)	VREF/2e2.500 VDC			g1	LSB
ADC0805: Total Unadjusted Error (Note 8)	VREF/2-No Connection			g1	LSB
VREF/2 Input Resistance (Pin 9)	ADC0801/02/03/05	2.5	8.0		kX
	ADC0804 (Note 9)	0.75	1.1		kX
Analog Input Voltage Range	(Note 4) V(a) or V(b)	Gnd ± 0.05		VCCa0.05	VDC
DC Common-Mode Error	Over Analog Input Voltage		g(/16	g(/8	LSB
	Range
Power Supply Sensitivity	VCCe5 VDC g10% Over		g(/16	g(/8	LSB
	Allowed VIN(a) and VIN(b)
	Voltage Range (Note 4)

AC Electrical Characteristics

The following specifications apply for VCCe5 VDC and TAe25§C unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

TC

Conversion Time

fCLKe640 kHz (Note 6)

103

114

ms

TC

Conversion Time

(Note 5, 6)

66

73

1/fCLK

fCLK

Clock Frequency

VCCe5V, (Note 5)

100

640

1460

kHz

Clock Duty Cycle

(Note 5)

40

60

%

CR

Conversion Rate in Free-Running

INTR tied to WR with

8770

9708

conv/s

Mode

CSe0 VDC, fCLKe640 kHz

Width of WR Input (Start Pulse Width)

CSe0 VDC (Note 7)

100

ns

tW(WR)L

tACC

Access Time (Delay from Falling

CLe100 pF

135

200

ns

Edge of RD to Output Data Valid)

t1H, t0H

TRI-STATE Control (Delay

CLe10 pF, RLe10k

125

200

ns

from Rising Edge of RD to

(See TRI-STATE Test

Hi-Z State)

Circuits)

tWI, tRI

Delay from Falling Edge

300

450

ns

of WR or RD to Reset of INTR

CIN

Input Capacitance of Logic

5

7.5

pF

Control Inputs

COUT

TRI-STATE Output

5

7.5

pF

Capacitance (Data Buffers)

CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]

VIN (1)

Logical ``1'' Input Voltage

VCCe5.25 VDC

2.0

15

VDC

(Except Pin 4 CLK IN)

2

AC Electrical Characteristics (Continued)

The following specifications apply for VCC e 5VDC and TMIN s TA s TMAX, unless otherwise specified.

Symbol				Parameter		Conditions	Min	Typ	Max	Units
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN (0)		Logical ``0'' Input Voltage				VCCe4.75 VDC			0.8	VDC
		(Except Pin 4 CLK IN)
IIN (1)		Logical ``1'' Input Current				VINe5 VDC		0.005	1	mADC
		(All Inputs)
IIN (0)		Logical ``0'' Input Current				VINe0 VDC	b1	b0.005		mADC
		(All Inputs)
CLOCK IN AND CLOCK R
VTa		CLK IN (Pin 4) Positive Going					2.7	3.1	3.5	VDC
		Threshold Voltage
VTb		CLK IN (Pin 4) Negative					1.5	1.8	2.1	VDC
		Going Threshold Voltage
VH		CLK IN (Pin 4) Hysteresis					0.6	1.3	2.0	VDC
		(VTa)b(VTb)
VOUT (0)		Logical ``0'' CLK R Output				IOe360 mA			0.4	VDC
		Voltage				VCCe4.75 VDC
VOUT (1)		Logical ``1'' CLK R Output				IOeb360 mA	2.4			VDC
		Voltage				VCCe4.75 VDC
DATA OUTPUTS AND INTR
VOUT (0)		Logical ``0'' Output Voltage
		Data Outputs				IOUTe1.6 mA, VCCe4.75 VDC			0.4	VDC
						IOUTe1.0 mA, VCCe4.75 VDC
		INTR Output							0.4	VDC
VOUT (1)		Logical ``1'' Output Voltage				IOeb360 mA, VCCe4.75 VDC	2.4			VDC
VOUT (1)		Logical ``1'' Output Voltage				IOeb10 mA, VCCe4.75 VDC	4.5			VDC
IOUT		TRI-STATE Disabled Output				VOUTe0 VDC	b3			mADC
		Leakage (All Data Buffers)				VOUTe5 VDC			3	mADC
ISOURCE						VOUT Short to Gnd, TAe25§C	4.5	6		mADC
ISINK						VOUT Short to VCC, TAe25§C	9.0	16		mADC
POWER SUPPLY
ICC		Supply Current (Includes				fCLKe640 kHz,
		Ladder Current)				VREF/2eNC, TAe25§C
						and CSe5V
		ADC0801/02/03/04LCJ/05						1.1	1.8	mA
		ADC0804LCN/LCV/LCWM						1.9	2.5	mA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.

Note 3: A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC.

Note 4: For VIN(b)t VIN(a) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct±especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading.

Note 5: Accuracy is guaranteed at fCLK e 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.

Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The start request is internally latched, see Figure 2 and section 2.0.

Note 7: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams).

Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 5 .

Note 9: The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, and ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kX. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 kX.

Note 10: Human body model, 100 pF discharged through a 1.5 kX resistor.

3

Typical Performance Characteristics

	Delay From Falling Edge of
Logic Input Threshold Voltage	RD to Output Data Valid
vs. Supply Voltage	vs. Load Capacitance

CLK IN Schmitt Trip Levels vs. Supply Voltage

Error

TL/H/5671 ± 2

4

TRI-STATE Test Circuits and Waveforms

t1H

t1H, CLe10 pF

t0H

t0H, CLe10 pF

tre20 ns	tre20 ns	TL/H/5671 ± 3

Timing Diagrams (All timing is measured from the 50% voltage points)

TL/H/5671 ± 4

Note: Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to guarantee reset of INTR.

5

Typical Applications (Continued)

6800 Interface

Ratiometric with Full-Scale Adjust

TL/H/5671 ± 5

6

Typical Applications (Continued)

Directly Converting a Low-Level Signal

A mP Interfaced Comparator

TL/H/5671 ± 6

7

Typical Applications (Continued)

*

Self

*After of the

*

TL/H/5671 ± 7

8

Typical Applications (Continued)

mP Compatible Differential-Input Comparator with Pre-Set VOS (with or without Hysteresis)

*

*Circuit

**Can A/D

TL/H/5671 ± 8

9

Typical Applications (Continued)

Handling g5V Analog Inputs

Read-Only Interface

TL/H/5671 ± 33

*Beckman Instruments Ý694-3-R10K resistor array

mP Interfaced Comparator with Hysteresis

TL/H/5671 ± 35

Analog Self-Test for a System

TL/H/5671 ± 36

TL/H/5671 ± 34

Protecting the Input

Diodes are 1N914

TL/H/5671 ± 9

A Low-Cost, 3-Decade Logarithmic Converter

TL/H/5671 ± 37

*LM389 transistors

A, B, C, D e LM324A quad op amp

10

Typical Applications (Continued)

3-Decade Logarithmic A/D Converter

TL/H/5671 ± 10

*A/D output data is updated 1 CLK period			*Allows output data to set-up at falling edge of CS
prior to assertion of INTR

11