NSC 5962-9581601QXA Datasheet
54ACTQ16646
16-Bit Transceiver/Register with TRI-STATE
®
Outputs
General Description
The ’ACTQ16646 contains sixteen non-inverting bidirectional registered bus transceivers providing multiplexed
transmission of data directly from the input bus or from the
internal storage registers. Each byte has separate control inputs which can be shorted together for full 16-bit operation.
The DIR inputs determine the direction of data flow through
the device. The CPAB and CPBA inputs load data into the
registers on the LOW-to-HIGH transition. The ’ACTQ16646
utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance.
FACT Quiet Series
®
features GTO®output control and un-
dershoot corrector for superior performance.
Features
n Utilizes NSC FACT Quiet Series technology
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Independent registers for A and B buses
n Multiplexed real-time and stored data transfers
n Separate control logic for each byte
n 16-bit version of the ’ACTQ646
n Outputs source/sink 24 mA
n Standard Microcircuit Drawing (SMD) 5962-9581601
Logic Symbol
GTO™is a trademarkof National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
™
and FACT Quiet Series™are trademarks of Fairchild Semiconductor Corporation.
DS010937-1
September 1998
54ACTQ16646 16-Bit Transceiver/Register with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS010937 www.national.com
Connection Diagram
Pin Assignment for
CERPAK
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Real Time Transfer
A-Bus to B-Bus
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FIGURE 1.
Real Time Transfer
B-Bus to A-Bus
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FIGURE 2.
Storage from
Bus to Register
DS010937-5
FIGURE 3.
Transfer from
Register to Bus
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FIGURE 4.
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Function Table
Inputs Data I/O (Note 1) Output Operation Mode
G
1
DIR1CPAB1CPBA1SAB1SBA1A
0–7
B
0–7
H X H or L H or L X X Isolation
H X N X X X Input Input Clock An Data into A Register
H X X N X X Clock Bn Data Into B Register
L H X X L X An to Bn— Real Time (Transparent Mode)
L H N X L X Input Output Clock An Data to A Register
L H H or L X H X A Register to Bn (Stored Mode)
L H N X H X Clock An Data into A Register and Output to Bn
L L X X X L Bn to An — Real Time (Transparent Mode)
L L X N X L Output Input Clock Bn Data into B Register
L L X H or L X H B Register to An (Stored Mode)
L L X N X H Clock Bn into B Register and Output to An
H=HIGH Voltage Level X=Immaterial
L=LOW Voltage Level N=LOW-to-HIGH Transition.
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the
bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and
#
2 control pins.
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