NEC Electronics Inc UPA603T Datasheet

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NEC Electronics Inc UPA603T Datasheet

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

μPA603T

P-CHANNEL MOS FET (6-PIN 2 CIRCUITS)

The μPA603T is a mini-mold device provided with two MOS FET circuits. It achieves high-density mounting and saves mounting costs.

FEATURES

Two MOS FET circuits in package the same size as SC-59

Complement to μPA602T

Automatic mounting supported

PACKAGE

DIMENSIONS

(in millimeters)

 

+0.1

–0.5

0.32

–0.05+0.1

0.16 –0.06+0.1

 

 

 

 

2.8±0.2

0.65

 

 

 

1.5

 

 

0 to 0.1

 

 

 

 

 

 

 

 

0.95

0.95

0.8

 

 

 

1.9

1.1 to 1.4

 

 

 

2.9 ±0.2

 

PIN CONNECTION (Top view)

ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)

PARAMETER

SYMBOL

RATINGS

UNIT

 

 

 

 

Drain to Source Voltage

VDSS

–50

V

 

 

 

 

Gate to Source Voltage

VGSS

+16

V

 

 

 

 

Drain Current (DC)

ID(DC)

–100

mA

 

 

 

 

Drain Current (pulse)

ID(pulse)*

–200

mA

 

 

 

 

Total Power Dissipation

PT

300 (Total)

mW

 

 

 

 

Channel Temperature

Tch

150

˚C

 

 

 

 

Storage Temperature

Tstg

–55 to +150

˚C

 

 

 

 

* PW 10 ms, Dury Cycle 50 %

Document No. G11250EJ1V0DS00 (1st edition)

 

 

Date Published June 1996 P

 

 

Printed in Japan

©

1996

 

 

 

 

 

 

 

 

 

 

 

 

μPA603T

 

ELECTRICAL CHARACTERISTICS (TA = 25 ˚C)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PARAMETER

SYMBOL

 

 

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Drain Cut-off Current

IDSS

VDS = –50 V, VGS = 0

 

–1.0

μA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate Leakage Current

IGSS

VGS =

 

 

 

+1.0

μA

 

 

+16 V, VDS = 0

 

 

 

Gate Cut-off Voltage

VGS(off)

VDS = –5.0 V, ID = –1.0 μA

–1.5

–1.9

 

–2.5

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Forward Transfer Admittance

|yfs|

VDS = –5.0 V, ID = –10 mA

15

 

 

mS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Drain to Source On-State Resistance

RDS(on)1

VGS = –4.0 V, ID = –10 mA

60

100

Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Drain to Source On-State Resistance

RDS(on)2

VGS = –10 V, ID = –10 mA

40

60

Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Capacitance

Ciss

VDS = –5.0 V, VGS = 0, f = 1.0 MHz

17

 

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Capacitance

Coss

 

 

 

9

 

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reverse Transfer Capacitance

Crss

 

 

 

1

 

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Turn-On Delay Time

td(on)

VGS(on) = –4.0 V, RG = 10 Ω,

45

 

 

ns

 

 

 

 

VDD = –5.0 V, ID = –10 mA, RL = 500 Ω

 

 

 

 

 

 

 

 

Rise Time

tr

75

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Turn-Off Delay Time

td(off)

 

 

 

25

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fall Time

tf

 

 

 

80

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Marking: JA

SWITCHING TIME MEASUREMENT CIRCUIT AND CONDITIONS

PG.

0

VGS

τ

τ = 1 μs

Duty Cycle 1 %

 

 

VGS

 

 

 

 

RL

Gate

 

10 %

 

 

 

DUT

voltage

 

 

 

 

 

 

 

VGS(on)

 

 

 

 

 

 

 

waveform

 

 

 

 

 

 

 

 

 

90 %

VDD

 

 

 

 

 

 

 

 

 

 

 

RG

 

ID

 

 

 

 

 

 

 

td(on)

tr

td(off)

tf

 

Drain

0

 

 

 

 

 

current

10 %

 

 

10 %

 

waveform

 

 

 

ID

 

 

 

 

 

 

 

 

 

 

 

 

 

90 %

 

 

 

 

90 %

 

 

2

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