NEC Electronics Inc UPA1852GR-9JG Datasheet

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DATA SHEET

MOS FIELD EFFECT TRANSISTOR

μ PA1852

N-CHANNEL MOS FIELD EFFECT TRANSISTOR

FOR SWITCHING

DESCRIPTION

The μPA1852 is a switching device which can be driven directly by a 2.5-V power source.

The μPA1852 features a low on-state resistance and excellent switching characteristics, and is suitable for applications such as power switch of portable machine and so on.

FEATURES

Can be driven by a 2.5-V power source

Low on-state resistance

RDS(on)1 = 40 mΩ MAX. (VGS = 4.5 V, ID = 3.0 A) RDS(on)2 = 45 mΩ MAX. (VGS = 4.0 V, ID = 3.0 A) RDS(on)3 = 60 mΩ MAX. (VGS = 2.5 V, ID = 3.0 A)

Built-in G-S protection diode against ESD

ORDERING INFORMATION

PART NUMBER

PACKAGE

 

 

μPA1852GR-9JG

Power TSSOP8

 

 

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

PACKAGE DRAWING (Unit : mm)

8

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

:Drain1

 

1.2 MAX.

 

2, 3

:Source1

 

 

 

 

 

 

 

1.0±0.05

 

 

 

 

 

 

4

:Gate1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

:Gate2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.25

 

 

 

 

6, 7

:Source2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

:Drain2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3° –3+5°°

 

0.5

 

 

 

 

 

 

 

 

 

 

 

0.1±0.05

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

4

 

 

 

 

 

 

 

 

0.6 –0.1+0.15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.15 ±0.15

 

3.0 ±0.1

0.145 ±0.055

 

0.65

0.8 MAX.

0.27 –0.08+0.03

0.10 M

6.4 ±0.2

 

4.4 ±0.1

1.0 ±0.2

 

 

0.1

Drain to Source Voltage

VDSS

20

V

Gate to Source Voltage

VGSS

±12

V

Drain Current (DC)

ID(DC)

±6.0

A

Drain Current (pulse) Note1

ID(pulse)

±24

A

Total Power Dissipation Note2

PT

2.0

W

Channel Temperature

Tch

150

°C

Storage Temperature

Tstg

–55 to +150

°C

Notes 1.

PW 10 μs, Duty Cycle 1 %

 

 

2.

Mounted on ceramic substrate of 5000 mm2 x 1.1 mm

EQUIVALENT CIRCUIT

 

Drain1

 

Drain2

 

Body

 

Body

Gate1

Diode

Gate2

Diode

Gate

 

Gate

 

Protection

Source1

Protection

Source2

Diode

Diode

 

 

Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. D12803EJ1V0DS00 (1st edition) Date Published October 1999 NS CP(K) Printed in Japan

© 1997, 1999

 

 

 

 

 

 

 

μ PA1852

 

ELECTRICAL CHARACTERISTICS (TA = 25 °C)

 

 

 

 

 

 

 

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

 

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

Drain Cut-off Current

IDSS

VDS = 20 V, VGS = 0 V

 

 

10

 

μA

 

 

 

 

 

 

 

 

 

 

 

 

Gate Leakage Current

IGSS

VGS = ±12 V, VDS = 0 V

 

 

±10

 

μA

 

 

 

 

 

 

 

 

 

 

 

 

Gate Cut-off Voltage

VGS(off)

VDS = 10 V, ID = 1 mA

0.5

0.74

1.5

 

V

 

 

 

 

 

 

 

 

 

 

 

 

Forward Transfer Admittance

| yfs |

VDS = 10 V, ID = 3.0 A

1

10

 

 

S

 

 

 

 

 

 

 

 

 

 

 

 

Drain to Source On-state Resistance

RDS(on)1

VGS = 4.5 V, ID = 3.0 A

 

29

40

 

mΩ

 

 

 

 

 

 

 

 

 

 

 

 

 

RDS(on)2

VGS = 4.0 V, ID = 3.0 A

 

31

45

 

mΩ

 

 

 

 

 

 

 

 

 

 

 

 

 

RDS(on)3

VGS = 2.5 V, ID = 3.0 A

 

39

60

 

mΩ

 

 

 

 

 

 

 

 

 

 

 

 

Input Capacitance

Ciss

VDS = 10 V

 

420

 

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

Output Capacitance

Coss

VGS = 0 V

 

265

 

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

Reverse Transfer Capacitance

Crss

f = 1 MHz

 

120

 

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

Turn-on Delay Time

td(on)

VDD = 10 V

 

55

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

Rise Time

tr

ID = 1.5 A

 

160

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

Turn-off Delay Time

td(off)

VGS(on) = 4.0 V

 

385

 

 

ns

 

 

 

 

RG = 10 Ω

 

 

 

 

 

 

 

Fall Time

tf

 

355

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

Total Gate Charge

QG

VDD = 10 V

 

6

 

 

nC

 

 

 

 

 

 

 

 

 

 

 

 

Gate to Source Charge

QGS

ID = 6.0 A

 

2

 

 

nC

 

 

 

 

 

 

 

 

 

 

 

 

Gate to Drain Charge

QGD

VGS = 4.0 V

 

3

 

 

nC

 

 

 

 

 

 

 

 

 

 

 

 

Diode Forward Voltage

VF(S-D)

IF = 6.0 A, VGS = 0 V

 

0.74

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

Reverse Recovery Time

trr

IF = 6.0 A, VGS = 0 V

 

20

 

 

ns

 

 

 

 

di/dt = 15 A / μs

 

 

 

 

 

 

 

Reverse Recovery Charge

Qrr

 

2

 

 

nC

 

 

 

 

 

 

 

 

 

 

 

TEST CIRCUIT 1 SWITCHING TIME

 

 

 

 

 

D.U.T.

 

 

 

 

 

 

 

RL

VGS

 

 

90 %

 

 

VGS

10 %

 

VGS(on)

 

 

 

 

 

 

Wave Form

 

 

 

 

RG

0

 

 

 

PG.

VDD

 

 

 

RG = 10 Ω

 

 

 

 

 

 

 

ID

90 %

 

90 %

 

 

 

 

 

 

VGS

 

 

 

 

ID

 

 

ID

0 10 %

 

 

10 %

0

 

 

 

 

Wave Form

 

 

 

 

τ

 

 

td(on)

tr

td(off)

tf

τ = 1 μs

 

 

 

ton

 

toff

 

 

 

 

 

 

Duty Cycle 1 %

TEST CIRCUIT 2 GATE CHARGE

 

D.U.T.

 

 

IG = 2 mA

RL

 

 

PG.

50 Ω

VDD

2

Data Sheet D12803EJ1V0DS00

NEC Electronics Inc UPA1852GR-9JG Datasheet

μ PA1852

TYPICAL CHARACTERISTICS (TA = 25°C)

DERATING FACTOR OF FORWARD BIAS

SAFE OPERATING AREA

 

100

 

 

 

 

- %

80

 

 

 

 

 

 

 

 

 

Factor

60

 

 

 

 

dT - Derating

40

 

 

 

 

20

 

 

 

 

 

 

 

 

 

 

0

60

90

120

150

 

30

 

TA - Ambient Temperature - ˚C

 

 

 

 

DRAIN CURRENT vs.

 

 

 

 

 

 

25

 

DRAIN TO SOURCE VOLTAGE

 

 

 

 

 

 

 

 

VGS = 4.5

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

 

 

 

 

 

 

 

 

 

 

 

- A

 

 

 

 

 

 

 

4.0 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CurrentDrain

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.5 V

 

 

 

15

 

 

 

 

 

 

 

 

 

ID -

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0.2

0.4

0.6

0.8

1

 

 

 

VDS - Drain to Source Voltage - V

 

 

GATE TO SOURCE CUT-OFF VOLTAGE vs.

CHANNEL TEMPERATURE

V

1.5

 

 

 

 

 

 

 

 

 

-

VDS = 10 V

 

 

 

 

-off Voltage

 

 

 

 

ID = 1 mA

 

 

 

 

1

 

 

 

 

to Source Cut

0.5

 

 

 

 

Gate

 

 

 

 

 

 

 

 

 

-

 

 

 

 

 

VGS(off)

0

 

 

 

 

 

50

0

50

100

150

 

Tch

- Channel Temperature - ˚C

 

FORWARD BIAS SAFE OPERATING AREA

 

100

 

 

 

 

 

 

 

 

 

 

 

 

Limited.5

 

ID (pulse)

PW

 

 

 

 

 

 

V)

 

=

 

 

 

 

 

 

 

 

10

 

4

 

 

 

 

 

-A

DS(on) =

ID (DC)

 

 

 

 

1

ms

 

R

GS

 

10

 

 

 

Current

 

(@V

 

 

ms

 

 

 

 

 

 

100

 

 

 

 

 

 

 

ms

 

 

 

 

1

 

 

 

DC

 

 

 

 

ID - Drain

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.1

 

 

 

 

 

 

 

 

 

 

Single Pulse

 

 

 

 

 

 

Mounted on Ceramic Substrate of 50cm2x 1.1mm

0.01 PD(FET1) : PD(FET2) = 1:1

0.1

1.0

10.0

100.0

VDS - Drain to Source Voltage - V

TRANSFER CHARACTERISTICS

 

100

VDS = 10 V

 

 

 

- A

10

 

 

 

 

 

 

 

 

 

Current

1

 

 

 

 

 

 

TA = 125 ˚C

 

 

Drain

 

 

 

 

0.1

 

75 ˚C

 

 

ID -

 

 

25 ˚C

 

 

 

 

 

 

 

 

0.01

 

25 ˚C

 

 

 

0.001

 

 

 

 

 

0

1

2

3

4

VGS - Gate to Source Voltage - V

FORWARD TRANSFER ADMMITTANCE vs. DRAIN CURRENT

 

100

VDS = 10 V

 

 

 

 

 

 

 

 

- S

 

 

 

 

 

Admittance

 

 

TA = 25 ˚C

 

 

Transfer

10

 

25 ˚C

 

 

 

 

75 ˚C

 

 

 

 

 

 

 

Forward-|yfs

 

 

125 ˚C

 

 

1

 

 

 

 

 

 

 

 

 

|

 

 

 

 

 

 

0.1

 

1

10

100

 

0.1

 

 

 

ID - Drain Current - A

 

Data Sheet D12803EJ1V0DS00

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