NEC Electronics Inc UPA1850GR-9JG Datasheet

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DATA SHEET

MOS FIELD EFFECT TRANSISTOR

μ PA1850

P-CHANNEL MOS FIELD EFFECT TRANSISTOR

FOR SWITCHING

DESCRIPTION

The μPA1850 is a switching device which can be driven directly by a 2.5-V power source.

The μPA1850 features a low on-state resistance and excellent switching characteristics, and is suitable for applications such as power switch of portable machine and so on.

FEATURES

Can be driven by a 2.5-V power source

Low on-state resistance

RDS(on)1 = 115 mΩ MAX. (VGS = –4.5 V, ID = –1.5 A) RDS(on)2 = 130 mΩ MAX. (VGS = –4.0 V, ID = –1.5 A) RDS(on)3 = 200 mΩ MAX. (VGS = –2.5 V, ID = –1.5 A)

Built-in G-S protection diode against ESD

ORDERING INFORMATION

PART NUMBER

PACKAGE

 

 

μPA1850GR-9JG

Power TSSOP8

 

 

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

PACKAGE DRAWING (Unit : mm)

8

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

:Drain1

 

1.2 MAX.

 

2, 3

:Source1

 

 

 

 

 

 

 

1.0±0.05

 

 

 

 

 

 

4

:Gate1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

:Gate2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.25

 

 

 

 

6, 7

:Source2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

:Drain2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3° –3+5°°

 

0.5

 

 

 

 

 

 

 

 

 

 

 

0.1±0.05

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

4

 

 

 

 

 

 

 

 

0.6 –0.1+0.15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.15 ±0.15

 

3.0 ±0.1

0.145 ±0.055

 

0.65

0.8 MAX.

0.27 –0.08+0.03

0.10 M

6.4 ±0.2

 

4.4 ±0.1

1.0 ±0.2

 

 

0.1

Drain to Source Voltage

VDSS

–12

V

Gate to Source Voltage

VGSS

–10/+5

V

Drain Current (DC)

ID(DC)

#2.5

A

Drain Current (pulse) Note1

ID(pulse)

#10

A

Total Power Dissipation Note2

PT

2.0

W

Channel Temperature

Tch

150

°C

Storage Temperature

Tstg

–55 to +150

°C

Notes 1.

PW 10 μs, Duty Cycle 1 %

 

 

2.

Mounted on ceramic substrate of 5000 mm2 x 1.1 mm

EQUIVALENT CIRCUIT

 

Drain1

 

Drain2

 

Body

 

Body

Gate1

Diode

Gate2

Diode

Gate

 

Gate

 

Protection

Source1

Protection

Source2

Diode

Diode

 

 

Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. D11818EJ2V0DS00 (2nd edition) Date Published January 2000 NS CP(K)

Printed in Japan

The mark shows major revised points.

© 1997, 2000

 

 

 

 

 

 

 

 

 

μ PA1850

 

ELECTRICAL CHARACTERISTICS (TA = 25 °C)

 

 

 

 

 

 

 

 

CHARACTERISTICS

 

SYMBOL

TEST CONDITIONS

 

MIN.

TYP.

MAX.

 

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Drain Cut-off Current

 

IDSS

VDS = –12 V, VGS = 0 V

 

 

 

–10

 

μA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate Leakage Current

 

IGSS

VGS = # 10 V, VDS = 0 V

 

 

 

# 10

 

μA

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate to Source Cut-off Voltage

 

VGS(off)

VDS = –10 V, ID = –1 mA

 

–0.5

–1.0

–1.5

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

Forward Transfer Admittance

 

| yfs |

VDS = –10 V, ID = –1.5 A

 

2.0

5.0

 

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Drain to Source On-state Resistance

 

RDS(on)1

VGS = –4.5 V, ID = –1.5 A

 

 

80

115

 

mΩ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RDS(on)2

VGS = –4.0 V, ID = –1.5 A

 

 

85

130

 

mΩ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RDS(on)3

VGS = –2.5 V, ID = –1.5 A

 

 

127

200

 

mΩ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Capacitance

 

Ciss

VDS = –10 V

 

 

260

 

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Capacitance

 

Coss

VGS = 0 V

 

 

300

 

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reverse Transfer Capacitance

 

Crss

f = 1 MHz

 

 

45

 

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Turn-on Delay Time

 

td(on)

VDD = –10 V

 

 

120

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise Time

 

tr

ID = –1.5 A

 

 

420

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Turn-off Delay Time

 

td(off)

VGS(on) = –4.0 V

 

 

520

 

 

ns

 

 

 

 

 

RG = 10 Ω

 

 

 

 

 

 

 

 

Fall Time

 

tf

 

 

430

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Total Gate Charge

 

QG

VDD = –10 V

 

 

12

 

 

nC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate to Source Charge

 

QGS

ID = –2.5 A

 

 

2

 

 

nC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate to Drain Charge

 

QGD

VGS = –4.0 V

 

 

5

 

 

nC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Diode Forward Voltage

 

VF(S-D)

IF = 2.5 A, VGS = 0 V

 

 

0.80

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

Reverse Recovery Time

 

trr

IF = 2.5 A, VGS = 0 V

 

 

750

 

 

ns

 

 

 

 

 

di/dt = 10 A / μs

 

 

 

 

 

 

 

Reverse Recovery Charge

 

Qrr

 

 

950

 

 

nC

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST CIRCUIT 1 SWITCHING TIME

 

 

TEST CIRCUIT 2 GATE CHARGE

 

D.U.T.

 

 

 

 

 

RL

VGS ()

 

 

90 %

 

VGS

10 %

 

VGS(on)

 

 

 

 

Wave Form

 

 

 

 

0

 

 

 

PG.

RG

 

 

 

VDD

 

 

 

 

 

 

ID ()

90 %

 

90 %

 

 

 

 

ID

VGS ()

 

 

 

10 %

ID

0 10 %

 

 

0

 

 

Wave Form

 

 

 

 

τ

 

td(on)

tr

td(off)

tf

τ = 1 μ s

 

 

ton

 

toff

 

 

 

 

Duty Cycle 1 %

 

D.U.T.

 

 

IG = 2 mA

RL

 

 

PG.

50 Ω

VDD

2

Data Sheet D11818EJ2V0DS00

NEC Electronics Inc UPA1850GR-9JG Datasheet

TYPICAL CHARACTERISTICS (TA = 25°C)

DERATING FACTOR OF FORWARD BIAS

SAFE OPERATING AREA

 

100

 

 

 

 

- %

80

 

 

 

 

 

 

 

 

 

Factor

60

 

 

 

 

dT - Derating

40

 

 

 

 

20

 

 

 

 

 

 

 

 

 

 

0

60

90

120

150

 

30

 

TA - Ambient Temperature - ˚C

 

 

 

 

TRANSFER CHARACTERISTICS

 

 

 

10

 

 

 

 

 

 

VDS = 10 V

 

 

 

- A

 

1

 

 

 

 

Current

 

0.1

 

TA = 125 ˚C

 

Drain-

 

 

 

 

 

25

˚C

 

 

 

 

 

75

˚C

 

 

 

 

 

25 ˚C

 

ID

 

0.01

 

 

 

 

 

 

 

 

 

 

 

0.001

1

2

3

 

 

0

 

 

 

VGS - Gate to Source Voltage - V

 

 

 

FORWARD TRANSFER ADMMITTANCE vs.

 

 

DRAIN CURRENT

 

 

 

 

100

 

 

 

 

 

 

VDS = 10 V

 

 

 

 

- S

 

 

 

 

 

 

Admittance

 

TA

= 25 ˚C

 

 

 

 

10

 

25 ˚C

 

 

 

 

 

 

 

 

 

Transfer

 

 

75 ˚C

 

 

 

 

125 ˚C

 

 

Forward-|yfs

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

|

 

 

 

 

 

 

 

0.1

 

 

 

 

 

 

0.1

1

10

100

 

 

 

ID - Drain Current - A

 

μ PA1850

FORWARD BIAS SAFE OPERATING AREA

 

100

 

 

 

 

 

 

 

 

 

 

 

A

10

 

 

 

0V)

 

ID (pulse)

 

PW

=

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

-

 

 

 

Limited.

 

 

 

 

 

 

ms

 

 

 

4

 

 

 

10

 

 

Current

 

DS(on)

 

 

 

 

 

 

 

=

 

 

 

 

ms

 

 

 

 

 

 

 

 

 

R

GS

 

ID

(DC)

 

 

 

 

 

(@V

 

 

100

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

ms

 

 

 

 

 

 

 

 

 

DC

 

 

 

ID - Drain

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.1

 

 

 

 

 

 

 

 

 

 

 

 

Single Pulse

 

 

 

 

 

 

Mounted on Ceramic Substrate of 5000 mm2x 1.1mm

0.01 PD(FET1) : PD(FET2) = 1:1

0.1

1.0

10.0

100.0

VDS - Drain to Source Voltage - V

GATE TO SOURCE CUT-OFF VOLTAGE vs.

CHANNEL TEMPERATURE

V

1.5

 

 

 

 

 

 

 

 

 

-

VDS = 10 V

 

 

 

-off Voltage

 

 

 

ID = 1 mA

 

 

 

 

1

 

 

 

 

to Source Cut

 

 

 

 

0.5

 

 

 

 

Gate

 

 

 

 

 

 

 

 

 

-

 

 

 

 

 

VGS(off)

0

 

 

 

 

 

50

0

50

100

150

 

Tch

- Channel Temperature - ˚C

 

DRAIN TO SOURCE ON-STATE RESISTANCE vs.

mΩ

DRAIN CURRENT

 

 

 

 

 

 

250

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

 

VGS = 2.5 V

 

 

 

 

 

 

 

 

Resistance

 

 

 

 

 

 

 

 

 

200

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-Onstate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

150

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

75˚C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TA = 125˚C

 

 

 

 

 

 

 

 

 

 

 

 

Source

 

 

25˚C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

- Drain to

100

 

25˚C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RDS(on)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

10

100

 

0.1

 

 

 

ID - Drain Current - A

Data Sheet D11818EJ2V0DS00

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