NEC Electronics Inc UPA1812 Datasheet

Loading...

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

μ PA1812

P-CHANNEL MOS FIELD EFFECT TRANSISTOR

FOR SWITCHING

DESCRIPTION

The μPA1812 is a switching device which can be driven directly by a 4.0-V power source.

The μPA1812 features a low on-state resistance and excellent switching characteristics, and is suitable for applications such as power switch of portable machine and so on.

FEATURES

Can be driven by a 4.0-V power source

Low on-state resistance

RDS(on)1 = 39 mΩ MAX. (VGS = –10 V, ID = –2.5 A) RDS(on)2 = 63 mΩ MAX. (VGS = –4.5 V, ID = –2.5 A) RDS(on)3 = 69 mΩ MAX. (VGS = –4.0 V, ID = –2.5 A)

ORDERING INFORMATION

PART NUMBER

PACKAGE

 

 

μPA1812GR-9JG

Power TSSOP8

 

 

PACKAGE DRAWING (Unit : mm)

8 5

1, 5, 8

: Drain

 

1.2 MAX.

 

 

 

 

2, 3, 6, 7: Source

 

 

 

 

 

 

 

 

 

 

 

 

 

1.0±0.05

 

 

 

4

: Gate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3° –3+5°°

0.5

0.1±0.05

1 4

0.6 +0.15–0.1

3.15 ±0.15

 

3.0 ±0.1

0.145 ±0.055

 

0.65

0.8 MAX.

0.27 –0.08+0.03

0.10 M

6.4 ±0.2

 

4.4 ±0.1

1.0 ±0.2

 

 

0.1

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

Drain to Source Voltage

VDSS

–30

V

Gate to Source Voltage

VGSS

–20/+5

V

Drain Current (DC)

ID(DC)

±5.0

A

Drain Current (pulse) Note1

ID(pulse)

±20

A

Total Power Dissipation Note2

PT

2.0

W

Channel Temperature

Tch

150

°C

Storage Temperature

Tstg

–55 to +150

°C

Notes 1.

PW 10 μs, Duty Cycle 1 %

 

 

 

2.

Mounted on ceramic substrate of 5000 mm2 x 1.1 mm

 

EQUIVALENT CIRCUIT

 

Drain

 

Body

Gate

Diode

Gate

 

Protection

Source

Diode

 

Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No.

D12967EJ1V0DS00 (1st edition)

The mark shows major revised points.

©

 

1997, 1999

 

Date Published

October 1999 NS CP(K)

 

 

 

 

Printed in Japan

μ PA1812

ELECTRICAL CHARACTERISTICS (TA = 25 °C)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

 

 

 

 

 

 

 

Zero Gate Voltage Drain Current

IDSS

VDS = –30 V, VGS = 0 V

 

 

–10

μA

 

 

 

 

 

 

 

Gate Leakage Current

IGSS

VGS = ±20 V, VDS = 0 V

 

 

±10

μA

 

 

 

 

 

 

 

Gate Cut-off Voltage

VGS(off)

VDS = –10 V, ID = –1 mA

–1.0

–1.6

–2.5

V

 

 

 

 

 

 

 

Forward Transfer Admittance

| yfs |

VDS = –10 V, ID = –2.5 A

1

8

 

S

 

 

 

 

 

 

 

Drain to Source On-state Resistance

RDS(on)1

VGS = –10 V, ID = –2.5 A

 

29

39

mΩ

 

 

 

 

 

 

 

 

RDS(on)2

VGS = –4.5 V, ID = –2.5 A

 

46

63

mΩ

 

 

 

 

 

 

 

 

RDS(on)3

VGS = –4.0 V, ID = –2.5 A

 

52

69

mΩ

 

 

 

 

 

 

 

Input Capacitance

Ciss

VDS = –10 V

 

1500

 

pF

 

 

 

 

 

 

 

Output Capacitance

Coss

VGS = 0 V

 

550

 

pF

 

 

 

 

 

 

 

Reverse Transfer Capacitance

Crss

f = 1 MHz

 

270

 

pF

 

 

 

 

 

 

 

Turn-on Delay Time

td(on)

VDD = –10 V

 

30

 

ns

 

 

 

 

 

 

 

Rise Time

tr

ID = –2.5 A

 

160

 

ns

 

 

 

 

 

 

 

Turn-off Delay Time

td(off)

VGS(on) = –10 V

 

110

 

ns

 

 

RG = 10 Ω

 

 

 

 

Fall Time

tf

 

80

 

ns

 

 

 

 

 

 

 

Total Gate Charge

QG

VDS = –24 V

 

31

 

nC

 

 

 

 

 

 

 

Gate to Source Charge

QGS

ID = –5.0 A

 

4

 

nC

 

 

 

 

 

 

 

Gate to Drain Charge

QGD

VGS = –10 V

 

8

 

nC

 

 

 

 

 

 

 

Diode Forward Voltage

VF(S-D)

IF = 5.0 A, VGS = 0 V

 

0.76

 

V

 

 

 

 

 

 

 

TEST CIRCUIT 1 SWITCHING TIME

 

 

 

 

 

D.U.T.

 

 

 

 

 

 

 

RL

VGS

 

 

90 %

 

 

VGS

10 %

 

VGS(on)

 

 

 

 

 

 

Wave Form

 

 

 

 

RG

0

 

 

 

PG.

VDD

 

 

 

RG = 10 Ω

 

 

 

 

 

 

 

ID

90 %

 

90 %

 

 

 

 

 

 

VGS

 

 

 

 

ID

 

 

ID

0 10 %

 

 

10 %

0

 

 

 

 

Wave Form

 

 

 

 

τ

 

 

td(on)

tr

td(off)

tf

τ = 1μ s

 

 

 

ton

 

toff

 

 

 

 

 

 

Duty Cycle 1 %

TEST CIRCUIT 2 GATE CHARGE

 

D.U.T.

 

 

IG = 2 mA

RL

 

 

PG.

50 Ω

VDD

2

Data Sheet D12967EJ1V0DS00

NEC Electronics Inc UPA1812 Datasheet

TYPICAL CHARACTERISTICS (TA = 25 °C)

DERATING FACTOR OF FORWARD BIAS

SAFE OPERATING AREA

 

100

 

 

 

 

- %

80

 

 

 

 

 

 

 

 

 

Factor

60

 

 

 

 

 

 

 

 

 

dT - Derating

40

 

 

 

 

20

 

 

 

 

 

 

 

 

 

 

0

60

90

120

150

 

30

 

TA - Ambient Temperature - ˚C

 

DRAIN CURRENT vs.

DRAIN TO SOURCE VOLTAGE

 

−20

Pulsed

 

 

 

 

 

 

 

 

 

 

- A

 

VGS = −10 V

 

 

 

 

−15

 

 

 

 

 

Current

−10

 

 

 

−4.5 V

 

ID - Drain

 

 

−4.0 V

 

 

 

 

 

 

 

−5

 

 

 

 

 

 

 

 

 

 

 

 

0

−0.2

−0.4

−0.6

−0.8

−1.0

 

 

VDS - Drain to Source Voltage - V

GATE TO SOURCE CUT-OFF VOLTAGE vs.

CHANNEL TEMPERATURE

- V

−2.0

 

 

 

 

 

VDS = −10 V

 

 

 

 

 

Voltage

−1.8

 

 

 

 

 

 

 

 

 

 

ID

= −1 mA

Cut-off

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−1.6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Source

 

 

 

 

 

 

 

 

 

 

−1.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gate to

 

 

 

 

 

 

 

 

 

 

−1.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

 

 

 

 

 

 

 

 

 

 

 

VGS(off)

 

 

 

 

 

 

 

 

 

 

 

−1.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−50

0

50

100

150

Tch - Channel Temperature - ˚C

μ PA1812

FORWARD BIAS SAFE OPERATING AREA

 

−100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PW=

 

 

 

 

 

 

 

V)

ID(pulse)

 

 

1

ms

 

 

 

 

 

5

 

 

 

 

 

 

 

Limited.

 

 

 

 

 

 

 

DS(on)

 

4

 

 

 

 

 

 

 

=

-

 

 

10

 

 

 

 

 

 

 

 

 

A

−10

R

GS

 

 

 

 

ms

 

(@V

 

 

 

ID(DC)

 

 

 

 

 

 

 

-

 

 

 

 

 

 

 

 

 

Current

 

 

 

 

 

 

100

 

 

 

 

 

 

 

 

 

ms

 

 

 

 

 

 

 

 

 

 

−1

 

 

 

 

 

 

DC

 

 

 

ID - Drain

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−0.1

 

 

 

 

 

 

 

 

 

 

 

TA = 25˚C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Single Pulse

Mounted on Ceramic

 

 

−0.01 Substrate of 5000 mm2 x 1.1 mm

 

 

−0.1

−1.0

−10.0

−100.0

VDS - Drain to Source Voltage - V

FORWARD TRANSFER CHARACTERISTICS

 

−100

 

VDS = −10 V

 

 

 

 

 

 

 

 

 

 

−10

 

 

 

 

 

- A

−1

 

 

 

 

 

Current

 

 

 

 

 

 

 

TA = 125˚C

 

 

 

−0.1

 

75˚C

 

TA = 25˚C

 

- Drain

 

 

 

 

 

 

 

 

 

 

 

 

−25˚C

 

−0.01

 

 

 

 

 

ID

 

 

 

 

 

 

 

 

 

 

 

 

−0.001

 

 

 

 

 

−0.0001

0

−1.0

−2.0

−3.0

−4.0

VGS - Gate to Source Voltage - V

FORWARD TRANSFER ADMITTANCE vs.

DRAIN CURRENT

 

100

VDS = −10 V

 

 

 

 

- S

 

 

 

 

 

 

 

 

 

 

 

Admittance

10

 

 

 

 

 

 

 

 

TA = −25

 

Transfer

 

 

 

˚C

 

 

 

 

25

˚C

 

 

 

 

75

˚C

 

 

 

 

125

˚C

yfs | - Forward

 

 

 

 

1

 

 

 

 

 

0.1

 

 

 

 

 

|

 

 

 

 

 

 

 

−1

−10

 

−100

 

−0.1

 

 

 

 

ID - Drain Current - A

 

 

Data Sheet D12967EJ1V0DS00

3

+ 5 hidden pages