NEC Electronics Inc UPA1790G Datasheet

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NEC Electronics Inc UPA1790G Datasheet

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

μ PA1790

SWITCHING

N-AND P-CHANNEL POWER MOS FET

INDUSTRIAL USE

DESCRIPTION

This product is N-and P-Channel MOS Field Effect Transistor designed for motor driver applications.

PACKAGE DRAWING (Unit : mm)

8 5

N-Channel 1

; Source 1

2

; Gate 1

7,8

; Drain 1

FEATURES

Dual chip type

Low on-resistance

N-Channel RDS(on)1 = 0.12 Ω TYP. (VGS = 10 V, ID = 0.5 A) RDS(on)2 = 0.19 Ω TYP. (VGS = 4 V, ID = 0.5 A)

P-Channel RDS(on)1 = 0.45 Ω TYP. (VGS = –10 V, ID = –0.35 A) RDS(on)2 = 0.74 Ω TYP. (VGS = –4 V, ID = –0.35 A)

Low input capacitance N-Channel Ciss = 180 pF TYP. P-Channel Ciss = 230 pF TYP.

Built-in G-S protection diode

Small and surface mount package (Power SOP8)

P-Channel 3

; Source 2

4

; Gate 2

5,6

; Drain 2

 

1

 

4

 

6.0 ±0.3

 

 

 

 

4.4

 

MAX.1.8

1.44

5.37 MAX.

0.15

0.8

 

 

 

 

 

 

 

 

 

+0.10

–0.05

 

 

 

MIN.

 

 

 

0.5 ±0.2

 

 

1.27

0.78 MAX.

 

0.10

 

0.05

0.40 –0.05+0.10

0.12 M

 

 

EQUIVARENT CIRCUIT

ORDERING INFORMATION

PART NUMBER

PACKAGE

 

 

μPA1790G

Power SOP8

 

 

 

Drain

 

 

Drain

 

 

 

Body

 

 

Body

Gate

 

Diode

Gate

 

Diode

Gate

 

 

Gate

 

 

Protection

Source

 

Protection

Source

 

Diode

 

Diode

 

 

 

 

 

N-Channel

 

P-Channel

 

Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. G14320EJ1V0DS00 (1st edition) Date Published May 1999 NS CP(K)

Printed in Japan

© 1999

μ PA1790

ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)

 

PARAMETER

SYMBOL

N-CHANNEL

P-CHANNEL

UNIT

Drain to Source Voltage (VGS = 0 V)

VDSS

60

 

–60

V

Gate to Source Voltage (VDS = 0 V)

VGSS

±20

 

# 20

V

Drain Current (DC)

ID(DC)

±1.0

 

# 0.7

A

Drain Current (pulse) Note1

ID(pulse)

±4.0

 

# 2.8

A

Total Power Dissipation (1 unit) Note2

PT

 

1.7

W

Total Power Dissipation (2 unit) Note2

PT

 

2.0

W

Channel Temperature

Tch

 

150

°C

Storage Temperature

Tstg

–55 to +150

°C

Notes 1.

PW 10 μs, Duty Cycle 1 %

 

 

 

 

 

2.

Mounted on ceramic substrate of 2000 mm2 x 2.25 mm

 

 

 

2

Data Sheet G14320EJ1V0DS00

μ PA1790

ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)

N-CHANNEL

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

 

 

 

 

 

 

 

Drain to Source On-state Resistance

RDS(on)1

VGS = 10 V, ID = 0.5 A

 

0.12

0.26

Ω

 

 

 

 

 

 

 

 

RDS(on)2

VGS = 4 V, ID = 0.5 A

 

0.19

0.34

Ω

 

 

 

 

 

 

 

Gate to Source Cut-off Voltage

VGS(off)

VDS = 10 V, ID = 1 mA

1.0

1.7

2.5

V

 

 

 

 

 

 

 

Forward Transfer Admittance

| yfs |

VDS = 10 V, ID = 0.5 A

1.0

1.7

 

S

 

 

 

 

 

 

 

Drain Leakage Current

IDSS

VDS = 60 V, VGS = 0 V

 

 

10

μA

 

 

 

 

 

 

 

Gate to Source Leakage Current

IGSS

VGS = ±16 V, VDS = 0 V

 

 

±10

μA

 

 

 

 

 

 

 

Input Capacitance

Ciss

VDS = 10 V

 

180

 

pF

 

 

 

 

 

 

 

Output Capacitance

Coss

VGS = 0 V

 

100

 

pF

 

 

 

 

 

 

 

Reverse Transfer Capacitance

Crss

f = 1 MHz

 

35

 

pF

 

 

 

 

 

 

 

Turn-on Delay Time

td(on)

ID = 0.5 A

 

1

 

ns

 

 

 

 

 

 

 

Rise Time

tr

VGS(on) = 10 V

 

1.4

 

ns

 

 

 

 

 

 

 

Turn-off Delay Time

td(off)

VDD = 30 V

 

23

 

ns

 

 

RG = 10 Ω

 

 

 

 

Fall Time

tf

 

17

 

ns

 

 

 

 

 

 

 

Total Gate Charge

QG

ID = 1.0 A

 

8

 

nC

 

 

 

 

 

 

 

Gate to Source Charge

QGS

VDD = 48 V

 

1

 

nC

 

 

 

 

 

 

 

Gate to Drain Charge

QGD

VGS = 10 V

 

3.5

 

nC

 

 

 

 

 

 

 

Body Diode Forward Voltage

VF(S-D)

IF = 1.0 A, VGS = 0 V

 

0.75

 

V

 

 

 

 

 

 

 

Reverse Recovery Time

trr

IF = 1.0 A, VGS = 0 V

 

30

 

ns

 

 

di/dt = 100 A / μs

 

 

 

 

Reverse Recovery Charge

Qrr

 

33

 

nC

 

 

 

 

 

 

 

TEST CIRCUIT 1 SWITCHING TIME

 

 

 

 

 

D.U.T.

 

 

 

 

 

 

 

RL

VGS

 

 

90 %

 

 

VGS

10 %

 

VGS(on)

 

 

 

 

 

 

Wave Form

 

 

 

 

RG

0

 

 

 

PG.

VDD

 

 

 

RG = 10 Ω

 

 

 

 

 

 

 

ID

90 %

 

90 %

 

 

 

 

 

 

VGS

 

 

 

 

ID

 

 

ID

0 10 %

 

 

10 %

0

 

 

 

 

Wave Form

 

 

 

 

τ

 

 

td(on)

tr

td(off)

tf

τ = 1μ s

 

 

 

ton

 

toff

 

 

 

 

 

 

Duty Cycle 1 %

TEST CIRCUIT 2 GATE CHARGE

 

D.U.T.

 

 

IG = 2 mA

RL

 

 

PG.

50 Ω

VDD

Data Sheet G14320EJ1V0DS00

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