DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μ PA1790
SWITCHING
N-AND P-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
This product is N-and P-Channel MOS Field Effect Transistor designed for motor driver applications.
PACKAGE DRAWING (Unit : mm)
8 5
N-Channel 1 |
; Source 1 |
2 |
; Gate 1 |
7,8 |
; Drain 1 |
FEATURES
∙Dual chip type
∙Low on-resistance
N-Channel RDS(on)1 = 0.12 Ω TYP. (VGS = 10 V, ID = 0.5 A) RDS(on)2 = 0.19 Ω TYP. (VGS = 4 V, ID = 0.5 A)
P-Channel RDS(on)1 = 0.45 Ω TYP. (VGS = –10 V, ID = –0.35 A) RDS(on)2 = 0.74 Ω TYP. (VGS = –4 V, ID = –0.35 A)
∙Low input capacitance N-Channel Ciss = 180 pF TYP. P-Channel Ciss = 230 pF TYP.
∙Built-in G-S protection diode
∙Small and surface mount package (Power SOP8)
P-Channel 3 |
; Source 2 |
4 |
; Gate 2 |
5,6 |
; Drain 2 |
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1 |
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4 |
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6.0 ±0.3 |
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4.4 |
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MAX.1.8 |
1.44 |
5.37 MAX. |
0.15 |
0.8 |
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+0.10 |
–0.05 |
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MIN. |
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0.5 ±0.2 |
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1.27 |
0.78 MAX. |
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0.10 |
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0.05 |
0.40 –0.05+0.10 |
0.12 M |
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EQUIVARENT CIRCUIT
ORDERING INFORMATION
PART NUMBER |
PACKAGE |
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μPA1790G |
Power SOP8 |
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Drain |
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Drain |
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Body |
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Body |
Gate |
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Diode |
Gate |
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Diode |
Gate |
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Gate |
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Protection |
Source |
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Protection |
Source |
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Diode |
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Diode |
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N-Channel |
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P-Channel |
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Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. G14320EJ1V0DS00 (1st edition) Date Published May 1999 NS CP(K)
Printed in Japan
© 1999
μ PA1790
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
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PARAMETER |
SYMBOL |
N-CHANNEL |
P-CHANNEL |
UNIT |
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Drain to Source Voltage (VGS = 0 V) |
VDSS |
60 |
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–60 |
V |
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Gate to Source Voltage (VDS = 0 V) |
VGSS |
±20 |
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# 20 |
V |
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Drain Current (DC) |
ID(DC) |
±1.0 |
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# 0.7 |
A |
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Drain Current (pulse) Note1 |
ID(pulse) |
±4.0 |
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# 2.8 |
A |
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Total Power Dissipation (1 unit) Note2 |
PT |
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1.7 |
W |
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Total Power Dissipation (2 unit) Note2 |
PT |
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2.0 |
W |
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Channel Temperature |
Tch |
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150 |
°C |
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Storage Temperature |
Tstg |
–55 to +150 |
°C |
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Notes 1. |
PW ≤ 10 μs, Duty Cycle ≤ 1 % |
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2. |
Mounted on ceramic substrate of 2000 mm2 x 2.25 mm |
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2 |
Data Sheet G14320EJ1V0DS00 |
μ PA1790
ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
N-CHANNEL
CHARACTERISTICS |
SYMBOL |
TEST CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Drain to Source On-state Resistance |
RDS(on)1 |
VGS = 10 V, ID = 0.5 A |
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0.12 |
0.26 |
Ω |
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RDS(on)2 |
VGS = 4 V, ID = 0.5 A |
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0.19 |
0.34 |
Ω |
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Gate to Source Cut-off Voltage |
VGS(off) |
VDS = 10 V, ID = 1 mA |
1.0 |
1.7 |
2.5 |
V |
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Forward Transfer Admittance |
| yfs | |
VDS = 10 V, ID = 0.5 A |
1.0 |
1.7 |
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S |
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Drain Leakage Current |
IDSS |
VDS = 60 V, VGS = 0 V |
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10 |
μA |
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Gate to Source Leakage Current |
IGSS |
VGS = ±16 V, VDS = 0 V |
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±10 |
μA |
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Input Capacitance |
Ciss |
VDS = 10 V |
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180 |
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pF |
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Output Capacitance |
Coss |
VGS = 0 V |
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100 |
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pF |
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Reverse Transfer Capacitance |
Crss |
f = 1 MHz |
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35 |
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pF |
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Turn-on Delay Time |
td(on) |
ID = 0.5 A |
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1 |
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ns |
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Rise Time |
tr |
VGS(on) = 10 V |
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1.4 |
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ns |
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Turn-off Delay Time |
td(off) |
VDD = 30 V |
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23 |
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ns |
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RG = 10 Ω |
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Fall Time |
tf |
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17 |
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ns |
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Total Gate Charge |
QG |
ID = 1.0 A |
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8 |
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nC |
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Gate to Source Charge |
QGS |
VDD = 48 V |
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1 |
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nC |
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Gate to Drain Charge |
QGD |
VGS = 10 V |
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3.5 |
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nC |
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Body Diode Forward Voltage |
VF(S-D) |
IF = 1.0 A, VGS = 0 V |
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0.75 |
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V |
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Reverse Recovery Time |
trr |
IF = 1.0 A, VGS = 0 V |
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30 |
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ns |
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di/dt = 100 A / μs |
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Reverse Recovery Charge |
Qrr |
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33 |
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nC |
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TEST CIRCUIT 1 SWITCHING TIME |
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D.U.T. |
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RL |
VGS |
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90 % |
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VGS |
10 % |
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VGS(on) |
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Wave Form |
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RG |
0 |
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PG. |
VDD |
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RG = 10 Ω |
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ID |
90 % |
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90 % |
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VGS |
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ID |
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ID |
0 10 % |
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10 % |
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0 |
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Wave Form |
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τ |
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td(on) |
tr |
td(off) |
tf |
τ = 1μ s |
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ton |
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toff |
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Duty Cycle ≤ 1 %
TEST CIRCUIT 2 GATE CHARGE
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D.U.T. |
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IG = 2 mA |
RL |
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PG. |
50 Ω |
VDD |
Data Sheet G14320EJ1V0DS00 |
3 |