NEC Electronics Inc UPA1764G Datasheet

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NEC Electronics Inc UPA1764G Datasheet

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

μ PA1764

SWITCHING

DUAL N-CHANNEL POWER MOS FET

INDUSTRIAL USE

DESCRIPTION

The μPA1764 is N-channel MOS Field Effect Transistor designed for high current switching applications.

PACKAGE DRAWING (Unit : mm)

8 5

1 : Source 1

2 : Gate 1

7, 8 : Drain 1

FEATURES

Dual chip type

Low On-state Resistance

RDS(on)1 = 27 mΩ (TYP.) (VGS = 10 V, ID = 3.5 A)

RDS(on)2 = 32 mΩ (TYP.) (VGS = 4.5 V, ID = 3.5 A)

RDS(on)3 = 34 mΩ (TYP.) (VGS = 4.0 V, ID = 3.5 A)

Low input capacitance

Ciss = 1300 pF (TYP.)

Built-in G-S protection diode

Small and surface mount package (Power SOP8)

 

 

 

 

3

: Source 2

 

 

 

 

 

4

: Gate 2

 

 

 

 

 

5, 6 : Drain 2

 

 

1

 

4

 

6.0 ±0.3

 

 

 

 

4.4

 

MAX.1.8

1.44

5.37 MAX.

0.15

0.8

 

 

 

 

 

 

 

 

 

+0.10

–0.05

 

 

 

MIN.

 

 

 

0.5 ±0.2

 

 

1.27

0.78 MAX.

 

0.10

 

0.05

0.40 –0.05+0.10

0.12 M

 

 

ORDERING INFORMATION

PART NUMBER

PACKAGE

 

 

 

 

μPA1764G

Power SOP8

EQUIVALENT CIRCUIT

 

 

 

 

 

 

(1/2 circuit)

ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)

Drain to Source Voltage

VDSS

60

V

 

 

 

Drain

 

 

 

 

 

 

 

 

 

 

Gate to Source Voltage

VGSS

±20

V

 

 

 

 

 

 

 

 

 

Body

 

 

 

 

 

 

 

 

 

Drain Current (DC)

ID(DC)

±7

A

Gate

 

 

 

 

 

 

 

Diode

Drain Current (pulse) Note1

ID(pulse)

±28

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Total Power Dissipation (1 unit) Note2

PT

1.7

W

Gate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Total Power Dissipation (2 unit) Note2

PT

2.0

W

Protection

Source

Diode

Channel Temperature

Tch

150

°C

 

 

 

 

 

 

 

 

 

 

Storage Temperature

Tstg

–55 to +150

°C

 

 

 

 

 

 

 

 

 

 

Single Avalanche Current Note3

IAS

7

A

 

 

 

 

 

 

 

 

 

 

Single Avalanche Energy Note3

EAS

98

mJ

 

 

 

 

 

 

 

 

 

 

Notes 1. PW 10 μs, Duty Cycle 1 %

 

 

 

 

 

 

 

 

 

 

 

 

 

2. Mounted on ceramic substrate of 2000 mm2 x 2.2 mm

3. Starting Tch = 25 °C, R G = 25 Ω, VGS = 20 V 0 V

Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. G14329EJ1V0DS00 (1st edition) Date Published January 2000 NS CP(K) Printed in Japan

The mark shows major revised points.

©

1999,2000

 

μ PA1764

ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

 

 

 

 

 

 

 

Drain to Source On-state Resistance

RDS(on)1

VGS = 10 V, ID = 3.5 A

 

27

35

mΩ

 

 

 

 

 

 

 

 

RDS(on)2

VGS = 4.5 V, ID = 3.5 A

 

32

42

mΩ

 

 

 

 

 

 

 

 

RDS(on)3

VGS = 4.0 V, ID = 3.5 A

 

34

46

mΩ

 

 

 

 

 

 

 

Gate to Source Cut-off Voltage

VGS(off)

VDS = 10 V, ID = 1 mA

1.5

2.0

2.5

V

 

 

 

 

 

 

 

Forward Transfer Admittance

| yfs |

VDS = 10 V, ID = 3.5 A

5.0

9.0

 

S

 

 

 

 

 

 

 

Drain Leakage Current

IDSS

VDS = 60 V, VGS = 0 V

 

 

10

μA

 

 

 

 

 

 

 

Gate to Source Leakage Current

IGSS

VGS = ±20 V, VDS = 0 V

 

 

±10

μA

 

 

 

 

 

 

 

Input Capacitance

Ciss

VDS = 10 V

 

1300

 

pF

 

 

 

 

 

 

 

Output Capacitance

Coss

VGS = 0 V

 

230

 

pF

 

 

 

 

 

 

 

Reverse Transfer Capacitance

Crss

f = 1 MHz

 

110

 

pF

 

 

 

 

 

 

 

Turn-on Delay Time

td(on)

ID = 3.5 A

 

15

 

ns

 

 

 

 

 

 

 

Rise Time

tr

VGS(on) = 10 V

 

69

 

ns

 

 

 

 

 

 

 

Turn-off Delay Time

td(off)

VDD = 30 V

 

65

 

ns

 

 

RG = 10 Ω

 

 

 

 

Fall Time

tf

 

27

 

ns

 

 

 

 

 

 

 

Total Gate Charge

QG

ID = 7.0 A

 

29

 

nC

 

 

 

 

 

 

 

Gate to Source Charge

QGS

VDD = 48 V

 

3.6

 

nC

 

 

 

 

 

 

 

Gate to Drain Charge

QGD

VGS = 10 V

 

7.4

 

nC

 

 

 

 

 

 

 

Body Diode Forward Voltage

VF(S-D)

IF = 7.0 A, VGS = 0 V

 

0.84

 

V

 

 

 

 

 

 

 

Reverse Recovery Time

trr

IF = 7.0 A, VGS = 0 V

 

40

 

ns

 

 

di/dt = 100 A / μs

 

 

 

 

Reverse Recovery Charge

Qrr

 

66

 

nC

 

 

 

 

 

 

 

TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME

D.U.T.

 

 

 

 

 

 

 

RG = 25 Ω

L

 

D.U.T.

 

 

 

 

 

 

 

 

VGS

 

 

 

PG.

 

 

 

RL

 

 

90 %

 

 

 

VGS

 

 

VGS(on)

50 Ω

VDD

 

 

10 %

 

 

 

RG

Wave Form

 

 

 

VGS = 20 0 V

 

 

VDD

0

 

 

 

 

 

PG.

 

 

 

 

 

 

 

 

 

ID

90 %

 

90 %

 

BVDSS

 

 

 

 

 

ID

IAS

VGS

ID

0 10 %

 

10 %

 

VDS

 

 

 

0

 

 

 

ID

 

Wave Form

 

 

 

 

 

 

 

 

 

 

 

 

 

 

td(on)

tr

td(off)

tf

VDD

 

 

τ

 

 

 

 

τ = 1 μs

 

 

ton

 

toff

 

 

 

 

 

 

 

 

Starting Tch

 

Duty Cycle 1 %

 

 

 

 

 

TEST CIRCUIT 3 GATE CHARGE

 

D.U.T.

 

 

IG = 2 mA

RL

 

 

PG.

50 Ω

VDD

2

Data Sheet G14329EJ1V0DS00

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