NEC Electronics Inc UPA1759G Datasheet

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NEC Electronics Inc UPA1759G Datasheet

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

μPA1759

SWITCHING

N-CHANNEL POWER MOS FET

INDUSTRIAL USE

DESCRIPTION

 

PACKAGE DRAWING (Unit : mm)

This product is Dual N-channel MOS Field Effect

 

 

 

Transistor designed for DC/DC converters.

8

5

 

 

 

1

; Source 1

FEATURES

 

2

; Gate 1

 

7, 8 ; Drain 1

Dual chip type

Low on-resistance

RDS(on)1 = 110 mΩ TYP. (VGS = 10 V, ID = 2.5 A) RDS(on)2 = 170 mΩ TYP. (VGS = 4 V, ID = 2.5 A)

Low input capacitance Ciss = 190 pF TYP.

Built-in G-S protection diode

Small and surface mount package (Power SOP8)

ORDERING INFORMATION

Max.

 

 

1.44

 

 

 

 

 

 

 

 

 

 

 

 

1.8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.05 Min.

3; Source 2

4; Gate 2 5, 6 ; Drain 2

1

4

 

6.0 ±0.3

 

 

4.4

 

5.37 Max.

 

 

0.8

 

 

 

 

+0.10

–0.05

 

 

 

0.15

0.5 ±0.2

 

 

 

 

 

1.27

0.78 Max.

 

0.10

 

 

0.40 –0.05+0.10

0.12 M

 

 

PART NUMBER

PACKAGE

 

 

μPA1759G

Power SOP8

 

 

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, All terminals are connected.)

Drain to Source Voltage (VGS = 0)

VDSS

60

V

Gate to Source Voltage (VDS = 0)

VGSS

±20

V

Drain Current (DC)

ID(DC)

±5.0

A

Drain Current (pulse) Note1

ID(pulse)

±20

A

Total Power Dissipation (1 unit) Note2

PT

1.7

W

Total Power Dissipation (2 unit) Note2

PT

2.0

W

Channel Temperature

Tch

150

°C

Storage Temperature

Tstg

–55 to + 150

°C

Single Avalanche Current Note3

IAS

2.5

A

Single Avalanche Energy Note3

EAS

0.625

mJ

Notes 1. PW 10 μs, Duty cycle 1 %

 

 

 

2.Mounted on ceramic substrate of 1200 mm2 x 1.7 mm

3.Starting Tch = 25 °C, R G = 25 Ω, VGS = 20 V 0 V

EQUIVALENT CIRCUIT

(1/2 Circuit)

 

Drain

 

Body

Gate

Diode

Gate

 

Protection

Source

Diode

 

Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. G13622EJ1V0DS00 (1st edition) Date Published May 1999 NS CP(K)

Printed in Japan

© 1999

μPA1759

ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

 

 

 

 

 

 

 

Drain to Source On-state Resistance

RDS(on)1

VGS = 10 V, ID = 2.5 A

 

110

150

mΩ

 

 

 

 

 

 

 

 

RDS(on)2

VGS = 4 V, ID = 2.5 A

 

170

240

mΩ

 

 

 

 

 

 

 

Gate to Source Cut-off Voltage

VGS(off)

VDS = 10 V, ID = 1 mA

1.0

1.7

2.5

V

 

 

 

 

 

 

 

Forward Transfer Admittance

| yfs |

VDS = 10 V, ID = 2.5 A

2.0

3.9

 

S

 

 

 

 

 

 

 

Drain Leakage Current

IDSS

VDS = 60 V, VGS = 0 V

 

 

10

μA

 

 

 

 

 

 

 

Gate to Source Leakage Current

IGSS

VGS = ±20 V, VDS = 0 V

 

 

±10

μA

 

 

 

 

 

 

 

Input Capacitance

Ciss

VDS = 10 V

 

190

 

pF

 

 

 

 

 

 

 

Output Capacitance

Coss

VGS = 0 V

 

100

 

pF

 

 

 

 

 

 

 

Reverse Transfer Capacitance

Crss

f = 1 MHz

 

36

 

pF

 

 

 

 

 

 

 

Turn-on Delay Time

td(on)

ID = 2.5 A

 

6

 

ns

 

 

 

 

 

 

 

Rise Time

tr

VGS(on) = 10 V

 

50

 

ns

 

 

 

 

 

 

 

Turn-off Delay Time

td(off)

VDD = 15 V

 

80

 

ns

 

 

RG = 10 Ω

 

 

 

 

Fall Time

tf

 

50

 

ns

 

 

 

 

 

 

 

Total Gate Charge

QG

ID = 5.0 A

 

8

 

nC

 

 

 

 

 

 

 

Gate to Source Charge

QGS

VDD = 24 V

 

1

 

nC

 

 

 

 

 

 

 

Gate to Drain Charge

QGD

VGS = 10 V

 

2.4

 

nC

 

 

 

 

 

 

 

Body Diode forward Voltage

VF(S-D)

IF = 5.0 A, VGS = 0 V

 

0.9

 

V

 

 

 

 

 

 

 

Reverse Recovery Time

trr

IF = 5.0 A, VGS = 0 V

 

40

 

ns

 

 

di/dt = 100 A/μs

 

 

 

 

Reverse Recovery Charge

Qrr

 

50

 

nC

 

 

 

 

 

 

 

TEST CIRCUIT 1 AVALANCHE CAPABILITY

TEST CIRCUIT 2 SWITCHING TIME

 

 

 

 

D.U.T.

L

 

 

D.U.T.

 

VGS

 

 

RG = 25 Ω

 

 

 

 

RL

 

 

 

 

 

 

VGS

 

90 %

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10 %

VGS(on)

 

 

 

 

 

 

RG

 

 

Wave Form

 

 

PG.

50 Ω

VDD

PG.

 

Ω

 

 

0

 

 

RG

= 10

VDD

 

 

 

VGS = 20 0 V

 

ID

 

 

 

 

 

 

 

 

 

90 %

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

90 %

 

 

BVDSS

VGS

 

 

 

 

 

 

 

ID

 

 

0

 

 

 

 

 

ID

0 10 %

10 %

 

 

IAS

 

 

 

 

 

 

 

VDS

τ

 

 

 

 

Wave Form

 

 

 

VDD

ID

 

 

 

 

 

td(on) tr

td(off) tf

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

τ = 1 μs

 

 

 

 

 

ton

toff

 

 

 

Duty Cycle 1 %

 

 

 

 

 

 

 

Starting Tch

 

 

 

 

 

 

 

 

TEST CIRCUIT 3 GATE CHARGE

 

 

 

 

 

 

 

 

 

 

 

D.U.T.

 

 

 

 

 

 

 

 

 

 

IG = 2 mA

RL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PG.

50

Ω

VDD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

Data Sheet G13622EJ1V0DS00

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