NEC Electronics Inc UPA1560H Datasheet

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NEC Electronics Inc UPA1560H Datasheet

DATA SHEET

COMPOUND FIELD EFFECT POWER TRANSISTOR

μ PA1560

N-CHANNEL POWER MOS FET ARRAY

SWITCHING

INDUSTRIAL USE

DESCRIPTION

The μPA1560 is N-Channel Power MOS FET Array that built in 4 circuits designed for solenoid, motor and lamp driver.

FEATURES

Full mold package with 4 circuits

4 V driving is possible

Low on-state resistance

RDS(on)1 = 165 mΩ MAX. (VGS = 10 V, ID = 1.5 A) RDS(on)2 = 200 mΩ MAX. (VGS = 4 V, ID = 1.5 A)

Low input capacitance Ciss = 600 pF TYP.

ORDERING INFORMATION

PART NUMBER

PACKAGE

 

 

μ PA1560H

10-pin SIP

 

 

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

PACKAGE DRAWING (Unit : mm)

 

26.8 MAX.

 

4.0

10

 

 

 

2.5

 

 

10 MIN.

 

 

2.54

1.4

 

 

0.5±0.1

1.4

0.6±0.1

 

1 2 3 4 5 6 7 8 910

EQUIVALENT CIRCUIT

3

5

7

9

2

4

6

8

1

 

 

10

ELECTRODE CONNECTION

2, 4, 6, 8

: Gate

3, 5, 7, 9

: Drain

1, 10

: Source

Drain to Source Voltage (VGS = 0 V)

VDSS

120

V

Gate to Source Voltage (VDS = 0 V)

VGSS(AC)

±20

V

Gate to Source Voltage (VDS = 0 V)

VGSS(DC)

+ 20, –10

V

Drain Current (DC)

ID(DC)

±3.0

A

Drain Current (pulse) Note1

ID(pulse)

±12

A

Total Power Dissipation (TC = 25°C)

P T1

28

W

Total Power Dissipation (TA = 25°C)

P T2

3.7

W

Channel Temperature

Tch

150

°C

Storage Temperature

Tstg

–55 to + 150

°C

Single Avalanche Current Note2

IAS

3.0

A

Single Avalanche Energy Note2

EAS

0.9

mJ

Notes 1. PW 10 μs, Duty Cycle 1 %

2. Starting Tch = 25 °C, V DD = 60 V, RG = 25 Ω, VGS = 20 V →0 V

Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. G14283EJ1V0DS00 (1st edition) Date Published April 1999 NS CP(K)

Printed in Japan

© 1999

μ PA1560

ELECTRICAL CHARACTERISTICS (TA = 25 °C)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

 

 

 

 

 

 

 

Drain to Source On-state Resistance

RDS(on)1

VGS = 10 V, ID = 1.5 A

 

130

165

mΩ

 

 

 

 

 

 

 

 

RDS(on)2

VGS = 4.0 V, ID = 1.5 A

 

145

200

mΩ

 

 

 

 

 

 

 

Gate to Source Cut-off Voltage

VGS(off)

VDS = 10 V, ID = 1.0 mA

1.0

1.8

2.5

V

 

 

 

 

 

 

 

Forward Transfer Admittance

| yfs |

VDS = 10 V, ID = 1.5 A

2

4.5

 

S

 

 

 

 

 

 

 

Drain Leakage Current

IDSS

VDS = 120 V, VGS = 0 V

 

 

10

μA

 

 

 

 

 

 

 

Gate to Source Leakage Current

IGSS

VGS = ±20 V, VDS = 0 V

 

 

±10

μA

 

 

 

 

 

 

 

Input Capacitance

Ciss

VDS = 10 V

 

600

 

pF

 

 

 

 

 

 

 

Output Capacitance

Coss

VGS = 0 V

 

160

 

pF

 

 

 

 

 

 

 

Reverse Transfer Capacitance

Crss

f = 1.0 MHz

 

70

 

pF

 

 

 

 

 

 

 

Turn-on Delay Time

td(on)

ID = 1.5 A

 

35

 

ns

 

 

 

 

 

 

 

Rise Time

tr

VGS(on) = 10 V

 

80

 

ns

 

 

 

 

 

 

 

Turn-off Delay Time

td(off)

VDD = 60 V

 

700

 

ns

 

 

RL = 30 Ω

 

 

 

 

Fall Time

tf

 

250

 

ns

 

 

 

 

 

 

 

Total Gate Charge

QG

ID = 3.0 A

 

28

 

nC

 

 

 

 

 

 

 

Gate to Source Charge

QGS

VDD = 96 V

 

2.5

 

nC

 

 

 

 

 

 

 

Gate to Drain Charge

QGD

VGS = 10 V

 

9

 

nC

 

 

 

 

 

 

 

Body Diode Forward Voltage

VF(S-D)

IF = 3.0 A, VGS = 0 V

 

0.9

 

V

 

 

 

 

 

 

 

Reverse Recovery Time

trr

IF = 3.0 A, VGS = 0 V

 

160

 

ns

 

 

di/dt = 50 A/ μs

 

 

 

 

Reverse Recovery Charge

Qrr

 

280

 

nC

 

 

 

 

 

 

 

 

 

 

TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME

D.U.T.

 

D.U.T.

 

 

 

 

 

 

 

 

 

 

 

 

RG = 25 Ω

L

 

 

RL

VGS

 

 

90 %

PG

 

 

 

VGS

10 %

 

VGS(on)

 

 

 

 

 

 

 

 

Wave Form

 

 

 

50 Ω

VDD

RG

 

 

0

 

 

 

Ω

VDD

 

 

 

 

VGS = 20 0 V

PG.

RG = 10

 

 

 

 

 

 

 

 

ID

90 %

 

 

 

 

 

 

 

 

90 %

 

 

 

 

 

 

 

 

BVDSS

VGS

 

 

 

 

 

ID

 

 

 

ID

0 10 %

 

 

10 %

IAS

0

 

 

 

 

 

 

 

Wave Form

 

 

 

 

ID

VDS

 

 

 

td(on)

tr

td(off)

tf

τ

 

 

 

VDD

 

 

 

 

 

 

 

 

 

τ = 1μ s

 

 

 

 

ton

 

toff

 

 

 

 

 

 

 

 

Duty Cycle 1 %

Starting Tch

TEST CIRCUIT 3 GATE CHARGE

 

D.U.T.

 

 

IG = 2 mA

RL

 

 

PG.

50 Ω

VDD

2

Data Sheet G14283EJ1V0DS00

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