NEC UPA1560H Datasheet

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©
1999
COMPOUND FIELD EFFECT POWER TRANSISTOR
µ µ
PA1560
N-CHANNEL POWER MOS FET ARRAY
SWITCHING
INDUSTRIAL USE
DATA SHEET
Document No. G14283EJ1V0DS00 (1st edition)
Date Published April 1999 NS CP(K)
Printed in Japan
DESCRIPTION
The
µ
PA1560 is N-Channel Power MOS FET Array
that built in 4 circuits designed for solenoid, motor and
lamp driver.
FEATURES
Full mold package with 4 circuits
4 V driving is possible
Low on-state resistance
R
DS(on)1
= 165 m
MAX. (V
GS
= 10 V, I
D
= 1.5 A)
R
DS(on)2
= 200 m
MAX. (V
GS
= 4 V, I
D
= 1.5 A)
Low input capacitance
C
iss
= 600 pF TYP.
ORDERING INFORMATION
PART NUMBER PACKAGE
µ
PA1560H 10-pin SIP
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C)
Drain to Source Voltage (V
GS
= 0 V) V
DSS
120 V
Gate to Source Voltage (V
DS
= 0 V) V
GSS(AC)
±20 V
Gate to Source Voltage (V
DS
= 0 V) V
GSS(DC)
+ 20, –10 V
Drain Current (DC) I
D(DC)
±3.0 A
Drain Current (pulse)
Note1
I
D(pulse)
±12 A
Total Power Dissipation (T
C
= 25°C) P
T1
28 W
Total Power Dissipation (T
A
= 25°C) P
T2
3.7 W
Channel Temperature T
ch
150 °C
Storage Temperature T
stg
–55 to + 150 °C
Single Avalanche Current
Note2
I
AS
3.0 A
Single Avalanche Energy
Note2
E
AS
0.9 mJ
Notes 1.
PW
10
µ
s, Duty Cycle
1 %
2.
Starting T
ch
= 25
°C, V
DD
= 60
V, R
G
= 25
, V
GS
= 20
V
0
V
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
PACKAGE DRAWING (Unit : mm)
26.8 MAX.
4.0
10
2.5
1.4
12345678910
0.6±0.1
2.54
1.4
10 MIN.
0.5±0.1
EQUIVALENT CIRCUIT
3
2468
110
579
ELECTRODE CONNECTION
2, 4, 6, 8
3, 5, 7, 9
1, 10
: Gate
: Drain
: Source
Data Sheet G14283EJ1V0DS00
2
µ
µ µ
µ
PA1560
ELECTRICAL CHARACTERISTICS (T
A
= 25 °C)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Drain to Source On-state Resi stance R
DS(on)1
V
GS
= 10 V, I
D
= 1.5 A 130 165 m
R
DS(on)2
V
GS
= 4.0 V, I
D
= 1.5 A 145 200 m
Gate to Source Cut-off Voltage V
GS(off)
V
DS
= 10 V, I
D
= 1.0 mA 1.0 1.8 2.5 V
Forward Transfer Admittance | y
fs
|V
DS
= 10 V, I
D
= 1.5 A 2 4.5 S
Drain Leakage Current I
DSS
V
DS
= 120 V, V
GS
= 0 V 10
µ
A
Gate to Source Leakage Current I
GSS
V
GS
= ±20 V, V
DS
= 0 V ±10
µ
A
Input Capacitance C
iss
V
DS
= 10 V 600 pF
Output Capacitance C
oss
V
GS
= 0 V 160 pF
Reverse Transfer Capacitance C
rss
f = 1.0 MHz 70 pF
Turn-on Delay Time t
d(on)
I
D
= 1.5 A 35 ns
Rise Time t
r
V
GS(on)
= 10 V 80 ns
Turn-off Delay Time t
d(off)
V
DD
= 60 V 700 ns
Fall Time t
f
R
L
= 30
250 ns
Total Gate Charge Q
G
I
D
= 3.0 A 28 nC
Gate to Source Charge Q
GS
V
DD
= 96 V 2.5 nC
Gate to Drain Charge Q
GD
V
GS
= 10 V 9 nC
Body Diode Forward Voltage V
F(S-D)
I
F
= 3.0 A, V
GS
= 0 V 0.9 V
Reverse Recovery Time t
rr
160 ns
Reverse Recovery Charge Q
rr
I
F
= 3.0 A, V
GS
= 0 V
di/dt = 50 A/
µ
s
280 nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
R
G
= 25
50
PG
L
V
DD
V
GS
= 20 0 V
BV
DSS
I
AS
I
D
V
DS
Starting T
ch
V
DD
D.U.T.
TEST CIRCUIT 3 GATE CHARGE
PG.
50
D.U.T.
R
L
V
DD
I
G
= 2 mA
90 %
V
GS(on)
90 %
t
d(off)
t
f
10 %
I
D
t
off
TEST CIRCUIT 2 SWITCHING TIME
PG.
R
G
0
V
GS
D.U.T.
R
L
V
DD
τ = 1 s
µ
Duty Cycle 1 %
V
GS
Wave Form
I
D
Wave Form
V
GS
10 %
10 %
0
I
D
90 %
t
d(on)
t
r
τ
R
G
= 10
0
t
on
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