NEC Electronics Inc UPB1005K-E1, UPB1005K Datasheet

PRELIMINARYD TA SHEETDATA SHEET

BIPOLAR ANALOG + DIGITAL INTEGRATED CIRCUIT

μPB1005K

REFERENCE FREQUENCY 16.368 MHz, 2ND IF FREQUENCY 4.092 MHz

RF/IF FREQUENCY DOWN-CONVERTER +

PLL FREQUENCY SYNTHESIZER IC FOR GPS RECEIVER

DESCRIPTION

The μPB1005K is a silicon monolithic integrated circuit for GPS receiver. This IC is designed as double conversion RF block integrated RF/IF down-converter + PLL frequency synthesizer on 1 chip.

The μPB1005K features 36-pin plastic QFN, fixed prescaler and supply voltage. The 36-pin plastic QFN package is suitable for high density surface mounting. The fixed division internal prescaler is needless to input serial counter data. Supply voltage is 3 V. Thus, the μPB1005K can make RF block fewer components and lower power consumption.

This IC is manufactured using NEC’s 20 GHz fT NESATTMIII silicon bipolar process. This process uses direct silicon nitride passivation film and gold electrodes. These materials can protect the chip surface from pollution and prevent corrosion/migration. Thus, this IC realizes excellent performance, uniformity and reliability.

FEATURES

•	Double conversion		:	fREFin = 16.368 MHz, f2ndIFout = 4.092 MHz
•	Integrated RF block		:	RF/IF frequency down-converter + PLL frequency synthesizer
•	High-density surface mountable :			36-pin plastic QFN (6.0 × 6.0 × 0.95 mm)
• Needless to input counter data			:	fixed division internal prescaler
	•	VCO side division	:	÷ 200 (÷ 25, ÷ 8 serial prescaler)
	•	Reference division	:	÷ 2
•	Supply voltage		:	VCC = 2.7 to 3.3 V
•	Low current consumption		:	ICC = 45.0 mA TYP.@VCC = 3.0 V
•	Gain adjustable externally		:	Gain control voltage pin (control voltage up vs. gain down)

APPLICATION

• Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz

ORDERING INFORMATION

Part Number	Package	Supplying Form
μPB1005K-E1	36-pin plastic QFN	Embossed tape 12 mm wide.
		Pin 1 is in pull-out direction.
		Qty 2.5 kp/reel.

Remark To order evaluation samples, please contact your local NEC sales office. (Part number for sample order: μPB1005K)

Caution Electro-static sensitive device

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. P14016EJ1V0DS00 (1st edition)

Date Published November 1999 N CP(K)

©

1999

Printed in Japan

μPB1005K

PIN CONNECTION AND INTERNAL BLOCK DIAGRAM

IF-MIXout

N.C.

VGC

(IF-MIX)

VCC

(IF-MIX)

N.C.

IF-MIXin

GND (IF-MIX)

RF-MIXout

VCC

(RF-MIX)

GND (2ndIF-AMP)	2ndIFin1	2ndIFin2	2ndIFbypass	VCC (2ndIF-AMP)	2ndIFout	N.C.	REFout	VCC (reference block)
27	26	25	24	23	22	21	20	19
28
29
30							÷2
31
32					÷8
33				÷25
							PD
34
35
36
1	2	3	4	5	6	7	8	9
RF-MIXin	GND (RF-MIXin)	VCC (1stLO-OSC)	1stLO-OSC1	1stLO-OSC2	GND (1stLO-OSC)	VCC (phase detector)	N.C.	PD-Vout3

18 N.C.

17 REFin

16 N.C.

GND

15 (divider block)

14 LOout

13VCC

(divider block)

12 (PhaseGND detector)

11 PD-Vout1

10 PD-Vout2

2	Preliminary Data Sheet P14016EJ1V0DS00

μPB1005K

PRODUCT LINE-UP (TA = +25 °C, VCC = 3.0 V)

	Type	Part Number	Functions	VCC	ICC	CG	Package	Status
			(Frequency unit: MHz)	(V)	(mA)	(dB)
	General	μPC2756T	RF down-converter with osc. Tr	2.7 to 3.3	6.0	14	6-pin minimold	Available
	Purpose
		μPC2756TB					6-pin super minimold
	Wideband
		μPC2753GR	IF down-converter with gain	2.7 to 3.3	6.5	60 to 79	20-pin plastic SSOP
	Separate
			control amplifier				(225 mil)
	IC
	Clock	μPB1003GS	RF/IF down-converter	2.7 to 3.3	37.5	72 to 92	30-pin plastic SSOP	Discontinued
	Frequency		+ PLL synthesizer				(300 mil)
	Specific		REF = 18.414
	1 chip IC		1stIF = 28.644/2ndIF = 1.023
		μPB1004GS	RF/IF down-converter	2.7 to 3.3	37.5	72 to 92
			+ PLL synthesizer
		μPB1005GS		2.7 to 3.3	45.0	72 to 92		Available
			REF = 16.368
		μPB1005K					36-pin plastic QFN
			1stIF = 61.380/2ndIF = 4.092

Notice Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail.

To know the associated products, please refer to their latest data sheets.

SYSTEM APPLICATION EXAMPLE

GPS receiver RF block diagram

• f0 = 1.023 MHz in the diagram.

60f0

40f0

• μPB1005K is in

.

RF-MIXout

BPF

IF-MIXout

LPF

2ndlFin1

2ndlFin2

IF-MIXin

VGC

2ndlFbypass

LNA

1540f0

RF-MIX

IF-MIX

2ndlF-Amp

4.092 MHz

1575.42 MHz

1540f0

4f0

to Demodulator

from

Buff

Antenna

e.g.μ PC2749TB

BPF

64f0

8f0

16.368 MHz

16f0

1/25

1/8

P D

1/2

Buff

to Demodulator

1600f0

REF

OSC

8f0

LOOP

AMP

16f0

1stLO-OSC1

1stLO-OSC2

LOOUT

TCXO

VCC

16.368 MHz

Caution This diagram schematically shows only the μPB1005K’s internal functions on the system.

This diagram does not present the actual application circuits.

Preliminary Data Sheet P14016EJ1V0DS00

3

									μPB1005K
	ABSOLUTE MAXIMUM RATINGS
	Parameter	Symbol		Conditions				Rating		Unit
	Supply Voltage	VCC	TA = +25 °C					3.6		V
	Total Circuit Current	ICC	TA = +25 °C					120		mA
	Power Dissipation	PD	Mounted on double-sided copper clad					430		mW
			50 ´ 50 ´ 1.6 mm epoxy glass PWB (TA = +85 °C)
	Operating Ambient Temperature	TA						-40 to +85		°C
	Storage Temperature	Tstg						-55 to +150		°C
	RECOMMENDED OPERATING RANGE
	Parameter	Symbol	MIN.		TYP.			MAX.		Unit
	Supply Voltage	VCC	2.7		3.0		3.3			V
	Operating Ambient Temperature	TA	-40		+25		+85			°C
	RF Input Frequency	fRFin	¾		1575.42		¾			MHz
	1st LO Oscillating Frequency	f1stLOin	1616.80		1636.80		1656.80			MHz
	1st IF Input Frequency	f1stIFin	¾		61.38		¾			MHz
	2nd LO Input Frequency	f2ndLOin	¾		65.472		¾			MHz
	2nd IF Input/output Frequency	f2ndIFin	¾		4.092		¾			MHz
		f2ndIFout
	Reference Input/output Frequency	fREFin	¾		16.368		¾			MHz
		fREFout
	LO Output Frequency	fLOout	¾		8.184		¾			MHz

4	Preliminary Data Sheet P14016EJ1V0DS00

μPB1005K

ELECTRICAL CHARACTERISTICS (Unless otherwise specified TA = +25 °C, VCC = 3.0 V)

Parameter	Symbol	Conditions	MIN.	TYP.	MAX.	Unit
Total Circuit Current	ICCtotal	ICC1 + ICC2 + ICC3 + ICC4	32.0	45.0	60.0	mA
RF Down-converter Block (fRFin = 1575.42 MHz, f1stLOin = 1636.80 MHz, PLOin = -10 dBm, ZS = ZL = 50 W)
Circuit Current 1	ICC1	No Signals	6.0	10.0	14.0	mA
RF Conversion Gain	CGRF	PRFin = -40 dBm	12.5	15.5	18.5	dB
RF-SSB Noise Figure	NFRF	PRFin = -40 dBm	7.0	10.0	13.0	dB
Maximum IF Output	PO(sat)RF	PRFin = -10 dBm	-5.5	-2.5	+0.5	dBm
IF Down-converter Block (f1stIFIn = 61.38 MHz, f2ndLOIn = 65.472 MHz, ZS = 50 W, ZL = 2 kW)
Circuit Current 2	ICC2	No Signals	3.4	5.3	7.2	mA
IF Conversion Voltage Gain	CG(GV)IF	at Maximum Gain, P1stIFin = -50 dBm	38	41	44	dB
IF-SSB Noise Figure	NFIF	at Maximum Gain, P1stIFin = -50 dBm	8.5	11.5	14.5	dB
Maximum 2ndIF Output	PO(sat)IF	at Maximum Gain, P1stIFin = -20 dBm	-9.5	-6.5	-3.5	dBm
Gain Control Voltage	VGC	Voltage at Maximum Gain CGIF	¾	¾	1.0	V
Gain Control Range	DGC	P1stIFin = -50 dBm	20	¾	¾	dB
2nd IF Amplifier (f2ndIF = 4.092 MHz, ZS = 50 W, ZL = 2 kW)
Circuit Current 3	ICC3	No Signals	1.55	2.40	3.25	mA
Voltage Gain	GV	P2ndIFin = -60 dBm	37	40	43	dB
Output Power	P2ndIFout	P2ndIFin = -30 dBm	-14.5	-11.5	-8.5	dBm
PLL Synthesizer Block
Circuit Current 4	ICC4	PLL All Block Operating	18.5	28.5	38.5	mA
Phase Comparing	fPD	PLL Loop	8.0	8.184	8.4	MHz
Frequency
Reference Input Minimum	VREFin	ZL = 10 kW//20 pFNote	200	¾	¾	mVP-P
Level
Loop Filter Output Level (H)	VLP(H)		2.8	¾	¾	V
Loop Filter Output Level (L)	VLP(L)		¾	¾	0.4	V
Reference Output Swing	VREFout	ZL = 10 kW//2 pF Note	1.0	¾	¾	VP-P

Note Impedance of measurement equipment

Preliminary Data Sheet P14016EJ1V0DS00

5