NEC Electronics Inc UPB1005GS-E1, UPB1005GS Datasheet

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DATA SHEET

BIPOLAR ANALOG + DIGITAL INTEGRATED CIRCUIT

μPB1005GS

REFERENCE FREQUENCY 16.368 MHz, 2ND IF FREQUENCY 4.092 MHz

RF/IF FREQUENCY DOWN-CONVERTER +

PLL FREQUENCY SYNTHESIZER IC FOR GPS RECEIVER

DESCRIPTION

The μPB1005GS is a silicon monolithic integrated circuit for GPS receiver. This IC is designed as double conversion RF block integrated RF/IF down-converter + PLL frequency synthesizer on 1 chip.

The μPB1005GS features shrink package, fixed prescaler and supply voltage. The 30-pin plastic SSOP package is suitable for high density surface mounting. The fixed division internal prescaler is needless to input serial counter data. Supply voltage is 3 V. Thus, the μPB1005GS can make RF block fewer components and lower power consumption.

This IC is manufactured using NEC’s 20 GHz fT NESATTMIII silicon bipolar process. This process uses direct silicon nitride passivation film and gold electrodes. These materials can protect the chip surface from pollution and prevent corrosion/migration. Thus, this IC realizes excellent performance, uniformity and reliability.

FEATURES

Double conversion

:

fREFin = 16.368 MHz, f2ndIFout = 4.092 MHz

Integrated RF block

:

RF/IF frequency down-converter + PLL frequency synthesizer

High-density surface mountable :

30-pin plastic SSOP (9.85 × 6.1 × 2.0 mm)

• Needless to input counter data

:

fixed division internal prescaler

 

VCO side division

:

÷ 200 (÷ 25, ÷ 8 serial prescaler)

 

Reference division

:

÷ 2

Supply voltage

:

VCC = 2.7 to 3.3 V

Low current consumption

:

ICC = 45.0 mA TYP.@VCC = 3.0 V

Gain adjustable externally

:

Gain control voltage pin (control voltage up vs. gain down)

APPLICATION

• Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz

ORDERING INFORMATION

Part Number

Package

Supplying Form

 

 

 

μPB1005GS-E1

30-pin plastic SSOP

Embossed tape 16 mm wide.

 

(7.62 mm (300))

Pin 1 is in tape pull-out direction.

 

 

QTY 2.5 kpcs/reel.

 

 

 

Remark To order evaluation samples, please contact your local NEC sales office. (Part number for sample order: μPB1005GS)

Caution Electro-static sensitive devices

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. P13860EJ3V0DS00 (3rd edition)

The mark shows major revised points.

 

 

Date Published April 2000 N CP(K)

©

 

1998, 2000

Printed in Japan

 

 

 

 

μPB1005GS

PIN CONNECTIONS AND INTERNAL BLOCK DIAGRAM

IF-MIXin

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

GND (IF-MIX)

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

RF-MIXout

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

VCC (RF-MIX)

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

RF-MIXin

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND (RF-MIX)

 

 

 

 

 

 

 

÷25

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC (1stLO-OSC)

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

 

 

1stLO-OSC1

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

1stLO-OSC2

 

 

 

 

 

 

 

÷8

 

9

 

 

 

 

 

 

 

 

 

 

 

 

GND (1stLO-OSC)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

VCC (phase detector)

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PD-Vout3

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

PD

 

 

 

 

 

 

 

 

 

 

 

PD-Vout2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

 

 

 

 

 

 

PD-Vout1

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

 

 

 

 

 

 

 

 

GND (phase detector)

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30 VCC (IF-MIX)

29 VGC (IF-MIX)

28 IF-MIXout

27 GND (2ndIF-AMP)

26 2ndlFin1

25 2ndlFin2

24 2ndlFbypass

23 VCC (2ndIF-AMP)

22 2ndIFout

21 REFout

20 VCC (reference block)

÷2

 

 

 

 

REFin

 

 

 

19

 

 

 

 

 

 

 

 

 

 

 

18 GND (divider block) 17 LOout

16 VCC (divider block)

2

Data Sheet P13860EJ3V0DS00

NEC Electronics Inc UPB1005GS-E1, UPB1005GS Datasheet

μPB1005GS

PRODUCT LINE-UP (TA = +25°C, VCC = 3.0 V)

Type

Part Number

Functions

VCC

ICC

CG

TA

Package

Status

(Frequency unit: MHz)

(V)

(mA)

(dB)

(°C)

 

 

 

 

 

 

 

 

 

 

 

 

 

General

μPC2756T

RF down-converter with osc. Tr

2.7 to 3.3

6

14

40 to

6-pin

Available

Purpose

 

 

 

 

 

+85

minimold

 

Wideband

 

 

 

 

 

 

 

 

μPC2756TB

 

 

 

 

 

6-pin super

 

Separate

 

 

 

 

 

 

 

 

 

 

 

 

minimold

 

IC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

μPC2753GR

IF down-converter with gain

2.7 to 3.3

6.5

60 to 79

 

20-pin plastic

 

 

 

 

 

 

control amplifier

 

 

 

 

SSOP

 

 

 

 

 

 

 

 

 

 

Clock

μPB1003GS

RF/IF down-converter

2.7 to 3.3

37.5

72 to 92

20 to

30-pin plastic

Discontinued

Frequency

 

+ PLL synthesizer

 

 

 

+85

SSOP

 

Specific

 

REF = 18.414

 

 

 

 

 

 

1 chip IC

 

1stIF = 28.644/2ndIF = 1.023

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

μPB1004GS

RF/IF down-converter

2.7 to 3.3

37.5

72 to 92

20 to

 

 

 

 

+ PLL synthesizer

 

 

 

+85

 

 

 

 

REF = 16.368

 

 

 

 

 

 

 

μPB1005GS

2.7 to 3.3

45.0

72 to 92

40 to

 

Available

 

1stIF = 61.380/2ndIF = 4.092

 

 

 

 

 

 

+85

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Remark Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail.

To know the associated products, please refer to their latest data sheets.

SYSTEM APPLICATION EXAMPLE

GPS receiver RF block diagram

 

 

 

 

 

 

 

 

 

 

f0 = 1.023 MHz in the diagram.

 

 

 

 

60f0

 

40f0

 

 

 

μPB1005GS is in

.

 

 

 

 

BPF

 

LPF

2ndlFin1

 

 

 

 

 

 

RF-MIXout

IF-MIXin

IF-MIXout

 

2ndlFin2

 

 

 

 

VGC

 

 

 

 

 

 

 

 

 

 

 

 

2ndlFbypass

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LNA

1540f0

RF-MIX

 

IF-MIX

 

 

2ndlF-Amp

 

4.092 MHz

 

 

 

 

 

 

 

 

 

 

1575.42 MHz

 

1540f0

 

 

 

 

 

 

 

4f0

 

to Demodulator

from

 

 

 

 

 

 

 

 

Buff

 

 

 

 

 

 

 

 

 

Antenna

 

 

 

 

 

 

 

 

 

 

 

 

example: μ PC2749TB

BPF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64f0

 

 

 

 

 

 

 

 

 

 

 

 

8f0

 

 

 

 

16.368 MHz

 

 

 

 

 

 

 

 

 

 

16f0

 

 

 

 

 

1/25

1/8

P D

 

1/2

 

Buff

to Demodulator

 

 

 

 

 

 

 

 

 

1600f0

 

 

 

 

 

REF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OSC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8f0

LOOP

 

 

 

 

 

 

 

 

 

 

 

AMP

 

 

16f0

 

 

 

 

 

1stLO-OSC1

1stLO-OSC2

LOout

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCXO

 

 

 

 

 

 

 

 

 

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

16.368 MHz

 

 

 

Caution This diagram schematically shows only the μPB1005GS’s internal functions on the system.

This diagram does not present the actual application circuits.

Data Sheet P13860EJ3V0DS00

3

 

 

 

 

 

 

 

 

μPB1005GS

 

ABSOLUTE MAXIMUM RATINGS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

Symbol

 

Conditions

 

Ratings

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

Supply Voltage

VCC

TA = +25°C

 

 

 

 

3.6

V

 

 

 

 

 

 

 

 

 

 

 

 

 

Total Circuit Current

ICC

TA = +25°C

 

 

 

 

128

mA

 

 

 

 

 

 

 

 

 

 

 

 

Power Dissipation

PD

Mounted on double-sided copper clad

 

464

mW

 

 

 

 

50 ´ 50 ´ 1.6 mm epoxy glass PWB at TA = +85°C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operating Ambient Temperature

TA

 

 

 

 

 

-40 to +85

°C

 

 

 

 

 

 

 

 

 

 

 

 

 

Storage Temperature

Tstg

 

 

 

 

 

-55 to +150

°C

 

 

 

 

 

 

 

 

 

 

 

 

 

RECOMMENDED OPERATING RANGE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

Symbol

MIN.

 

TYP.

 

 

MAX.

Unit

 

 

 

 

 

 

 

 

 

 

 

 

Supply Voltage

VCC

2.7

 

3.0

 

3.3

V

 

 

 

 

 

 

 

 

 

 

 

 

Operating Ambient Temperature

TA

-40

 

+25

 

+85

°C

 

 

 

 

 

 

 

 

 

 

 

 

RF Input Frequency

fRFin

¾

 

1575.42

 

¾

MHz

 

 

 

 

 

 

 

 

 

 

 

 

1stLO Oscillating Frequency

f1stLOin

1616.80

 

1636.80

 

1656.80

MHz

 

 

 

 

 

 

 

 

 

 

 

 

1stIF Input Frequency

f1stIFin

¾

 

61.380

 

¾

MHz

 

 

 

 

 

 

 

 

 

 

 

 

2ndLO Input Frequency

f2ndLOin

¾

 

65.472

 

¾

MHz

 

 

 

 

 

 

 

 

 

 

 

 

2ndIF Input/output Frequency

f2ndIFin

¾

 

4.092

 

¾

MHz

 

 

 

f2ndIFout

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reference Input/output Frequency

fREFin

¾

 

16.368

 

¾

MHz

 

 

 

fREFout

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

Data Sheet P13860EJ3V0DS00

μPB1005GS

ELECTRICAL CHARACTERISTICS (Unless otherwise specified, TA = +25°C, VCC = 3.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

 

 

 

 

 

 

 

Total Circuit Current

ICCtotal

ICC1 + ICC2 + ICC3 + ICC4

32.0

45.0

60.0

mA

 

 

 

 

 

 

 

RF Down-converter Block (fRFin = 1575.42 MHz, f1stLOin = 1636.80 MHz, PLOin = -10 dBm, ZL = ZS = 50 W)

 

 

 

 

 

 

 

 

 

Circuit Current 1

ICC1

No Signals

6.0

10.0

14.0

mA

 

 

 

 

 

 

 

RF Conversion Gain

CGRF

PRFin = -40 dBm

12.5

15.5

18.5

dB

 

 

 

 

 

 

 

RF-SSB Noise Figure

NFRF

PRFin = -40 dBm

7

10

13

dB

 

 

 

 

 

 

 

Maximum IF Output Power

PO(sat)RF

PRFin = -10 dBm

-5.5

-2.5

+0.5

dBm

 

 

 

 

 

 

 

IF Down-converter Block (f1stIFIn = 61.38 MHz, f2ndLOIn = 65.472 MHz, ZS = 50 W, ZL = 2 kW)

 

 

 

 

 

 

 

 

 

 

Circuit Current 2

ICC2

No Signals

3.4

5.3

7.2

mA

 

 

 

 

 

 

 

IF Voltage Conversion Gain

CG(GV)IF

at Maximum Gain, P1stIFin = -50 dBm

38

41

44

dB

 

 

 

 

 

 

 

IF-SSB Noise Figure

NFIF

at Maximum Gain, P1stIFin = -50 dBm

8.5

11.5

14.5

dB

 

 

 

 

 

 

 

Maximum 2nd IF Output

PO(sat)IF

at Maximum Gain, P1stIFin = -20 dBm

-9.5

-6.5

-3.5

dBm

Power

 

 

 

 

 

 

 

 

 

 

 

 

 

Gain Control Voltage

VGC

Voltage at Maximum Gain of CGIF

¾

¾

1.0

V

 

 

 

 

 

 

 

Gain Control Range

DGC

P1stIFin = -50 dBm

20

¾

¾

dB

 

 

 

 

 

 

 

2nd IF Amplifier (f2ndIF = 4.092 MHz, ZS = 50 W, ZL = 2 kW)

 

 

 

 

 

 

 

 

 

 

 

Circuit Current 3

ICC3

No Signals

1.55

2.40

3.25

mA

 

 

 

 

 

 

 

Voltage Gain

GV

P2ndIFin = -60 dBm

37

40

43

dB

 

 

 

 

 

 

 

Maximum Output Power

PO(sat)

P2ndIFin = -30 dBm

-14.5

-11.5

-8.5

dBm

 

 

 

 

 

 

 

PLL Synthesizer Block

 

 

 

 

 

 

 

 

 

 

 

 

 

Circuit Current 4

ICC4

PLL All Block Operating

18.5

28.5

38.5

mA

 

 

 

 

 

 

 

Phase Comparing

fPD

PLL Loop

8.0

8.184

8.4

MHz

Frequency

 

 

 

 

 

 

 

 

 

 

 

 

 

Reference Input Minimum

VREFin

ZL = 10 kW//20 pF (Impedance of

200

¾

¾

mVP-P

Level

 

measurement equipment)

 

 

 

 

 

 

 

 

 

 

 

Loop Filter Output Level (H)

VLP(H)

 

2.8

¾

¾

V

 

 

 

 

 

 

 

Loop Filter Output Level (L)

VLP(L)

 

¾

¾

0.4

V

 

 

 

 

 

 

 

Reference Output Swing

VREFout

ZL = 10 kW//2 pF (Impedance of

1.0

¾

¾

VP-P

 

 

measurement equipment)

 

 

 

 

 

 

 

 

 

 

 

Data Sheet P13860EJ3V0DS00

5

 

 

 

 

 

μPB1005GS

 

STANDARD CHARACTERISTICS (Unless otherwise specified TA = +25°C, VCC = 3.0 V)

 

 

 

 

 

 

 

 

 

 

 

Parameter

Symbol

Conditions

Reference

 

Unit

 

 

 

 

 

 

 

 

 

 

RF Down-converter Block (P1stLOin = 10 dBm, ZL = ZS = 50 Ω)

 

 

 

 

 

 

 

 

 

 

 

 

 

LO Leakage to IF Pin

LOif

f1stLOin = 1636.80 MHz

30

 

dBm

 

 

 

 

 

 

 

 

 

 

LO Leakage to RF Pin

LOrf

f1stLOin = 1636.80 MHz

30

 

dBm

 

 

 

 

 

 

 

 

 

 

Input 3rd Order Intercept

IIP3RF

fRFin1 = 1600 MHz, fRFin2 = 1605 MHz

13

 

dBm

 

 

Point

 

f1stLOin = 1660 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

IF Down-converter Block (1stLO oscillating, ZS = 50 Ω, ZL = 2 kΩ)

 

 

 

 

 

 

 

 

 

 

 

 

 

LO Leakage to 2nd IF Pin

LO2ndif

f2ndLOin = 65.472 MHz

20

 

dBm

 

 

 

 

 

 

 

 

 

 

LO Leakage to 1st IF Pin

LO1stif

f2ndLOin = 65.472 MHz

40

 

dBm

 

 

 

 

 

 

 

 

 

 

Input 3rd Order Intercept

IIP3IF

f1stIFin1 = 61.38 MHz, f1stIFIn2 = 61.48 MHz

34

 

dBm

 

 

Point

 

f2ndLOin = 65.472 MHz

 

 

 

 

 

 

 

 

 

 

 

 

6

Data Sheet P13860EJ3V0DS00

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