MSI MS-7779 Schematics rev0B

1

Cover Sheet BLOCK DIAGRAM

Clock Distribution PWRGD&RESET Map GPIO/MSIC TABLE VRM Intersil 6277/6377 3+1 PHASE AMD FM2

DDR3 DIMM CH-A

DDR3 DIMM CH-B DDR REF POWER AND CAPS EMI Reserved

AMD HUDSON D2/3

A A

SWITCH/HDMI CONN.

TRAVIS & VGA CONN. SATA//eSATA/PS2/ FAN LAN RTL8111F SUPER I/O NCT5533D ACPI UPI & SYS POWER FCH CORE & DDR POWER Azalia CODEC ALC892/662 USB 2.0/3.0CONN.

1 2 3 Power Deliver Chart 4 5 6 7 8 ~ 11 12 13 14 15 16~20 21 22 23 24 25 26 27 28 29

(MS-7779L2 Ver:0B )

CPU:

AMD FM2(Trinity uPGA FAMILIES)

System Chipset:

AMD - Hudson D4/D3/D2

On Board Chipset:

CLOCK GEN --FCH internal clock gen LPC Super I/O --NCT5533D LAN-Realtek 8111F

Azalia CODEC - Realtek ALC892/662/888/

Main Memory:

DDR III * 4 (max 32G)

Expansion Slots:

PCI Express X16 Slot * 1 PCI Express X1 Slot * 3 PCI Express X1 Slot *1 for front USB3.0

mini PCI Express X1 Slot *1 for wifi LAN

mATX: 244mm * 244mm

VIRGO

USB POWER/DISCHARGE PCI EXPRESS X16 SLOT PCIE X1 SLOTs ATX & Front Panel Auto BOM Manual MINI PCIE CONN,

30 31 32 33 34 35

VRM

Controller - Intersil 6277/6377 3/4+2 Phase

1

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Virgo BLOCK DIAGRAM

D D

VGA CONNECTOR

22

VGA

HUDSON D3

18

VGA MAIN LINK

HDMI CON

PCIE GFX x16

C C

PCIE INTERFACE

10/100/Giga bit ETHERNET 8111F

B B

CPU CORE POWER NB CORE POWERACPI CONTROLLER Intersil ISL6323 Intersil ISL6277

7

PCIE x1 SLOT1,2,3

24

PCIE INTERFACE

31

26

CPU VDDP Power CPU VDDR Power CPU VDDA Power DUAL POWER

A A

DDR3 DRAM POWER FCH CORE POWER

ATX CON

5

26

27

32

4

DP 1

DP0

21

PCIE x16

30

USB REAR

/HDR

USB REAR

29

Only D3 support USB3.0

F_USB_30

29

Only D3 support USB3.0

MINI PCIe x1 slot

USB 2.0

USB 3.0

33

FM2

8~11

UMI

HUDSON D4. D3/D2

16~20

SUPER I/O NCT5533D

SERIAL PORT

3

25

DDRIII 1333~1866

AZALIA

SERIAL ATA 3.0

SPI Bus

25

CHA

CHB

UNBUFFERED DDRIII DIMM1 2

UNBUFFERED DDRIII DIMM3 4

ALC662/888/892

i-SATA [4:1]

23

e-SATA 5

23

SPI ROM 16M

18

2

12

13

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Power Deliver Chart

2.5V Shunt Regulator

VRM SW

D D

ATX P/S WITH 1A STBY CURRENT

5V

5VSB

+/-5%

C C

3.3V +/-5%

12V +/-5%

-12V +/-5%

CPU PW 12V +/-5%

5VDIMM Linear REGULATOR

VCC5_SB FET REGULATOR

VCC3_WAKE Linear REGULATOR

1.5V VDD SW REGULATOR

1.1V VCCP SW REGULATOR

VCC3_SB SW REGULATOR

VCC5_SB

REGUALTOR

VDDA25 (S0, S1)

VCCP (S0, S1) / VCC_NB (S0, S1)

1.2V VDDR REGULATOR

1.2V VDDP REGULATOR

0.75V VTT_DDR REGULATOR

CPU_VDDR (S0, S1)

CPU_VDDP (S0, S1)

VCC_DDR (S0, S1, S3)

DDRIII DIMM X4

VDD MEM VTT_DDR

NB_VCC1P1 (S0, S1)

VCC3 (S0, S1)

VCC3_SB (S0, S1, S3, S5)

1.1V_SB Linear REGULATOR

+1.1VDUAL(S0,S1,S3,S5)

15A 2 A

OPTION

0R

AMD FM1 CPU

VDDA

2.5V(1.8~2.7V) VDDCORE

0.8-2V VDDNBCORE

1.2V CPU_VDDR

1.2V

CPU_VDDP

1.2V

DDR3 MEM I/F 1.5V VCC_DDR

0.8~2.3V TBD A

HUDSON 2/3

VDDPL_11_DAC

VDDAN_11_ML

VDDCR_11

VDDAN_11_SATA

VDDAN_11_CLK

VDDAN_11_PCIE

VDDIO_33_PCIGP 3.3V (S0, S1) VDDPL_33_*_RUN

VDDPL_33_*_ALW

VDDIO_33_GBE_S

VDDAN_33_USB_S

VDDXL_33_S

VDDIO_33_S

VDDCR/AN_11_SUSB_S

VDDCR/AN_11_USB_S

VDDCR_11_GBE_S

VDDCR_11_S

100 mA 500 mA 700 mA 400 mA 900 mA

300 mA 320 mA

34 mA 1 mA 130 mA 6 mA 30 mA

500 mA 52 mA 100 mA

100 mA

0.5A 120A

20A

5A

20 mA

B B

VCC3 (S0, S1)

+5VA Linear REGULATOR

SVCC Linear REGULATOR

SVCC(S0,S3)

+5VA (S0, S1)

AUDIO CODEC

3.3V CORE

5V ANALOG

0.1A

SUPER I/O

+3.3V (S0, S1)

VCC3_WAKE (S0, S1, S3, S5)

+3.3VDUAL (S3)

0.01A

VCC3_WAKE (S0, S1, S3, S5)

A A

5

COM Port

-12V

0.1A

X1 PCIE per

3.3V 12V

3.3Vaux

3.0A

0.5A

0.1A

4

X16 PCIE per

3.3V 12V

3.3VDual

3.0A

5.5A

0.3A

USB X6 FR

VDD 5VDual

3.8A

USB X4 RL 2XPS/2

5VDual

VDD

0.5A

5VDual

2.0A

3

ENTHENET

3.3V 1.05V

70mA

300mA

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INTERNAL CLOCK MODE

D D

CH A CH B

DIMM1

DIMM2

DIMM3

DIMM4

AMD HUDSON-D3/D2

MEM_MA_CLK_H0/L0

MEM_MA_CLK_H3/L3

MEM_MA_CLK_H2/L2

C C

MEM_MA_CLK_H1/L1

AMD

FM2 APU

B B

MEM_MB_CLK_H0/L0

MEM_MB_CLK_H3/L3

MEM_MB_CLK_H1/L1

MEM_MB_CLK_H2/L2

APU_CLKP/N

DISP_CLKP/N

FCH_APU_CLKP

FCH_DISP_CLKP 100MHZ (NO SPREAD)

USBCLK

14M_25M_48M_OSC

25M_X2

SATA_X1

25M_X1

25MHZ RTC CLOCK

FOR SATA DNI

25M Hz

32K_X1

SATA_X2

32.768K Hz

PCICLK0

PCICLK2

PCICLK3

PCICLK4

LPCCLK0 LPCCLK1

RTCCLK

AZ_BITCLK

SPI_CLK

FCH_GFX_CLKP/N

FCH_GPP_CLK0P/N

FCH_GPP_CLK1P/N

FCH_GPP_CLK2P/N

FCH_GPP_CLK3P/N

FCH_GPP_CLK4P/N

32K_X2

PCICLK1

33MHZ

PCI_CLK4

PCI_CLK3PCI_CLK2

33MHZ

LPC_CLK0

LPCCLK1

33MHZ

AZ_BIT_CLK

24MHZ

SPI_CLK

xxHZ

PE16_GXF_CLK/PE16_GXF_CLK#

100MHZ

PE1_GPP_CLK0/PE1_GPP_CLK0#

100MHZ

PE1_GPP_CLK1/PE1_GPP_CLK1#

100MHZ

PE1_GPP_CLK2/PE1_GPP_CLK2#

100MHZ

PE_LAN_CLK/PE_LAN_CLK#

100MHZ

SIO NCT6776F

STRAPS SETTING,

UNUSED CLOCKS

STRAPS SETTING,

RESERVE TP

HD AUDIO

SPI ROM & HEADER

PCIE GFX SLOT (FM1, 16 LANES)

PCIE GPP SLOT1 (HUDSON-D3, 1 LANE)

PCIE GPP SLOT2 (HUDSON-D3, 1 LANE)

PCIE GPP SLOT3(HUDSON-D3, 1 LANE)

PCIE LAN (FM1, 1 LANE)

reserve LAN_CLKREQ#

PCIEX16 SLOT

PCIE X1 SLOT

PCIE LAN

PCIE LAN RTL8111E

25M Hz

A A

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FM2

PWROK(Pin AG11)

4

PWRGD MAP

3

2

1

POWER ON SEQUENCE

HUDSON D3/D2

APU_PG(Pin E26)

D D

PWR_BTN#(Pin J4)

SLP_S3#(Pin T3)

SLP_S5#(Pin W2)

APU_PWRGD

FCH_PWRGDPWR_GD(Pin N7)

NCT 6776F

SLP_S5#

SLP_S5#(Pin 84)

SUSB#(Pin 64)SLP_S3#

PSOUT# (Pin 60)PSOUT#

ATX_POWER

U16

NCP1587

VRM U5

ISL6328CR

VDDPWRGD(Pin 34)

U32

NCP1587

U41

*

PS_ON#

FCH_PWRGD

CPU_VDD

VRM_PWRGD

U30

NCP102

Pin16

ATX_PWROK U23 (UP7501) 5VDIMM

Pin8

F_PANEL1PSIN#

VCC_DDR

CPU_VDDP CPU_VDDR

NB_VCC1P1

*

U54 (UP7704) VDDA_25

MEANS OPTION

PSON# (Pin 63)

PSIN# (Pin 61)

C C

ATX_PWROK

SLP_S5#

ATX_PWROK APU_FM1R1 VCC_DDR

VRM_PWRGD

B B

ATX_PWROK NB_VCC1P1 FP_RST# SLP_S3#

D41

CPU_VDDP_VDDR_EN

NBCORE_EN

D40

DDR_EN

VCORE_EN

APU_PWRGD

FCH_PWRGD_R

EN(Pin 25)

PWROK(Pin 35)

RESET MAP

FM2

RESET_L(Pin AJ13)

HUDSON D3/D2

CLK GEN

Reserve TP Reserve TP

PCIE_RST#(Pin AE2)

A_RST#(Pin AD5)Super IO

PCIE_RST2#(Pin AB6) PCIRST#(Pin AB5)

5

PCIE 16X slot PCIE 1X slot 1 PCIE 1X slot 2 PCIE LAN

A A

LPC debug

ICS-9VRS4818

APU_RST#(Pin F26)

SYS_RESET#(Pin U4)

FP_RST#

APU_RST#

RESET#(Pin 12)RESET_IN#(Pin 70)

F_PANEL

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PWRGD/RESET MAP

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DDR DIMM Config.

SIO NCT6776F GPIO Config

D D

50 GP60 VSB

78 GP36 VSB SIO_VDUAL_EN

GPIO Power Rail Function descriptionPin

GP4638 VSB SIO_WAKE

YLW_LED/GP4539 VSB

GRN_LED/GP4440 VSB PWR_LED

GP6742 VSB

GP6544

GP6445 VSB

GP6347 VSB

GP6248 VSB

GP6149 VSB

VSB

SUS_LED

USB_EN

MB_ID0

MB_ID1

MB_ID2

COM_GPIO2

CHASSIS_ID1

CHASSIS_ID2

Comment

OD

GPI

reserved

DEVICE

DIMM 1

10100000B

CH-A

10100010B A4H

CH-A MEM_MA_CLK_H3/L3

DIMM 3

10100001B

CH-B

DIMM 4

10100011B A6H

CH-B

CLOCKADDRESS

MEM_MA_CLK_H1/L1

A0H

MEM_MA_CLK_H2/L2

MEM_MA_CLK_H0/L0DIMM 2

MEM_MB_CLK_H1/L1

A2H

MEM_MB_CLK_H2/L2

MEM_MB_CLK_H0/L0 MEM_MB_CLK_H3/L3

SMBus TABLE

FCH HUDSON D3/D2GPIO Config

AJ3

C C

B B

AD22 SATA_ACT#/GPIO67 SATA_LED#:SATA Channel Active

M6

V3 SPI_CLK/GPIO162 SPI Clock

V6 SPI_DI/GPIO164 SPI Data In

V5 SPI_DO/GPIO163 SPI Data Output

T6 SPI_CS1#/GPIO165 SPI Chip Select1#

Y6 SPI_HOLD#/GEVENT9# SPI HOLD#. Assert low to hold the SPI transaction.

J7 USB_OC1#/TDI/GEVENT13# OC#1:USB2.0 port 4,5

P5 USB_OC2#/TCK/GEVENT14#

P5 USB_OC3#/

P6 USB_OC4#/IR_RX0/

T1 OC#5:USB2.0 port 2,3

R8 OC#6:USB2.0 port 0,1

M7 OC#7:USB 3.0 port 2,USB 2.0 port12BLINK/USB_OC7#/

pin Name Function description

AD0/GPIO0 CLEAR_CMOS

IR_LED#/LLB#/GPIO184 MINI_PWRONJ2

TEMPIN3/TALERT#/ GPIO174

ROM_RST#/SPI_WP#/GPIO161V1 SPI write protect (active low)

USB_OC0#/SPI_TPM_CS#/ TRST#/GEVENT12#

AC_PRES/TDO/GEVENT15#

GEVENT16# USB_OC5#/IR_TX0/ GEVENT17# USB_OC6#/IR_TX1/ GEVENT6#

GEVENT18#

GPIO[171::173];GPIO[175::182]; GPIO[193::194]

FCH_TALERT#:Thermal Alert. The FCH can be programmed to generate an SMI, SCI, or IRQ13 through GPE, or generate an SMI without GPE in response to the signal’s assertion.

OC#0:USB 3.0 port 3,USB 2.0 port 13T8

OC#2:USB2.0 port 8,9

OC#3:USB 3.0 port 0,USB 2.0 port 10

OC#4:USB 3.0 port 1,USB 2.0 port 11

Configure as one of the following: 10-kΩ 5% pull-up resistor to +3.3V_S5. 10-kΩ 5% pull-down resistor.

SOURCE

DP0_AUXP_C /DP0_AUXN_C

APU

DP1_AUXP_C /DP1_AUXN_C

SCLK0/SDATA0

FCH

SCLK1/SDATA1 LAN,PCIE SLOTs,MINI_PCIE

SCLK3/SDATA3 TP

RESET TABLE

SOURCE

PCIE_RST# PCIe 16X,1X,LAN,MINI_PCIE

FCH

FRONT PANEL

A_RST# SIO,LPC debug PCIE_RST2# RESERVE TP LDT_RST# APU AZ_RST# AZALIA CODEC DDR3_RST# NC FC_RST# DEBUG BUS ROM_RST# NC FP_RST# FCH,CLOCK GEN

LINKED DEVICESINGLE NAME

HDMI

Hudson D2/3 DP to VGA translator

DIMMs,CLOCK GEN ,SIO

LINKED DEVICESINGLE NAME

A A

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GPIO/MSIC TABLE

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VID Override Circuit

R231KR23

R561KR56

1K

APU_SVC10 APU_SVD10

APU_SVT10

APU_PWRGD

,16

Note: Remove R28, R29, R30, install R32

D D

set VID via SWITCH_VRM

SVC SVD

00 0

C C

1K

APU_PG: from FCH to APU & UP1640 PU 330R to VCC_DDR

To override VID,

BOOT VOLTAGE

Pre_PWROK Metal VID

1.1

1.0

1

0.9

01 1.0

0.8

11

VCCP

R20

10R0402

R22

COREFB+10

0R0402

R24 0R0402R24 0R0402

COREFB-10

R27

NB_SENSE+10

NB_SENSE-10

CLOSE CHOKE8 CLOSE CHOKE10

VCCP

R75

R75 X_1KR0402

X_1KR0402

VRM_PWRGD_R

R76 X_10KR0402R76 X_10KR0402

B B

ATX_PWROK25,26,27,33,34 APU_FM2R110

VCORE_EN_R25,27

ATX_12V

2

1

GND GND

5

VCC5

R155

X_0R0805

R153 X_0R0805R153 X_0R0805

A A

C593

X_C1u6.3X50402-HF

VCC_DDRVCC_DDR

R34

R2551KR255 1K

R60 0RR60 0R R230 0RR230 0R R247 33RR247 33R SP1SP1

R34

R35

X_1K

R259

R199

R226

X_1K

VRM_PWRGD27

V_FIX Mode

1.4

1.2

0.8

C123

10R0402

R41

R43

0R0402

VSUM+ NB_VSUM+

2.61KR1%0402

RT1

10KRT1%

D11 S-RB751V-40_SOD323-RHD11 S-RB751V-40_SOD323-RH D72 S-RB751V-40_SOD323-RHD72 S-RB751V-40_SOD323-RH

VCORE_EN_R

4

12V

3

12V

PWR-2X2M_natural-RH

R15 301R1%0402R15 301R1%0402

C14

C1000p50X0402

R19

3.83KR1%0402

C330p16N0402-RH-1

C21

C330p16N0402-RH-1

C130

C1000p50X0402

CPU_VDDNB

R104

10R0402

C108

C330p16N0402-RH-1

0R0402

R106

C109

C1000p50X0402

10R0402

R107

C38

C41

C0.33u6.3X50402-RH

R52

C0.22u50X_0805

11KR0.5%0402-RH

C118

C0.1u16X0402

VCC5

R70

DS

X_10KR0402

G

Q9

C

B

E

X_N-SST3904_SOT23

+12VIN

C107

C0.1u16Y0402

BOOT4 PH4

R135 X_0R0805R135 X_0R0805

U6

BOOT4

2

BOOT

7

FCCM

6

VCC

PWM4

3

PWM

4

GND

5

VRM_PWRGD_R VRM_PWROK VCORE_EN

R36

VCC5

X_1K

SVC SVD SVT

R97

VRM_PWROK

VCC_DDR

C26

C470p50X0402

R125

X_100R0402

G

X_ISL62081CRZU6X_ISL62081CRZ

1KR1%0805

X_1KR1%0805

R73

R73 X_220R

X_220R

R18 0R0402R18 0R0402

SVC SVD SVT

TP39TP39

C44 C100p50N0402C44 C100p50N0402

R14

137KR1%0402

R17 41.2KR1%0402R17 41.2KR1%0402

R21

3.83KR1%0402

R96

499R1%0402

R113

5.6KR1%0402

C30

C330p16N0402-RH-1

C137 C0.33u6.3X50402-RHC137 C0.33u6.3X50402-RH

R53

649R1%0402

10KRT1%

NB_VSUM-VSUM-

VRM_PWRGD

C90

Q17

X_C0.1u16Y0402

X_N-2N7002_SOT23

VCC5 +12VIN

R74

R74 10KR0402

10KR0402

DS

Q15

Q15 N-2N7002_SOT23

N-2N7002_SOT23

CHOKE7

CH-1.2u15A1.7m-RH-2

1 2

C163 X_C0.22u16XC163 X_C0.22u16X

UG4

R145 X_0R0805R145 X_0R0805

1

UGATE

PH4

8

PHASE

LG4

5

LGATE

GND_P

9

R91

C16

C110 C2200p50X0402C110 C2200p50X0402

R95

RT2

X_10KR0402

C126 X_C0.1u16Y0402C126 X_C0.1u16Y0402 C125 X_C0.1u16Y0402C125 X_C0.1u16Y0402 C45 C2.2u6.3X50402C45 C2.2u6.3X50402

VCC5 VCC5

R92

X_1KR1%0805

PG_NB

VRM_PWROK

C330p50N0402

C17 C10p25N0402-RH-2C17 C10p25N0402-RH-2

C139 C100p50N0402C139 C100p50N0402

143KR1%0402

R103

R120

5.6KR1%0402

2.61KR1%0402

R110

11KR0.5%0402-RH

C0.1u50X0805

R112

C119

Make sure +12VIN connector plug in

R116

10.7KR1%0402

DS

Q16

G

N-2N7002LT1G_SOT23-RH

VIN

R123

4 G

4 3 2 1

X_N-P0403BK_GEM-PAK8-RH

VCORE_EN

VRM_PWRGD_R

R88 X_0R0402R88 X_0R0402

C128

X_C0.1u16X0402

R90

X_24.9KR1%0402

C140

C470p50X0402

X_32.4KR1%0402

C141 C2200p50X0402C141 C2200p50X0402

C40

C42

C0.33u25X0805

C0.1u16X0402

VIN

DS

1 2 3

Q93

X_N-P0903BD

5

Q92

X_N-P0403BK_GEM-PAK8-RH

R124 X_100R0402R124 X_100R0402

R115

3.3KR0402

X_C1u16X5-RH

4 3 2 1

C132 C0.33u6.3X50402-RHC132 C0.33u6.3X50402-RH

4 G

4

C1u6.3X50402-HF

23 42

10

22

20 21

18

19

43

44

45

16

17

47

46

R111 422R1%0402R111 422R1%0402

C92

C92 C2.2U6.3X0603

C2.2U6.3X0603

C365

DS

1

X_C10u16X50805-HF

2 3

Q94

X_N-P0903BD

5

Q80

VSUM+ ISEN4

VSUM-

4

9

ENABLE PGOOD

PGOOD_NB PWROK

4

SVC

6

SVD

8

SVT

5

VR_HOT_L

7

VDDIO

COMP

FB2 FB

VSEN

RTN

COMP_NB

FB_NB

VSEN_NB

ISUMP

ISUMN

ISUMP_NB

ISUMN_NB

ISL6277 HRZISL6277 HRZ

VCORE_EN

C352

C144

VCC5 VCC5

R1

0R0805R10R0805

C142

C1u6.3X50402-HF

29

VDD

R93

X_2.2R1206

C549

X_C1000p50X0402

R117X_3.65KR1%0402R117X_3.65KR1%0402

R114 X_10KR0402R114 X_10KR0402

C143

X_C0.22u16X0402-HF

R2

1R0805R21R0805

30

VDDP

PAD GND

49

1 2

12

CP23CP23

R144X_1R1%0402R144X_1R1%0402

+12VIN

R3

0R0805R30R0805

C18 C0.22u16XC18 C0.22u16X

R296

35

xinhai@schmatic update(2011/10/07)

VIN

FCCM_NB

BOOT1

UGATE1

PHASE1

LGATE1

BOOT2

UGATE2

PHASE2

LGATE2

PWM_Y

BOOTX

UGATEX

PHASEX

LGATEX

PWM2_NB

ISNE1 ISNE2 ISEN3

ISNE1_NB ISEN2_NB

NTC

NTC_NB

IMON

IMON_NB

C1000p50X0402

C1u6.3X50402-HF

CHOKE17

X_CH-0.3u50A0.6m-HF

12

CP25CP25

PWM4

X_0R0402

41

R152

24

0R0805

25

26

27

R148

34

0R0805

33

32

31

PWMY

28

R142

36

0R0805

UG1_NB

37

PH1_NB

38

LG1_NB

39

PWM2_NB

40

ISEN1

15

ISEN2

14

ISEN3

13

NB_ISEN1

48

NB_ISEN2

1

12 2

11 3

R62

130KR1%0402-RH

C46

C50

C1000p50X0402

130KR1%0402-RH

C161

R121 X_10KR0402/NCR121 X_10KR0402/NC

R109 X_10KR0402/NCR109 X_10KR0402/NC

R414 X_10KR0402/NCR414 X_10KR0402/NC

C22

C0.22u16X

UG1

C24

C0.22u16X

UG2

PH2

LG2

C29

C0.22u16X

VCC5

R187

X_0R0402

R188

X_0R0402

R197 X_0R0402R197 X_0R0402

R309

X_0R0402

R297

X_0R0402

X_27.4KR1%0402-RH

R66

R67

BOOT3 PH3

VCC5

R141

R141 0R0805

0R0805

R140 0R0805R140 0R0805

VCCP

ISEN1

ISEN2

ISEN3

R184 0R0805R184 0R0805

R7

X_41.2KR1%R7X_41.2KR1%

PH1

LG1

R166 0R0805R166 0R0805

R50

10KR0402

R163 0R0805R163 0R0805

ISEN4

R326

0R0402

R58

18.2KR1%0402-RH

RT4

100KRT1%0402

RT4

100KRT1%0402

ERT-J0EV474J

CLOSE Q1 or Q13

R126

BOOT3

PWMY

VCC5

R138

R138 0R0805

0R0805

C148

C1u6.3X50402-HF

3

R167

R320

0R0805

3

10KR0402

X_0R0402

2 7 6 3 4

R137 0R0805R137 0R0805

VIN

EC78

X_C10u16X50805-HF

C1u16X5-RHC1C1u16X5-RH

R510KR0402 R510KR0402

DS

1

4

G

2 3

Q82

N-P0903BD

4 3 2 1

N-P0403BK_GEM-PAK8-RH

VIN

DS

1

4

G

2 3

Q84

N-P0903BD

4 3 2 1

N-P0403BK_GEM-PAK8-RH

VIN

DS

1

4

G

2 3

Q86

N-P0903BD

VCC5

N-P0403BK_GEM-PAK8-RH

C750

C0.22u16X

ISL6208BCRZ_QFN8-HF

U4

BOOT

UGATE

FCCM

PHASE VCC PWM

LGATE

GND

GND_P

9

BOOT2_NB PH2_NB

R139

BOOT2_NB

PWM2_NB

C35

C1

4 G

5

Q42

N-P0403BK_GEM-PAK8-RH

4 G

5

Q45

N-P0403BK_GEM-PAK8-RH

4 G

5

Q78

4 3 2 1

R57

18.2KR1%0402-RH

R68

X_27.4KR1%0402-RH

R68

X_27.4KR1%0402-RH

100KRT1%0402

ERT-J0EV474J

CLOSE Q7 or Q8

R133 0R0805R133 0R0805

1 8

LG3

5

C153

0R0805

ISL6208BCRZ_QFN8-HF

U3

2

BOOT

7

FCCM

6

VCC

3

PWM

4

GND

+

12

CD100u16SO-RH-1

DS

1 2 3

Q81

N-P0903BD

4 3 2 1

DS

1 2 3

Q85

N-P0903BD

4 3 2 1

DS

1 2 3

Q87

N-P0903BD

4 3 2 1

N-P0403BK_GEM-PAK8-RH

RT3

R69

10KR0402

UG3

PH3

N-P0403BK_GEM-PAK8-RH

C0.22u16X

1

UGATE

8

PHASE

5

LGATE

GND_P

9

2

+

12

+

12

EC84

EC88

CD820u2.5SO-RH-3

C470u2.5SO-HF

R162

5

Q41

2.2R1206

C33

C1000p50N

VSUM+ ISEN1

C232

C0.22u16X0402-HF

VSUM-

EC22

+

12

C32

C31

CD100u16SO-RH-1

X_C10u16X50805-HF

R156

2.2R1206

C246

C1000p50N

VSUM+ ISEN3 ISEN2

C28

C0.22u16X0402-HF

VSUM-

EC77

+

12

CD100u16SO-RH-1

R151

2.2R1206

C37

C1000p50N

NB_VSUM+

NB_ISEN1

NB_VSUM-

R419

EC89

X_C470u2.5SO-HF

VIN

C1u16X5-RH

C48

DS

1

4

R136 0R0805R136 0R0805

2 3

Q20

N-P0903BD

5

Q31

4 3 2 1

N-P0403BK_GEM-PAK8-RH

R71

10KR0402

N-P0403BK_GEM-PAK8-RH

DS 4 G

Q21

N-P0903BD

5

Q26

4 G

4 3 2 1

5

Q44

C1u16X5-RH

5

X_10KR0402/NC

4 3 2 1

UG2_NB PH2_NB

LG2_NB

C1u16X5-RH

C62

Q75

G

+

12

R10 3.65KR1%0402R10 3.65KR1%0402

R12 10KR0402R12 10KR0402

R13 1R1%0402R13 1R1%0402

R28 3.65KR1%0402R28 3.65KR1%0402

R31 10KR0402R31 10KR0402

R49 1R1%0402R49 1R1%0402

C57

C0.22u16X0402-HF

+

12

C47

1

X_C10u16X50805-HF

2 3

VSUM+ ISEN3

VSUM-

VIN

DS

1 2 3

Q22

N-P0903BD

5

Q37

N-P0403BK_GEM-PAK8-RH

2

+

12

EC85

CD820u2.5SO-RH-3

CP9CP912CP10CP10

CP11CP11

R54 3.65KR1%0402R54 3.65KR1%0402

R55 10KR0402R55 10KR0402

R72 1R1%0402R72 1R1%0402

+

12

CP17CP17

R89

2.2R1206

C56

C1000p50X0402

R81 3.65KR1%0402R81 3.65KR1%0402

R82 10KR0402R82 10KR0402

C59

C0.22u16X0402-HF

R1271R1%0402R1271R1%0402

C1u16X5-RH

C53

DS 4 G

5

4 3 2 1

12

CP14CP14

EC74

X_C470u2.5SO-HF

Q38

N-P0903BD

Q32

+

12

EC86

CD820u2.5SO-RH-3

CHOKE14

CH-0.3u50A0.6m-HF

1 2

CHOKE15

CH-0.3u50A0.6m-HF

1 2

CP12CP12

CHOKE16

CH-0.3u50A0.6m-HF

1 2

12

+

12

CHOKE12

CH-0.3u50A0.6m-HF

1 2

12

CP18CP18

EC25

+

12

C52

CD100u16SO-RH-1

1 2

X_C10u16X50805-HF

3

R131 3.65KR1%0402R131 3.65KR1%0402

NB_VSUM+ NB_ISEN2

R84 10KR0402R84 10KR0402

NB_VSUM-

12

EC87

CD820u2.5SO-RH-3

12

R11 X_10KR0402/NCR11 X_10KR0402/NC

R6 X_10KR0402/NCR6 X_10KR0402/NC

R59 X_10KR0402/NCR59 X_10KR0402/NC

12

R32 X_10KR0402/NCR32 X_10KR0402/NC

R33 X_10KR0402/NCR33 X_10KR0402/NC

R44 X_10KR0402/NCR44 X_10KR0402/NC

12

CP13CP13

EC73

X_C470u2.5SO-HF

12

CP19CP19

R78

2.2R1206

C61

C1000p50X0402

C60

C0.22u16X0402-HF

R1291R1%0402R1291R1%0402

+

EC79

CD820u2.5SO-RH-3

R51 X_10KR0402/NCR51 X_10KR0402/NC

+

12

R77 X_10KR0402/NCR77 X_10KR0402/NC

R80 X_10KR0402/NCR80 X_10KR0402/NC

R372 X_10KR0402/NCR372 X_10KR0402/NC

12

+

12

EC80

CD820u2.5SO-RH-3

VCCP

EC26

CD820u2.5SO-RH-3

ISEN2

ISEN4

CHOKE13

CH-0.3u50A0.6m-HF

1 2

CP20CP20

ISEN2

ISEN3

ISEN4

ISEN1

ISEN4

VCCP

ISEN1

12

+

12

EC81

EC82

CD820u2.5SO-RH-3

C22u6.3X5-HF

C225

C74

VCCP

CPU_VDDNB

NB_ISEN2

+

12

+

12

EC60

EC27

CD820u2.5SO-RH-3

CPU_VDDNB

R134 X_10KR0402/NCR134 X_10KR0402/NC

NB_ISEN1

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Date: Sheet

MICRO-START INT'L CO.,LTD.

FM1 PCIE I/F

Custom

K415-Virgo 0B

1

VCCP

C22u6.3X5-HF

C231

R61

X_10KR0402/NC

1

VCCP

C85

+

12

EC64

CD820u2.5SO-RH-3

C22u6.3X5-HF

CPU_VDDNB

C22u6.3X5-HF

C106

C105

of

736Thursday, November 24, 2011

5

4

3

2

1

FM1 PCIE I/F

mach@CRB PCIE AC Capacitors:75nF to 200nF

D D

CPU1A

GFX_RX0P31 GFX_RX0N31 GFX_RX1P31 GFX_RX1N31 GFX_RX2P31 GFX_RX2N31 GFX_RX3P31 GFX_RX3N31 GFX_RX4P31 GFX_RX4N31 GFX_RX5P31 GFX_RX5N31 GFX_RX6P31 GFX_RX6N31 GFX_RX7P31 GFX_RX7N31 GFX_RX8P31 GFX_RX8N31

C C

B B

CPU_VDDP

GFX_RX9P31 GFX_RX9N31 GFX_RX10P31 GFX_RX10N31 GFX_RX11P31 GFX_RX11N31 GFX_RX12P31 GFX_RX12N31 GFX_RX13P31 GFX_RX13N31 GFX_RX14P31 GFX_RX14N31 GFX_RX15P31 GFX_RX15N31

LAN_RXC_P24 LAN_RXC_N24

UMI_RX0P16 UMI_RX0N16 UMI_RX1P16 UMI_RX1N16 UMI_RX2P16 UMI_RX2N16 UMI_RX3P16 UMI_RX3N16

R252 196R1%R252 196R1% R253 196R1%R253 196R1%

LAN_RXC_P LAN_RXC_N

APU_P_ZVDDP

Layout: Place within 1.5'' of APU

AD8

P_GFX_RXP0

AD9

P_GFX_RXN0

AC7

P_GFX_RXP1

AC8

P_GFX_RXN1

AB5

P_GFX_RXP2

AB6

P_GFX_RXN2

AB8

P_GFX_RXP3

AB9

P_GFX_RXN3

AA7

P_GFX_RXP4

AA8

P_GFX_RXN4

Y5

P_GFX_RXP5

Y6

P_GFX_RXN5

Y8

P_GFX_RXP6

Y9

P_GFX_RXN6

W7

P_GFX_RXP7

W8

P_GFX_RXN7

V5

P_GFX_RXP8

V6

P_GFX_RXN8

V8

P_GFX_RXP9

V9

P_GFX_RXN9

U7

P_GFX_RXP10

U8

P_GFX_RXN10

T5

P_GFX_RXP11

T6

P_GFX_RXN11

T8

P_GFX_RXP12

T9

P_GFX_RXN12

R7

P_GFX_RXP13

R8

P_GFX_RXN13

P5

P_GFX_RXP14

P6

P_GFX_RXN14

P8

P_GFX_RXP15

P9

P_GFX_RXN15

AF5

P_GPP_RXP0

AF6

P_GPP_RXN0

AF8

P_GPP_RXP1

AF9

P_GPP_RXN1

AE7

P_GPP_RXP2

AE8

P_GPP_RXN2

AD5

P_GPP_RXP3

AD6

P_GPP_RXN3

AJ8

P_UMI_RXP0

AJ7

P_UMI_RXN0

AH6

P_UMI_RXP1

AH5

P_UMI_RXN1

AH9

P_UMI_RXP2

AH8

P_UMI_RXN2

AG8

P_UMI_RXP3

AG7

P_UMI_RXN3

AJ2

P_ZVDDP

PZ90421-2M66-01H

PCI EXPRESS

UMI GPP GRAPHICS

P_GFX_TXP0 P_GFX_TXN0 P_GFX_TXP1 P_GFX_TXN1 P_GFX_TXP2 P_GFX_TXN2 P_GFX_TXP3 P_GFX_TXN3 P_GFX_TXP4 P_GFX_TXN4 P_GFX_TXP5 P_GFX_TXN5 P_GFX_TXP6 P_GFX_TXN6 P_GFX_TXP7 P_GFX_TXN7 P_GFX_TXP8 P_GFX_TXN8 P_GFX_TXP9

P_GFX_TXN9 P_GFX_TXP10 P_GFX_TXN10 P_GFX_TXP11 P_GFX_TXN11 P_GFX_TXP12 P_GFX_TXN12 P_GFX_TXP13 P_GFX_TXN13 P_GFX_TXP14 P_GFX_TXN14 P_GFX_TXP15 P_GFX_TXN15

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_UMI_TXP0 P_UMI_TXN0 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3

P_ZVSS

AC2 AC1 AC4 AC5 AB2 AB3 AA2 AA1 AA4 AA5 Y2 Y3 W2 W1 W4 W5 V2 V3 U2 U1 U4 U5 T2 T3 R2 R1 R4 R5 P2 P3 N2 N1

AF2 AF3 AE2 AE1 AE4 AE5 AD2 AD3

UMI_TX0P_APU

AJ5

UMI_TX0N_APU

AJ4

UMI_TX1P_APU

AH3

UMI_TX1N_APU

AH2

UMI_TX2P_APU

AG1

UMI_TX2N_APU

AG2

UMI_TX3P_APU

AG5

UMI_TX3N_APU

AG4

APU_P_ZVSS

AJ1

Layout: PLACE CAPS WITH APU < 1 INCH ROUTE ALL PCIE AS 85OHM +/-10%

GFX_TXP0 GFX_TXN0 GFX_TXP1 GFX_TXN1 GFX_TXP2 GFX_TXN2 GFX_TXP3 GFX_TXN3 GFX_TXP4 GFX_TXN4 GFX_TXP5 GFX_TXN5 GFX_TXP6 GFX_TXN6 GFX_TXP7 GFX_TXN7 GFX_TXP8 GFX_TXN8 GFX_TXP9 GFX_TXN9 GFX_TXP10 GFX_TXN10 GFX_TXP11 GFX_TXN11 GFX_TXP12 GFX_TXN12 GFX_TXP13 GFX_TXN13 GFX_TXP14 GFX_TXN14 GFX_TXP15 GFX_TXN15

LAN_TXP LAN_TXN

C423 C0.1u10X0402C423 C0.1u10X0402 C422 C0.1u10X0402C422 C0.1u10X0402 C420 C0.1u10X0402C420 C0.1u10X0402 C421 C0.1u10X0402C421 C0.1u10X0402 C418 C0.1u10X0402C418 C0.1u10X0402 C419 C0.1u10X0402C419 C0.1u10X0402 C417 C0.1u10X0402C417 C0.1u10X0402 C416 C0.1u10X0402C416 C0.1u10X0402 C414 C0.1u10X0402C414 C0.1u10X0402 C415 C0.1u10X0402C415 C0.1u10X0402 C412 C0.1u10X0402C412 C0.1u10X0402 C413 C0.1u10X0402C413 C0.1u10X0402 C411 C0.1u10X0402C411 C0.1u10X0402 C410 C0.1u10X0402C410 C0.1u10X0402 C409 C0.1u10X0402C409 C0.1u10X0402 C408 C0.1u10X0402C408 C0.1u10X0402 C406 C0.1u10X0402C406 C0.1u10X0402 C407 C0.1u10X0402C407 C0.1u10X0402 C405 C0.1u10X0402C405 C0.1u10X0402 C404 C0.1u10X0402C404 C0.1u10X0402 C402 C0.1u10X0402C402 C0.1u10X0402 C403 C0.1u10X0402C403 C0.1u10X0402 C400 C0.1u10X0402C400 C0.1u10X0402 C401 C0.1u10X0402C401 C0.1u10X0402 C399 C0.1u10X0402C399 C0.1u10X0402 C398 C0.1u10X0402C398 C0.1u10X0402 C396 C0.1u10X0402C396 C0.1u10X0402 C397 C0.1u10X0402C397 C0.1u10X0402 C394 C0.1u10X0402C394 C0.1u10X0402 C395 C0.1u10X0402C395 C0.1u10X0402 C393 C0.1u10X0402C393 C0.1u10X0402 C392 C0.1u10X0402C392 C0.1u10X0402

C799 C0.1u10X0402C799 C0.1u10X0402 C800 C0.1u10X0402C800 C0.1u10X0402

C318 C0.1u10X0402C318 C0.1u10X0402 C319 C0.1u10X0402C319 C0.1u10X0402 C304 C0.1u10X0402C304 C0.1u10X0402 C305 C0.1u10X0402C305 C0.1u10X0402 C302 C0.1u10X0402C302 C0.1u10X0402 C303 C0.1u10X0402C303 C0.1u10X0402 C316 C0.1u10X0402C316 C0.1u10X0402 C317 C0.1u10X0402C317 C0.1u10X0402

Layout: Place within 1.5'' of APU

GFX_TXC_0P 31 GFX_TXC_0N 31 GFX_TXC_1P 31 GFX_TXC_1N 31 GFX_TXC_2P 31 GFX_TXC_2N 31 GFX_TXC_3P 31 GFX_TXC_3N 31 GFX_TXC_4P 31 GFX_TXC_4N 31 GFX_TXC_5P 31 GFX_TXC_5N 31 GFX_TXC_6P 31 GFX_TXC_6N 31 GFX_TXC_7P 31 GFX_TXC_7N 31 GFX_TXC_8P 31 GFX_TXC_8N 31 GFX_TXC_9P 31 GFX_TXC_9N 31 GFX_TXC_10P 31 GFX_TXC_10N 31 GFX_TXC_11P 31 GFX_TXC_11N 31 GFX_TXC_12P 31 GFX_TXC_12N 31 GFX_TXC_13P 31 GFX_TXC_13N 31 GFX_TXC_14P 31 GFX_TXC_14N 31 GFX_TXC_15P 31 GFX_TXC_15N 31

LAN_TXC_P 24 LAN_TXC_N 24

UMI_TX0P 16 UMI_TX0N 16 UMI_TX1P 16 UMI_TX1N 16 UMI_TX2P 16 UMI_TX2N 16 UMI_TX3P 16 UMI_TX3N 16

A A

MICRO-START INT'L CO.,LTD.

Title

FM1 PCIE I/F

Size Document Number Rev

B

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

1

of

836Tuesday, November 22, 2011

5

4

3

2

1

FM1DDR3 I/F

MEM_MA_DQS_L[7..0]12 MEM_MA_DQS_H[7..0]12

MEM_MA_DM[7..0]12

D D

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13

MEM_MA_ADD[15..0]12

MEM_MA_BANK012 MEM_MA_BANK112 MEM_MA_BANK212

C C

mach@CLOCK assignment can be changed

MEM_MA_CLK_H012 MEM_MA_CLK_L012 MEM_MA_CLK_H112 MEM_MA_CLK_L112 MEM_MA_CLK_H212 MEM_MA_CLK_L212 MEM_MA_CLK_H312 MEM_MA_CLK_L312

MEM_MA_CKE012 MEM_MA_CKE112

MEM_MA0_ODT012 MEM_MA0_ODT112 MEM_MA1_ODT012 MEM_MA1_ODT112

MEM_MA0_CS_L012 MEM_MA0_CS_L112 MEM_MA1_CS_L012

B B

MEM_MA1_CS_L112 MEM_MA_RAS_L12

MEM_MA_CAS_L12 MEM_MA_WE_L12

MEM_MA_RESET#12 MEM_MA_HOT#12

APU_M_VREF

VCC_DDR

MEM_MA_ADD14 MEM_MA_ADD15

MEM_MA_BANK0 MEM_MA_BANK1 MEM_MA_BANK2

MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7

MEM_MA_DQS_H0 MEM_MA_DQS_L0 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H7 MEM_MA_DQS_L7

MEM_MA_CLK_H0 MEM_MA_CLK_L0 MEM_MA_CLK_H1 MEM_MA_CLK_L1 MEM_MA_CLK_H2 MEM_MA_CLK_L2 MEM_MA_CLK_H3 MEM_MA_CLK_L3

MEM_MA_CKE0 MEM_MA_CKE1

MEM_MA0_ODT0 MEM_MA0_ODT1 MEM_MA1_ODT0 MEM_MA1_ODT1

MEM_MA0_CS_L0 MEM_MA0_CS_L1 MEM_MA1_CS_L0 MEM_MA1_CS_L1

MEM_MA_RAS_L MEM_MA_CAS_L MEM_MA_WE_L

MEM_MA_RESET# MEM_MA_HOT#

R254 39.2R1%0402R254 39.2R1%0402

Layout: Place within 1.5'' of APU

APU_M_ZVDDIO

CPU1B

V27 P27 R25 P26 R24 P24 P23 N26 N23

M25

V24 N25

M24

Y23 L27 L24

W26

V25 L26

E17 H21 F25

G29 AF29 AE25

AG21

AF17

H17

G17

F21

E21

G26

G25

F30

E30 AE28 AE29

AG24 AG25

AF20 AF21 AE16 AD16

U27

U26

T23

U23

T25

T26

R27

R28

L23

K26 AA24

AC27 AA25 AC26

Y27 AB26

W23

AB25

W25

Y24

Y26

J25

U24

K22

J24

PZ90421-2M66-01H

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MA_BANK0 MA_BANK1 MA_BANK2

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7

MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 MA_CLK_H2 MA_CLK_L2 MA_CLK_H3 MA_CLK_L3

MA_CKE0 MA_CKE1

MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1

MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1

MA_RAS_L MA_CAS_L MA_WE_L

MA_RESET_L MA_EVENT_L

M_VREF M_ZVDDIO

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7

MA_DATA8

MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15

MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23

MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31

MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39

MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47

MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55

MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

MEM_MA_DATA0

F16

MEM_MA_DATA1

G16

MEM_MA_DATA2

H18

MEM_MA_DATA3

F19

MEM_MA_DATA4

F15

MEM_MA_DATA5

H15

MEM_MA_DATA6

E18

MEM_MA_DATA7

F18

MEM_MA_DATA8

G20

MEM_MA_DATA9

H20

MEM_MA_DATA10

E23

MEM_MA_DATA11

G23

MEM_MA_DATA12

G19

MEM_MA_DATA13

E20

MEM_MA_DATA14

F22

MEM_MA_DATA15

G22

MEM_MA_DATA16

F24

MEM_MA_DATA17

H24

MEM_MA_DATA18

E27

MEM_MA_DATA19

F27

MEM_MA_DATA20

H23

MEM_MA_DATA21

E24

MEM_MA_DATA22

E26

MEM_MA_DATA23

H26

MEM_MA_DATA24

G28

MEM_MA_DATA25

E29

MEM_MA_DATA26

H29

MEM_MA_DATA27

H30

MEM_MA_DATA28

H27

MEM_MA_DATA29

F28

MEM_MA_DATA30

F31

MEM_MA_DATA31

G31

MEM_MA_DATA32

AD30

MEM_MA_DATA33

AF30

MEM_MA_DATA34

AG27

MEM_MA_DATA35

AF27

MEM_MA_DATA36

AD31

MEM_MA_DATA37

AE31

MEM_MA_DATA38

AG28

MEM_MA_DATA39

AD28

MEM_MA_DATA40

AF26

MEM_MA_DATA41

AD25

MEM_MA_DATA42

AF23

MEM_MA_DATA43

AE23

MEM_MA_DATA44

AD27

MEM_MA_DATA45

AE26

MEM_MA_DATA46

AF24

MEM_MA_DATA47

AD24

MEM_MA_DATA48

AG22

MEM_MA_DATA49

AD21

MEM_MA_DATA50

AE19

MEM_MA_DATA51

AG19

MEM_MA_DATA52

AD22

MEM_MA_DATA53

AE22

MEM_MA_DATA54

AE20

MEM_MA_DATA55

AD19

MEM_MA_DATA56

AG18

MEM_MA_DATA57

AE17

MEM_MA_DATA58

AF15

MEM_MA_DATA59

AG15

MEM_MA_DATA60

AD18

MEM_MA_DATA61

AF18

MEM_MA_DATA62

AG16

MEM_MA_DATA63

AD15

MEM_MA_DATA[63..0] 12

MEM_MB_ADD[15..0]13

MEM_MB_BANK013 MEM_MB_BANK113 MEM_MB_BANK213

MEM_MB_CLK_H013 MEM_MB_CLK_L013 MEM_MB_CLK_H113 MEM_MB_CLK_L113 MEM_MB_CLK_H213 MEM_MB_CLK_L213 MEM_MB_CLK_H313 MEM_MB_CLK_L313

MEM_MB_CKE013 MEM_MB_CKE113

MEM_MB0_ODT013 MEM_MB0_ODT113 MEM_MB1_ODT013 MEM_MB1_ODT113

MEM_MB0_CS_L013 MEM_MB0_CS_L113 MEM_MB1_CS_L013 MEM_MB1_CS_L113

MEM_MB_RAS_L13 MEM_MB_CAS_L13 MEM_MB_WE_L13

MEM_MB_RESET#13 MEM_MB_HOT#13

MEM_MB_BANK0 MEM_MB_BANK1 MEM_MB_BANK2

MEM_MB_DQS_H0 MEM_MB_DQS_L0 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H7 MEM_MB_DQS_L7

MEM_MB_CLK_H0 MEM_MB_CLK_L0 MEM_MB_CLK_H1 MEM_MB_CLK_L1 MEM_MB_CLK_H2 MEM_MB_CLK_L2 MEM_MB_CLK_H3 MEM_MB_CLK_L3

MEM_MB_CKE0 MEM_MB_CKE1

MEM_MB0_ODT0 MEM_MB0_ODT1 MEM_MB1_ODT0 MEM_MB1_ODT1

MEM_MB0_CS_L0 MEM_MB0_CS_L1 MEM_MB1_CS_L0 MEM_MB1_CS_L1

MEM_MB_RAS_L MEM_MB_CAS_L MEM_MB_WE_L

MEM_MB_RESET# MEM_MB_HOT#

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7

MEM_MB_DQS_L[7..0]13 MEM_MB_DQS_H[7..0]13

MEM_MB_DM[7..0]13

CPU1C

V31

N28

P29 N29 N31 M30 M31 M28 M27

L30 W31

L29

K28

AB28

K31

J31 W29

V30

K29 D16

B20

A25 D29

AL29 AH25 AK21 AJ17

A17

B17

B21 C21 D25 C25

B29

A29

AJ29 AH29 AK25 AL25 AJ20 AJ21 AL16 AL17

U30 U29

T29

T28 R31

T31

P30 R30

J30

J28

AA30 AC30 AA31 AC29

Y29

AB29

Y30

AB31

W28

AA27 AA28

J27

V28

PZ90421-2M66-01H

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7

MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 MB_CLK_H2 MB_CLK_L2 MB_CLK_H3 MB_CLK_L3

MB_CKE0 MB_CKE1

MB0_ODT0 MB0_ODT1 MB1_ODT0 MB1_ODT1

MB0_CS_L0 MB0_CS_L1 MB1_CS_L0 MB1_CS_L1

MB_RAS_L MB_CAS_L MB_WE_L

MB_RESET_L MB_EVENT_L

MEMORY CHANNEL B

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7

MB_DATA8

MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15

MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23

MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31

MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39

MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47

MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55

MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

MEM_MB_DATA0

A16

MEM_MB_DATA1

C16

MEM_MB_DATA2

B18

MEM_MB_DATA3

A19

MEM_MB_DATA4

C15

MEM_MB_DATA5

B15

MEM_MB_DATA6

D17

MEM_MB_DATA7

C18

MEM_MB_DATA8

D20

MEM_MB_DATA9

A20

MEM_MB_DATA10

D22

MEM_MB_DATA11

D23

MEM_MB_DATA12

C19

MEM_MB_DATA13

D19

MEM_MB_DATA14

A22

MEM_MB_DATA15

C22

MEM_MB_DATA16

C24

MEM_MB_DATA17

B24

MEM_MB_DATA18

B26

MEM_MB_DATA19

C27

MEM_MB_DATA20

A23

MEM_MB_DATA21

B23

MEM_MB_DATA22

D26

MEM_MB_DATA23

A26

MEM_MB_DATA24

C28

MEM_MB_DATA25

D28

MEM_MB_DATA26

C31

MEM_MB_DATA27

D31

MEM_MB_DATA28

B27

MEM_MB_DATA29

A28

MEM_MB_DATA30

B30

MEM_MB_DATA31

C30

MEM_MB_DATA32

AJ30

MEM_MB_DATA33

AK30

MEM_MB_DATA34

AH28

MEM_MB_DATA35

AJ27

MEM_MB_DATA36

AG30

MEM_MB_DATA37

AH31

MEM_MB_DATA38

AK28

MEM_MB_DATA39

AL28

MEM_MB_DATA40

AJ26

MEM_MB_DATA41

AH26

MEM_MB_DATA42

AH23

MEM_MB_DATA43

AJ23

MEM_MB_DATA44

AK27

MEM_MB_DATA45

AL26

MEM_MB_DATA46

AJ24

MEM_MB_DATA47

AK24

MEM_MB_DATA48

AK22

MEM_MB_DATA49

AH22

MEM_MB_DATA50

AL19

MEM_MB_DATA51

AK19

MEM_MB_DATA52

AL23

MEM_MB_DATA53

AL22

MEM_MB_DATA54

AH20

MEM_MB_DATA55

AL20

MEM_MB_DATA56

AJ18

MEM_MB_DATA57

AH17

MEM_MB_DATA58

AJ15

MEM_MB_DATA59

AK15

MEM_MB_DATA60

AH19

MEM_MB_DATA61

AK18

MEM_MB_DATA62

AK16

MEM_MB_DATA63

AH16

MEM_MB_DATA[63..0] 13

VCC_DDR

R196

1KR1%

A A

5

R201

1KR1%

C170

C1000P50X0402

APU_M_VREF

C679

C0.1u10X0402

C156

Layout: Place within 1.0'' of APU

C1000P50X0402

4

VCC_DDR

R275 1KR0402R275 1KR0402 R274 1KR0402R274 1KR0402

3

MEM_MA_HOT# MEM_MB_HOT#

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

FM1 DDR3 I/F

K415-Virgo 0B

1

936Tuesday, November 22, 2011

of

5

FM1 DISPLAY I/F

Note: Several vias on the DP0 interface violate the minimum distance rules for via to via spacing between diff pairs. These violations have been reviewed and approved on an individual basis, and pose no significant singal integrity issues for this implementation since the route lengths are under the maximum allowed spec, and the via distance violations are not severe.

DP0_TX0P21

FCH_THERMTRIP# 17

FCH_TALERT# 18

FCH_PROCHOT# 16

DP0_TX0N21 DP0_TX1P21

DP0_TX1N21 DP0_TX2P21

DP0_TX2N21 DP0_TX3P21

DP0_TX3N21 DP1_TX0P18

DP1_TX0N18 DP1_TX1P18

DP1_TX1N18 DP1_TX2P18

DP1_TX2N18 DP1_TX3P18

DP1_TX3N18

APU_SIC

C337

X_C10p50N0402

D D

APU_RST# APU_PWRGD

APU_THERMTRIP#

C C

APU_ALERT#

APU_PROCHOT#

B B

X_C10p50N0402

mach@DP1 for CRT

Layout: Place within 1.5'' of APU

C335

C299

C180p50N0402

VCC_DDR VCC3_SB

R305

2

10KR0402

61

Q49A

NN-CMKT3904_SOT363-6-RH

VCC3_SBVCC_DDR

R303

5

10KR0402

34

Q49B

NN-CMKT3904_SOT363-6-RH

VCC3_SBVCC_DDR

R446

5

10KR0402

34

Q132B

NN-CMKT3904_SOT363-6-RH

R304

R302

10KR0402

R452

10KR0402

APU_CLK16 APU_CLK#16

DISP_CLK16 DISP_CLK#16

APU_RST#16

APU_PWRGD7,16

APU_SIC25 APU_SID25

C230 C0.1u10X0402C230 C0.1u10X0402 C235 C0.1u10X0402C235 C0.1u10X0402

C226 C0.1u10X0402C226 C0.1u10X0402 C220 C0.1u10X0402C220 C0.1u10X0402

C213 C0.1u10X0402C213 C0.1u10X0402 C209 C0.1u10X0402C209 C0.1u10X0402

C210 C0.1u10X0402C210 C0.1u10X0402 C214 C0.1u10X0402C214 C0.1u10X0402

C255 C0.1u10X0402C255 C0.1u10X0402 C259 C0.1u10X0402C259 C0.1u10X0402

C248 C0.1u10X0402C248 C0.1u10X0402 C252 C0.1u10X0402C252 C0.1u10X0402

C244 C0.1u10X0402C244 C0.1u10X0402 C238 C0.1u10X0402C238 C0.1u10X0402

C240 C0.1u10X0402C240 C0.1u10X0402 C236 C0.1u10X0402C236 C0.1u10X0402

APU_SVC7 APU_SVD7 APU_SVT7

APU_SID

APU_RST# APU_PWRGD

PULL UP

VCC_DDR

VCC5_SB

R307 1KR0402R307 1KR0402 R317 1KR0402R317 1KR0402

R288 300R0402R288 300R0402 R310 300R0402R310 300R0402

R289 1KR0402R289 1KR0402 R287 1KR0402R287 1KR0402 R290 1KR0402R290 1KR0402

R318 1KR0402R318 1KR0402

R301 10KR0402R301 10KR0402

APU_SIC_R APU_SID

APU_RST#

APU_PWRGD

APU_PROCHOT# APU_ALERT# APU_THERMTRIP#

FCH_DMA_ACTIVE#

APU_FM2R1

R316 10R0402R316 10R0402

APU_PROCHOT# APU_THERMTRIP# APU_ALERT#

4

DP0_TX0P_APU DP0_TX0N_APU

DP0_TX1P_APU DP0_TX1N_APU

DP0_TX2P_APU DP0_TX2N_APU

DP0_TX3P_APU DP0_TX3N_APU

DP1_TX0P_APU DP1_TX0N_APU

DP1_TX1P_APU DP1_TX1N_APU

DP1_TX2P_APU DP1_TX2N_APU

DP1_TX3P_APU DP1_TX3N_APU

APU_SVC APU_SVD APU_SVT

APU_SIC_RAPU_SIC

CPU_TDI CPU_TDO CPU_TCK CPU_TMS CPU_TRST_L CPU_DBRDY CPU_DBREQ_L

ROUTE PCIE AS 85OHM +/-10% PLACE CAPS WITH APU < 1 INCH

Trace length within 10"

CPU1D

ANALOG/DISPLAY/MISC

N4

DP0_TXP0

N5

DP0_TXN0

M2

DP0_TXP1

M3

DP0_TXN1

L2

DP0_TXP2

L1

DP0_TXN2

L4

DP0_TXP3

L5

DP0_TXN3

K2

DP1_TXP0

K3

DP1_TXN0

J2

DP1_TXP1

J1

DP1_TXN1

J4

DP1_TXP2

J5

DP1_TXN2

H2

DP1_TXP3

H3

DP1_TXN3

L7

DP2_TXP0

L8

DP2_TXN0

K5

DP2_TXP1

K6

DP2_TXN1

K8

DP2_TXP2

K9

DP2_TXN2

J7

DP2_TXP3

J8

DP2_TXN3

N7

DP2_TXP4

N8

DP2_TXN4

M5

DP2_TXP5

M6

DP2_TXN5

M8

DP2_TXP6

M9

DP2_TXN6

AL12

CLKIN_H

AK12

CLKIN_L

AG12

DISP_CLKIN_H

AF12

DISP_CLKIN_L

C1

SVC

C2

SVD

D1

SVT

AK14

SIC

AL14

SID

AF10

RESET_L

AF14

PWROK

AE10

PROCHOT_L

AH14

THERMTRIP_L

AJ14

ALERT_L

G11

TDI

E10

TDO

E11

TCK

F11

TMS

F10

TRST_L

G10

DBRDY

E9

DBREQ_L

PZ90421-2M66-01H

DISPLAY PORT 0

DISPLAY PORT 2 DISPLAY PORT 1

SER. CLK

MISC

JTAG CTRL

SENSE RSVD

DP_AUX_ZVSS

DP_VARY_BL

DISPLAY PORT MISC.

TEST

DMAACTIVE_L

BP5/IDLEEXIT_L

VDDP_SENSE

VDDNB_SENSE

VDDIO_SENSE

VDDR_SENSE

DP_BLON

DP_DIGON

DP0_AUXP DP0_AUXN

DP1_AUXP DP1_AUXN

DP2_AUXP DP2_AUXN

DP3_AUXP DP3_AUXN

DP4_AUXP DP4_AUXN

DP5_AUXP DP5_AUXN

DP0_HPD DP1_HPD DP2_HPD DP3_HPD DP4_HPD DP5_HPD

TEST4 TEST5 TEST6

TEST9 TEST10 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 TEST24

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST30_H

TEST30_L

TEST31

TEST32_H

TEST32_L

TEST35

FM2R1

LDTSTOP_L

CORETYPE

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8

VDD_SENSE VSS_SENSE

G9 F8

G8 E8

E1 E2

F1 F2

G1 G2

E5 E6

F5 F6

G5 G6

E3 F3 G3 E7 F7 G7

T21 U21 AD14 P21 R21 F12 E12 F13 E13 G13 G14 F14 E14 AJ11 AH11 H10 J10 T22 U22 AG31 V22 R22 AE14

AC10 AG14 AD10 G12 F9

AJ13 AH13 AD12 K23 K25 AB23 AC24 AG10

C3 A3 A4 B3 C4 B4

3

DP_AUX_ZVSS APU_BLON

APU_DIGON APU_BLPWM

DP0

DP1

DP2_HPD DP3_HPD DP4_HPD DP5_HPD

APU_TEST4 APU_TEST5 APU_TEST6 APU_TEST9 APU_TEST10 APU_TEST14 APU_TEST15 APU_TEST16 APU_TEST17 APU_TEST18 APU_TEST19 APU_TEST20 APU_TEST24 APU_TEST25_H APU_TEST25_L APU_TEST28_H APU_TEST28_L APU_TEST30_H APU_TEST30_L APU_TEST31 APU_TEST32_H APU_TEST32L APU_TEST35

APU_FM2R1

FCH_DMA_ACTIVE#

VDDP_SENSE

VDDR_SENSE

R684 0R0402R684 0R0402

R680 0R0402R680 0R0402

Layout: Place within 1.5'' of APU

R207 150R1%0402R207 150R1%0402

DP0_AUXP_C 21 DP0_AUXN_C 21

MACH@??? DP2 to PCIE16X conn?

DP1_AUXP_C 18 DP1_AUXN_C 18

DP0_TX0,TX1,TX2 and TX3 DP0_AUX0 and DP0_HPD

DP1_TX0,TX1,TX2 and TX3 DP1_AUX0 and DP1_HPD

R266 100KR0402R266 100KR0402 R267 100KR0402R267 100KR0402 R262 100KR0402R262 100KR0402 R260 100KR0402R260 100KR0402

TP28TP28 TP45TP45 TP48TP48 TP49TP49 TP33TP33 TP20TP20 TP4TP4 TP21TP21 TP19TP19

R190 1KR0402R190 1KR0402 R189 1KR0402R189 1KR0402 R191 1KR0402R191 1KR0402 R193 1KR0402R193 1KR0402 R280 511R1%0402R280 511R1%0402

R319 511R1%0402R319 511R1%0402 TP26TP26 TP27TP27 TP30TP30 TP40TP40

R308 39.2R1%0402R308 39.2R1%0402

TP44TP44 TP43TP43

R204 X_300R0402R204 X_300R0402

R205 300R0402R205 300R0402

APU_FM2R1 7

FCH_DMA_ACTIVE# 16

LDTSTOP_L

LDTSTOP_L 16

FM_IDLEEXIT_L

LDTSTOP_L

R192 1KR0402R192 1KR0402

TP9TP9

NB_SENSE+ 7 VDDIOFB+ 27 COREFB+ 7

TP10TP10

COREFB- 7

NB_SENSE- 7

Sabine HDMI Design Guidance HDMI enable strapping: TEST35 PU TO VCC_DDR thru 300R

DP0_HPD_HDMI_C 21 DP1_HPD_VGA_C 18

CPU_VDDP

VCC_DDR

H:HDMI ENABLE

VCC_DDR

CPU_TRST_L

FM_IDLEEXIT_L

2

R203

R203 1KR0402

1KR0402

N-SST3904_SOT23

HDT+ Connector

VCC_DDR

J2

1

CPU_VDDIO

3

GND

5

GND

7

R658 X_0R0402R658 X_0R0402 R659 X_10KR0402R659 X_10KR0402 R660 X_10KR0402R660 X_10KR0402 R661 X_10KR0402R661 X_10KR0402

Q83A

X_NN-CMKT3904_SOT363-6-RH

VCC_DDR

B

Q74

GND CPU_TRST_L9CPU_PWROK_BUF CPU_DBRDY311CPU_RST_L_BUF CPU_DBRDY213CPU_DBRDY0 CPU_DBRDY115CPU_DBREQ_L

17

GND CPU_VDDIO19CPU_PLLTEST1

X_H2X10SM-1.27PITCH_BLUE-RH

VCC3 VCC3

R9

2

X_10KR0402

APU_PWROK_BUFAPU_PWRGD APU_LDT_RST_BUF

61

R583

10KR0402

CE

FCH_IDLEEXIT_L 17

SCAN Conn,

APU_TEST18 APU_TEST19

APU_TEST24 APU_TEST20

WARM RESET

APU_RST#

GPU DEBUG

APU_BLON APU_DIGON APU_BLPWM DP1_HPD_VGA_C

TP7TP7 TP32TP32

CPU_TCK

CPU_TMS

CPU_TDI

CPU_TDO

CPU_PLLTEST0

APU_RST#

VCC_DDR

1

CPU_TCK

2

CPU_TMS

4

CPU_TDI

6

CPU_TDO

8

APU_PWROK_BUF

10

APU_LDT_RST_BUF

12

CPU_DBRDY

14

CPU_DBREQ_L

16

APU_TEST19

18

APU_TEST18

20

R42

5

X_10KR0402

R83

R83 X_0R0402

X_0R0402

VDDIOFB+ COREFB+

X_10KR0402

34

Q83B

X_NN-CMKT3904_SOT363-6-RH

Layout: Place close to HDT header

R653 1KR0402R653 1KR0402 R651 1KR0402R651 1KR0402 R652 1KR0402R652 1KR0402 R657 1KR0402R657 1KR0402 R654 1KR0402R654 1KR0402

TP46TP46 TP64TP64

TP69TP69 TP70TP70

TP71TP71

TP76TP76 TP77TP77 TP78TP78 TP79TP79

CPU_TDI CPU_TCK CPU_TMS CPU_TRST_L CPU_DBREQ_L

A A

TEST2, TEST3, TEST6, TEST10, TEST23, TEST28_H TEST28_L, and any RSVD pins have no connections. TEST4, TEST5, TEST[17:14], TEST25_H/L,TEST30_H/L, and TEST32_H/L have onboard test points.

5

4

mach@FM1R1 used to control VRM_EN(D66)??? FM1R1 = OPEN ON PKG. IF LOW, KEEP PWR OFF!

3

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

FM1 DISPLAY/MSIC

K415-Virgo 0B

1

10 36Tuesday, November 29, 2011

of

5

BOTTOM SIDE DECOUPLING

VCCP

C697,C700,C705,C710 change to ASM-5010

D D

C C

CPU_VDDNB

VCC_DDR

B B

CPU_VDDR

C697

C700

VCCP VCCP

C712

VCCP

C715

C796

X_C47u6.3X1206

C695

C22u6.3X1206

Layout: Place close to Pins AH11,AJ11,AK11,AL11

C298

C22u6.3X1206

C22u6.3X0805

C47u4X50805-RH

C0.22U16X3

C790

X_C47u6.3X1206

C690

C22u6.3X1206

C324

C22u6.3X0805

C694

C47u4X50805-RH

C716

C0.22U16X3

C4.7u6.3X5

C705

C22u6.3X0805

C702

C22u6.3X5-HF

C795

X_C47u6.3X1206

C681

C22u6.3X1206

C314

C4.7u6.3X5

C682

C710

C47u6.3X1206

C22u6.3X0805

C709

C689

C789

X_C47u6.3X1206

C685

C22u6.3X1206

C332

C0.22U16X3

C709

C708

C47u4X50805-RH

VCCP VCCP

C711

C0.01u25X0603

C792

C794

X_C47u6.3X1206

C223

C698

C4.7u6.3X5

C10u6.3X50805

C330

C189

C0.22U16X3

C10u6.3X50805

EMC Caps On Bottom side

A A

VCCP

C149

C149 C180p50N0402

C180p50N0402

5

C704

C47u6.3X1206

C714

C0.01u25X0603

C816

C703

C699

C47u6.3X1206

C713

C47u4X50805-RH

C680

C0.01u25X0603

X_C47u6.3X1206

C4.7u6.3X5

C696

C797

C47u6.3X1206

C706

C4.7u6.3X5

C47u6.3X1206

C684

C47u4X50805-RH

C718

C814

C47u6.3X1206

C272

C4.7u6.3X5

C687

C47u6.3X1206

C180p50N0402

C692

C707

C47u4X50805-RH

C719

C180p50N0402

C791

X_C47u6.3X1206

C270

C0.22U16X3

C47u6.3X1206

C701

C47u4X50805-RH

C688

C815

X_C47u6.3X1206

C221

C0.22U16X3

C683

C47u6.3X1206

C180p50N0402

C798

X_C47u6.3X1206

C784

C180p50N0402

4

VCCP VCCP

CPU1E

AA11

VDD_1

AB7

VDD_2

Y20

VDD_3

M10

VDD_4

P10

VDD_5

T20

VDD_6

W11

VDD_7

AA13

VDD_8

AA21

VDD_9

AA3

VDD_10

AA6

VDD_11

AB1

VDD_12

AB10

VDD_13

AB14

VDD_14

AB16

VDD_15

AB18

VDD_16

AB4

VDD_17

AC11

VDD_18

AC13

VDD_19

AC19

VDD_20

AC21

VDD_21

AD1

VDD_22

AE3

VDD_23

AF4

VDD_24

AF7

VDD_25

AG6

VDD_26

AH7

VDD_27

H12

VDD_28

H14

VDD_29

H8

VDD_30

J11

VDD_31

J13

VDD_32

J15

VDD_33

J17

VDD_34

J19

VDD_35

J21

VDD_36

J9

VDD_37

K10

VDD_38

K12

VDD_39

K14

VDD_40

U13

VDD_41

K16

VDD_42

AC17

VDD_43

Y18

VDD_44

K18

VDD_45

K20

VDD_46

K4

VDD_47

L3

VDD_48

L11

VDD_49

L15

VDD_50

PZ90421-2M66-01H

CPU1F

K27

VDDIO_1

J29

VDDIO_2

U25

VDDIO_3

T30

VDDIO_4

V29

VDDIO_5

L28

VDDIO_6

L31

VDDIO_7

M22

VDDIO_8

M23

VDDIO_9

M26

VDDIO_10

N24

VDDIO_11

N27

VDDIO_12

N30

VDDIO_13

P22

VDDIO_14

U31

VDDIO_15

W24

VDDIO_16

V23

VDDIO_17

V26

VDDIO_18

U28

VDDIO_19

P25

VDDIO_20

P28

AB22 AB24 AB27 AB30 AC23 AC25 AC28 AC31

AA26

AA23

AA29 MEC1 MEC2 MEC3 MEC4

P31 R23 R26 R29 T24

W27

L25

W30

Y22 Y25 Y28 K24

K30 Y31

J26 M29 T27

VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29 VDDIO_30 VDDIO_31 VDDIO_32 VDDIO_33 VDDIO_34 VDDIO_35 VDDIO_36 VDDIO_37 VDDIO_38 VDDIO_39 VDDIO_40 VDDIO_41 VDDIO_42 VDDIO_43 VDDIO_44 VDDIO_45 VDDIO_46 VDDIO_47 VDDIO_48 VDDIO_49 MEC1 MEC2 MEC3 MEC4

PZ90421-2M66-01H

C785

C180p50N0402

4

VDD

VDDNB_CAP_1 VDDNB_CAP_2

VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72 VDD_73 VDD_74 VDD_75 VDD_76 VDD_77 VDD_78 VDD_79 VDD_80 VDD_81 VDD_82 VDD_83 VDD_84 VDD_85 VDD_86 VDD_87 VDD_88 VDD_89 VDD_90 VDD_91 VDD_92 VDD_93 VDD_94 VDD_95 VDD_96 VDD_97 VDD_98 VDD_99

VDDA_1 VDDA_2

VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 VDDNB_6 VDDNB_7 VDDNB_8

VDDNB_9 VDDNB_10 VDDNB_11 VDDNB_12 VDDNB_13 VDDNB_14 VDDNB_15 VDDNB_16 VDDNB_17 VDDNB_18 VDDNB_19 VDDNB_20 VDDNB_21 VDDNB_22 VDDNB_23 VDDNB_24 VDDNB_25 VDDNB_26 VDDNB_27 VDDNB_28 VDDNB_29 VDDNB_30

VDDR_1 VDDR_2 VDDR_3 VDDR_4 VDDR_5 VDDR_6

VDDP_1 VDDP_2 VDDP_3 VDDP_4 VDDP_5 VDDP_6 VDDP_7 VDDP_8 VDDP_9

L17 L21 M12 M16 M18 M20 N6 N11 N19 N3 P1 P12 P20 T1 P4 P7 R11 R13 R19 T10 T12 U11 V20 U3 U6 V1 V10 V12 V4 V7 W13 W19 J6 N21 U19 AE6 AC15 W21 Y1 Y10 Y12 Y14 AA15 AA17 AA19 Y16 AH1 AF1 K7

AE13 AD13

A7 A6 A5 A9 C6 A10 A11 A12 A13 A14 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C5 C14 C13 C12 C11 C10 C9 C8 C7 A8 M14 N13

AL10 AK8 AK9 AL8 AL9 AK10

AK4 AK5 AL5 AL3 AL4 AL6 AK3 AK6 AK2

CPU_VDDNB

C180p50N0402

C181

3

TOTLE POWER PINS

430 2

VALUE/SIZE/ MATERIAL

22U/1206/X5R 10U/0805/X5R

4.7U/0805/X5R

0.22U/0603/X5R

0.1U/0603/X5R

0.01U/0603/X5R

3.3 nF/0603/X5R 1 nF/0603/X5R 1 nF/0603/X5R 180 pF/0603/X5R

VDDA25VCC_DDR

TP18TP18

CPU_VDDNB

VDDNB = 0.8V (Variable)

Layout: Place close to Pins M14,M13 inside the backplate cavity openning

VDDNB_CAP

C686 C22u6.3X1206C686 C22u6.3X1206 C691 C22u6.3X1206C691 C22u6.3X1206

CPU_VDDR

CPU_VDDP

C180p50N0402

Layout: Place caps within 0.6'' of APU

VDDR = 1.2V VDDPCIE = 1.2V ONLY ONE SIDE OF VDDPCIE & VDDR MUST CONNECTED ON THE PCB.CONNECTING BOTH SIDES IS ACCEPTABLE BUT NOT REQUIRED. BOTH SIDES MUST BE DECOUPLED.

CPU_VDDP CPU_VDDR

C204

3

CPU_VDDP CPU_VDDR

C203

C180p50N0402

FM2DECOUPLING CAPS

VSS

VDD

VDDNB

VDDNBCAP

99

232

/ / / / / / / / / /

Place across each VDDIO-GND plane seam

VCC_DDR

C281

30

/

2 2

7

1

3 2

2

/

/ /

4 /

/

31

C357

C758

C0.22U16X3

C306

C312

C4.7u6.3X5

Layout: Place close to Pins H1,H2,H3,H4

C308

C180p50N0402

2+2

C371

C0.22U16X3

VDDIO

COMB

SPLIT

49

2

4

/ 1 4

/ / / / / 2+2

C180p50N0402

CPU_VDDP

C194

1

2+1(B)

2

2+2

2

2+2 /

/

//

/ //

4

2

2+2

C757

C180p50N0402

VDDA_25VDDA25

FB5

30L3A-40_0805-RH

C717

C3300p50X0402

Layout: Place close to Pins AH10,AJ10,AK10,AL10

C323

C47u4X50805-RH

C310

C10u6.3X50805

C321

C180p50N0402

C323

C296

2

VDDP

9

NEAR

//1

2 2 / / / / / /

CPU_VDDNB

C4.7u6.3X5

2

VDDR

SPLIT

6

FAR

/ / 2 2 / / / / / /

C180

C329

C0.22U16X3

C0.22U6.3X

VDDA

/ / 1 1 / / 1

/ /

C164

C0.22U6.3X

C326

C1000P50X0402

Mvref

1

/ / / / / 1 / 1

/

C169

C180p50N0402

C331

C1000P50X0402

1

CPU1H

AK29

VSS_115

R10

VSS_116

R12

VSS_117

R20

VSS_118

T4

VSS_119

T7

VSS_120

T11

VSS_121

T13

VSS_122

T19

VSS_123

U9

VSS_124

U10

VSS_125

U12

VSS_126

U20

VSS_127

V11

VSS_128

V13

VSS_129

V19

VSS_130

V21

VSS_131

W3

VSS_132

W6

VSS_133

W9

VSS_134

W10

VSS_135

W12

VSS_136

W20

VSS_137

W22

VSS_138

Y4

VSS_139

Y7

VSS_140

Y11

VSS_141

Y13

VSS_142

Y15

VSS_143

Y17

VSS_144

Y19

VSS_145

Y21

VSS_146

AA9

VSS_147

AA10

VSS_148

AA14

VSS_149

AA16

VSS_150

AA18

VSS_151

AA20

VSS_152

AA22

VSS_153

AB13

VSS_154

AB15

VSS_155

AB17

VSS_156

AB19

VSS_157

AB21

VSS_158

AC3

VSS_159

AC6

VSS_160

AC9

VSS_161

AC12

VSS_162

AC14

VSS_163

AC16

VSS_164

AC18

VSS_165

AC22

VSS_166

AD4

VSS_167

AD7

VSS_168

AD11

VSS_169

AK20

VSS_170

AK23

VSS_171

AF19

VSS_172

AK26

VSS_173

PZ90421-2M66-01H

CPU1G

A18

VSS_1

A21

VSS_2

A24

VSS_3

A27

VSS_4

B16

VSS_5

B19

VSS_6

B22

VSS_7

N22

VSS_8

B25

VSS_9

B28

VSS_10

C17

VSS_11

C20

VSS_12

C23

VSS_13

C26

VSS_14

C29

VSS_15

D2

VSS_16

D3

VSS_17

D4

VSS_18

D5

VSS_19

D6

VSS_20

D7

VSS_21

D8

VSS_22

D9

VSS_23

D10

VSS_24

D11

VSS_25

D12

VSS_26

D13

VSS_27

D14

VSS_28

D15

VSS_29

D18

VSS_30

D21

VSS_31

D24

VSS_32

D27

VSS_33

D30

VSS_34

E4

VSS_35

E15

VSS_36

E16

VSS_37

E19

VSS_38

E22

VSS_39

E25

VSS_40

E28

VSS_41

E31

VSS_42

F4

VSS_43

F17

VSS_44

F20

VSS_45

F23

VSS_46

F26

VSS_47

F29

VSS_48

G15

VSS_49

G18

VSS_50

G21

VSS_51

G24

VSS_52

R6

VSS_53

AL21

VSS_54

AL24

VSS_55

AL18

VSS_56

P11

VSS_57

PZ90421-2M66-01H

Title

FM1 POWER&DECOUPLING

Size Document Number Rev

C

K415-Virgo 0B

Date: Sheet

AF16

VSS_174

VSS

AF13

VSS_175

AF11

VSS_176

AF22

VSS_177

AF25

VSS_178

AF28

VSS_179

AF31

VSS_180

AG3

VSS_181

AG9

VSS_182

AG11

VSS_183

AG13

VSS_184

AG17

VSS_185

AG20

VSS_186

AG23

VSS_187

AG26

VSS_188

AG29

VSS_189

AH4

VSS_190

AH10

VSS_191

AH12

VSS_192

AH15

VSS_193

AH18

VSS_194

AH21

VSS_195

AH24

VSS_196

AH27

VSS_197

AH30

VSS_198

AJ3

VSS_199

AJ6

VSS_200

AJ9

VSS_201

AJ10

VSS_202

AJ12

VSS_203

AJ16

VSS_204

AJ19

VSS_205

AD17

VSS_206

AD20

VSS_207

AD23

VSS_208

AD26

VSS_209

AD29

VSS_210

AK7

VSS_211

AJ31

VSS_212

AJ28

VSS_213

AJ25

VSS_214

AJ22

VSS_215

AE9

VSS_216

AE11

VSS_217

AE12

VSS_218

AE15

VSS_219

AE18

VSS_220

AE21

VSS_221

AE24

VSS_222

AE27

VSS_223

AE30

VSS_224

AK11

VSS_225

AK13

VSS_226

K1

VSS_227

G4

VSS_228

M1

VSS_229

H1

VSS_230

J22

VSS_231

AB11

VSS_232

P13

VSS_58

VSS

P19

VSS_59

R3

VSS_60

M4

VSS_61

R9

VSS_62

G27

VSS_63

G30

VSS_64

H4

VSS_65

H5

VSS_66

H6

VSS_67

H7

VSS_68

H9

VSS_69

H11

VSS_70

H13

VSS_71

H16

VSS_72

H19

VSS_73

H22

VSS_74

H25

VSS_75

H28

VSS_76

H31

VSS_77

M7

VSS_78

M11

VSS_79

M15

VSS_80

M17

VSS_81

M21

VSS_82

N9

VSS_83

N10

VSS_84

N12

VSS_85

N20

VSS_86

J12

VSS_87

J14

VSS_88

J16

VSS_89

J18

VSS_90

J20

VSS_91

J23

VSS_92

K11

VSS_93

K13

VSS_94

K15

VSS_95

K17

VSS_96

K21

VSS_97

J3

VSS_98

L6

VSS_99

L9

VSS_100

L10

VSS_101

L12

VSS_102

L14

VSS_103

L16

VSS_104

L18

VSS_105

L20

VSS_106

L22

VSS_107

AL7

VSS_108

AL27

VSS_109

A15

VSS_110

AK17

VSS_111

AL11

VSS_112

AL15

VSS_113

AL13

VSS_114

MICRO-START INT'L CO.,LTD.

11 36Tuesday, November 22, 2011

of

1

of

5

VCC_DDR VCC3

MEM_MA_DQS_H[7..0]9 MEM_MA_DQS_L[7..0]9

MEM_MA_DATA[63..0]9

D D

C C

B B

MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63

122 123 128 129

131 132 137 138

140 141 146 147

149 150 155 156

200 201 206 207

209 210 215 216

100 105 106 218 219 224 225 108 109 114 115 227 228 233 234

101 104

3 4 9

10

12 13 18 19

21 22 27 28

30 31 36 37

81 82 87 88

90 91 96 97

99

2 5

8 11 14 17 20 23 26 29 32 35 38 41 44 47 80 83 86 89 92 95 98

DIMM1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

54

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

VSS

107

110

113

116

119

121

170

173

176

179

182

183

VDD

DDR3

VSS

124

127

VSS

130

133

136

139

142

145

148

151

154

157

DIMM1(CHANNEL-A A0) SM ADDRESS=A0

VTT_DDR

186

189

191

194

197

120

240

236

VTT

VDD

VSS

160

VTT

VDD

VDDSPD

VSS

163

166

199

202

205

208

211

214

217

4

MEM_MA_HOT#

48

187

198

53

167

68

79

RSVD

FREE1

FREE249FREE3

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

DM0/DQS9

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

CK1#(NU)

VSS

220

223

226

229

232

235

239

A0 A1

FREE4

A2 A3 A4 A5 A6 A7 A8 A9

A10/AP

A11 A12 A13 A14 A15

CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

ODT0 ODT1 CKE0 CKE1 CS0# CS1#

BA0 BA1 BA2

WE# RAS# CAS#

RESET#

CK0

CK0#

CK1(NU)

VREFDQ VREFCA

SCL

SDA

SA1 SA0

MEC1

MEC2

MEC3

DDRIII-240P_Blue-RH

MEC1

MEC2

MEC3

188 181 61 180 59 58 178 56 177 175 70 55 174 196 172 171

39 40 45 46 158 159 164 165

7 6 16 15 25 24 34 33 85 84 94 93 103 102 112 111 43 42

125 126 134 135 143 144 152 153 203 204 212 213 221 222 230 231 161 162

195 77 50 169 193 76 71 190 52

73 192 74 168

184 185 63 64

1 67 118 238 237 117

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15

MEM_MA_DQS_H0 MEM_MA_DQS_L0 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H7 MEM_MA_DQS_L7

MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7

MEM_MA0_ODT0 MEM_MA0_ODT1 MEM_MA_CKE0 MEM_MA_CKE1 MEM_MA0_CS_L0 MEM_MA0_CS_L1 MEM_MA_BANK0 MEM_MA_BANK1 MEM_MA_BANK2

MEM_MA_WE_L MEM_MA_RAS_L MEM_MA_CAS_L MEM_MA_RESET#

MEM_MA_CLK_H1 MEM_MA_CLK_L1 MEM_MA_CLK_H2 MEM_MA_CLK_L2

MEM_VREF_DQ_A MEM_VREF_CA MEM_SCLK MEM_SDATA

MEM_MA_HOT# 9

MEM_MA_ADD[15..0] 9

MEM_MA_DM[7..0] 9

MEM_MA0_ODT0 9 MEM_MA0_ODT1 9 MEM_MA_CKE0 9 MEM_MA_CKE1 9 MEM_MA0_CS_L0 9 MEM_MA0_CS_L1 9 MEM_MA_BANK0 9 MEM_MA_BANK1 9 MEM_MA_BANK2 9

MEM_MA_WE_L 9 MEM_MA_RAS_L 9 MEM_MA_CAS_L 9 MEM_MA_RESET# 9

MEM_MA_CLK_H1 9 MEM_MA_CLK_L1 9 MEM_MA_CLK_H2 9 MEM_MA_CLK_L2 9

MEM_VREF_CA

C97

C97 C0.1U25X

C0.1U25X

3

VCC_DDR VCC3

54

DIMM2

MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63

MEM_VREF_DQ_A MEM_VREF_DQ_A

C101

C1000P50X0402

C101

C1000P50X0402

DIMM2

3

DQ0

VDD51VDD

4

DQ1

9

DQ2

10

DQ3

122

DQ4

123

DQ5

128

DQ6

129

DQ7

12

DQ8

13

DQ9

18

DQ10

19

DQ11

131

DQ12

132

DQ13

137

DQ14

138

DQ15

21

DQ16

22

DQ17

27

DQ18

28

DQ19

140

DQ20

141

DQ21

146

DQ22

147

DQ23

30

DQ24

31

DQ25

36

DQ26

37

DQ27

149

DQ28

150

DQ29

155

DQ30

156

DQ31

81

DQ32

82

DQ33

87

DQ34

88

DQ35

200

DQ36

201

DQ37

206

DQ38

207

DQ39

90

DQ40

91

DQ41

96

DQ42

97

DQ43

209

DQ44

210

DQ45

215

DQ46

216

DQ47

99

DQ48

100

DQ49

105

DQ50

106

DQ51

218

DQ52

219

DQ53

224

DQ54

225

DQ55

108

DQ56

109

DQ57

114

DQ58

115

DQ59

227

DQ60

228

DQ61

233

DQ62

234

DQ63

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

80

VSS

83

VSS

86

VSS

89

VSS

92

VSS

95

VSS

98

VSS

101

VSS

104

VSS

107

110

113

116

170

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

VSS

119

121

124

127

130

133

136

139

142

DIMM2(CHANNEL-A A1) SM ADDRESS=A4

173

176

179

182

183

VDD

DDR3

VSS

145

148

151

154

157

2

VTT_DDR

186

189

191

194

197

53

167

68

120

240

79

236

VTT

VDD

VSS

160

VTT

VDD

VSS

163

166

199

202

205

VDDSPD

VSS

208

211

RSVD

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

VSS

214

217

220

223

226

229

232

48

187

FREE1

FREE249FREE3

A10/AP

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS8#

DM0/DQS9

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

RESET#

CK1(NU)

CK1#(NU)

VREFDQ VREFCA

VSS

MEC1

235

239

MEC1

MEM_MA_HOT#

198

188

A0

181

A1

FREE4

61

A2

180

A3

59

A4

58

A5

178

A6

56

A7

177

A8

175

A9

70 55

A11

174

A12

196

A13

172

A14

171

A15

39

CB0

40

CB1

45

CB2

46

CB3

158

CB4

159

CB5

164

CB6

165

CB7

7

DQS0

6 16

DQS1

15 25

DQS2

24 34

DQS3

33 85

DQS4

84 94

DQS5

93 103

DQS6

102 112

DQS7

111 43

DQS8

42 125

126 134 135 143 144 152 153 203 204 212 213 221 222 230 231 161 162

195

ODT0

77

ODT1

50

CKE0

169

CKE1

193

CS0#

76

CS1#

71

BA0

190

BA1

52

BA2

73

WE#

192

RAS#

74

CAS#

168 184

CK0

185

CK0#

63 64

1 67 118

SCL

238

SDA

237

SA1

117

SA0

MEC2

MEC3

DDRIII-240P_Green-RH

MEC2

MEC3

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15

MEM_MA_DQS_H0 MEM_MA_DQS_L0 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H7 MEM_MA_DQS_L7

MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7

MEM_MA1_ODT0 MEM_MA1_ODT1 MEM_MA_CKE0 MEM_MA_CKE1 MEM_MA1_CS_L0 MEM_MA1_CS_L1 MEM_MA_BANK0 MEM_MA_BANK1 MEM_MA_BANK2

MEM_MA_WE_L MEM_MA_RAS_L MEM_MA_CAS_L MEM_MA_RESET#

MEM_MA_CLK_H0 MEM_MA_CLK_L0 MEM_MA_CLK_H3 MEM_MA_CLK_L3

MEM_VREF_DQ_A MEM_VREF_CA MEM_SCLK MEM_SDATA

VCC3

MEM_MA1_ODT0 9 MEM_MA1_ODT1 9 MEM_MA_CKE0 9 MEM_MA_CKE1 9 MEM_MA1_CS_L0 9 MEM_MA1_CS_L1 9 MEM_MA_BANK0 9 MEM_MA_BANK1 9 MEM_MA_BANK2 9

MEM_MA_WE_L 9 MEM_MA_RAS_L 9 MEM_MA_CAS_L 9

MEM_MA_CLK_H0 9 MEM_MA_CLK_L0 9 MEM_MA_CLK_H3 9 MEM_MA_CLK_L3 9

MEM_VREF_CA

1

C79

C1000P50X0402

C79

C1000P50X0402

C80

C80 C0.1U25Y

C0.1U25Y

MEM_SCLK13 MEM_SDATA13

A A

Vref-DQ : Reference voltage for DQ0–DQ63, CB0–CB7 and PAR_IN. When in single ended mode used for DQS0–DQS7. Vref-CA : Reference voltage for A0-A15, BA0–BA2, RAS#, CAS#, WE#, S0#, S01#, CKE0, CKE1, ODT0 and ODT1.

RESET#(Output) : A synchronously forces all registered output LOW when RESET# is LOW. This signal can be used during power up to ensure that CKE is LOW and DQs are High-Z.

5

4

MEM_SCLK MEM_SDATA

R650 15R0402R650 15R0402 R655 15R0402R655 15R0402

SCLK0 17,25 SDATA0 17,25

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

DDR CH-A

K415-Virgo 0B

1

12 36Tuesday, November 22, 2011

of

5

4

3

2

1

VCC_DDR VCC3

MEM_MB_DQS_H[7..0]9 MEM_MB_DQS_L[7..0]9

MEM_MB_DATA[63..0]9 MEM_MB_ADD[15..0] 9

D D

C C

B B

MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63

122 123 128 129

131 132 137 138

140 141 146 147

149 150 155 156

200 201 206 207

209 210 215 216

100 105 106 218 219 224 225 108 109 114 115 227 228 233 234

101 104

3 4 9

10

12 13 18 19

21 22 27 28

30 31 36 37

81 82 87 88

90 91 96 97

99

2 5

8 11 14 17 20 23 26 29 32 35 38 41 44 47 80 83 86 89 92 95 98

DIMM3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

54

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

VSS

107

110

113

116

119

121

VSS

124

127

130

133

136

139

170

173

176

179

182

VDD

DDR3

VSS

142

145

148

151

154

DIMM3(CHANNEL-B B0) SM ADDRESS=A2

VTT_DDR

183

186

189

191

194

197

236

VDD

VSS

157

160

163

166

199

202

205

208

VDDSPD

VSS

211

48

53

167

68

120

240

79

VTT

RSVD

FREE1

FREE249FREE3

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

DM0/DQS9

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

CK1#(NU)

VSS

214

217

220

223

226

229

232

235

239

187

198

A0 A1

FREE4

A2 A3 A4 A5 A6 A7 A8 A9

A10/AP

A11 A12 A13 A14 A15

CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

ODT0 ODT1 CKE0 CKE1

CS0# CS1#

BA0 BA1 BA2

WE# RAS# CAS#

RESET#

CK0

CK0#

CK1(NU)

VREFDQ VREFCA

SCL SDA SA1 SA0

MEC1

MEC2

MEC3

DDRIII-240P_Blue-RH

MEC1

MEC2

MEC3

188 181 61 180 59 58 178 56 177 175 70 55 174 196 172 171

39 40 45 46 158 159 164 165

7 6 16 15 25 24 34 33 85 84 94 93 103 102 112 111 43 42

125 126 134 135 143 144 152 153 203 204 212 213 221 222 230 231 161 162

195 77 50 169 193 76 71 190 52

73 192 74 168

184 185 63 64

1 67 118 238 237 117

MEM_MB_HOT#

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

MEM_MB_DQS_H0 MEM_MB_DQS_L0 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H7 MEM_MB_DQS_L7

MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7

MEM_MB0_ODT0 MEM_MB0_ODT1 MEM_MB_CKE0 MEM_MB_CKE1 MEM_MB0_CS_L0 MEM_MB0_CS_L1 MEM_MB_BANK0 MEM_MB_BANK1 MEM_MB_BANK2

MEM_MB_WE_L MEM_MB_RAS_L MEM_MB_CAS_L MEM_MB_RESET#

MEM_MB_CLK_H1 MEM_MB_CLK_L1 MEM_MB_CLK_H2 MEM_MB_CLK_L2

MEM_VREF_DQ_B MEM_VREF_CA MEM_SCLK MEM_SDATA

VCC3

MEM_MB_HOT# 9

MEM_MB_DM[7..0] 9

MEM_MB0_ODT0 9 MEM_MB0_ODT1 9 MEM_MB_CKE0 9 MEM_MB_CKE1 9 MEM_MB0_CS_L0 9 MEM_MB0_CS_L1 9 MEM_MB_BANK0 9 MEM_MB_BANK1 9 MEM_MB_BANK2 9

MEM_MB_WE_L 9 MEM_MB_RAS_L 9 MEM_MB_CAS_L 9 MEM_MB_RESET# 9

MEM_MB_CLK_H1 9 MEM_MB_CLK_L1 9 MEM_MB_CLK_H2 9 MEM_MB_CLK_L2 9

MEM_VREF_CA

MEM_SCLK 12 MEM_SDATA 12

MEM_VREF_DQ_B

C88

C88 C0.1U25Y

C0.1U25Y

C98

C1000P50X0402

C98

C1000P50X0402

MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63

VCC_DDR VCC3

54

DIMM4

3

DQ0

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

4

DQ1

9

DQ2

10

DQ3

122

DQ4

123

DQ5

128

DQ6

129

DQ7

12

DQ8

13

DQ9

18

DQ10

19

DQ11

131

DQ12

132

DQ13

137

DQ14

138

DQ15

21

DQ16

22

DQ17

27

DQ18

28

DQ19

140

DQ20

141

DQ21

146

DQ22

147

DQ23

30

DQ24

31

DQ25

36

DQ26

37

DQ27

149

DQ28

150

DQ29

155

DQ30

156

DQ31

81

DQ32

82

DQ33

87

DQ34

88

DQ35

200

DQ36

201

DQ37

206

DQ38

207

DQ39

90

DQ40

91

DQ41

96

DQ42

97

DQ43

209

DQ44

210

DQ45

215

DQ46

216

DQ47

99

DQ48

100

DQ49

105

DQ50

106

DQ51

218

DQ52

219

DQ53

224

DQ54

225

DQ55

108

DQ56

109

DQ57

114

DQ58

115

DQ59

227

DQ60

228

DQ61

233

DQ62

234

DQ63

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

80

VSS

83

VSS

86

VSS

89

VSS

92

VSS

95

VSS

98

VSS

101

VSS

104

VSS

107

110

113

VSS

116

119

121

124

127

130

133

136

139

170

173

176

179

182

VDD

DDR3

VSS

142

145

148

151

154

DIMM4(CHANNEL-B B1) SM ADDRESS=A6

VTT_DDR

183

186

189

191

194

197

236

VDD

VSS

157

160

163

166

199

202

205

208

VDDSPD

VSS

211

48

53

167

68

120

240

79

VTT

RSVD

FREE1

FREE249FREE3

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

DM0/DQS9

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

CK1#(NU)

VSS

214

217

220

223

226

229

232

235

239

187

198

A0 A1

FREE4

A2 A3 A4 A5 A6 A7 A8 A9

A10/AP

A11 A12 A13 A14 A15

CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

ODT0 ODT1 CKE0 CKE1 CS0# CS1#

BA0 BA1 BA2

WE# RAS# CAS#

RESET#

CK0

CK0#

CK1(NU)

VREFDQ VREFCA

SCL SDA SA1 SA0

MEC1

MEC2

MEC3

DDRIII-240P_Green-RH

MEC1

MEC2

MEC3

188 181 61 180 59 58 178 56 177 175 70 55 174 196 172 171

39 40 45 46 158 159 164 165

7 6 16 15 25 24 34 33 85 84 94 93 103 102 112 111 43 42

125 126 134 135 143 144 152 153 203 204 212 213 221 222 230 231 161 162

195 77 50 169 193 76 71 190 52

73 192 74 168

184 185 63 64

1 67 118 238 237 117

MEM_MB_HOT#

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

MEM_MB_DQS_H0 MEM_MB_DQS_L0 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H7 MEM_MB_DQS_L7

MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7

MEM_MB1_ODT0 MEM_MB1_ODT1 MEM_MB_CKE0 MEM_MB_CKE1 MEM_MB1_CS_L0 MEM_MB1_CS_L1 MEM_MB_BANK0 MEM_MB_BANK1 MEM_MB_BANK2

MEM_MB_WE_L MEM_MB_RAS_L MEM_MB_CAS_L MEM_MB_RESET#

MEM_MB_CLK_H0 MEM_MB_CLK_L0 MEM_MB_CLK_H3 MEM_MB_CLK_L3

MEM_VREF_DQ_B MEM_VREF_CA MEM_SCLK MEM_SDATA

VCC3

MEM_MB1_ODT0 9 MEM_MB1_ODT1 9 MEM_MB_CKE0 9 MEM_MB_CKE1 9 MEM_MB1_CS_L0 9 MEM_MB1_CS_L1 9 MEM_MB_BANK0 9 MEM_MB_BANK1 9 MEM_MB_BANK2 9

MEM_MB_WE_L 9 MEM_MB_RAS_L 9 MEM_MB_CAS_L 9

MEM_MB_CLK_H0 9 MEM_MB_CLK_L0 9 MEM_MB_CLK_H3 9 MEM_MB_CLK_L3 9

MEM_VREF_CA

MEM_VREF_DQ_B

C121

C121 C0.1U25Y

C0.1U25Y

C124

C1000P50X0402

C124

C1000P50X0402

A A

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

DDR CH-B

K415-Virgo 0B

1

13 36Tuesday, November 22, 2011

of

A

DDR REF POWER & CAPS

VCC_DDR

B

C

D

E

De-coupling Caps For DIMMs

C242

X_C0.1u16Y0402

VTT_DDR

C759

X_C4.7u6.3X5

C760

X_C4.7u6.3X5

C376

C376 C1U10Y

C1U10Y

C377

C377 C1U10Y

C1U10Y

R182

VCC_DDR

R182

1KR1%

R181

1KR1%

R292

1KR1%

R333

1KR1%

R321

1KR1%

R325

1KR1%

C285

C133

C751

X_C0.1u10X0402

C282

C131

X_C1000P50X0402

C753

X_C1000P50X0402

MEM_VREF_CA

C761

MEM_VREF_DQ_A

MEM_VREF_DQ_B

C786

VCC3

C437

C0.1u16Y0402

C233

C233 C1U10Y

C1U10Y

C217

C217 C1U10Y

C1U10Y

C205

C205 C1U10Y

C1U10Y

C278

C278 C1U10Y

C1U10Y

C243

C243 C1U10Y

C1U10Y

C254

C254 C1U10Y

C1U10Y

C295

C295 C1U10Y

C1U10Y

C261

C261 C1U10Y

C1U10Y

VCC_DDRVCC_DDR

C292

C0.1u16Y0402

4 4

3 3

2 2

C0.1u10X0402

C1000P50X0402

1 1

MICRO-START INT'L CO.,LTD.

Title

DDR REF POWER & CAPS

Size Document Number Rev

B

Date: Sheet

A

B

C

D

Date: Sheet

MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

E

of

14 36Tuesday, November 22, 2011

5

4

3

2

1

D D

C C

B B

EMI Reserved

VCC5

C2 C0.1u16Y0402C2 C0.1u16Y0402 C4 C0.1u16Y0402C4 C0.1u16Y0402 C6 C0.1u16Y0402C6 C0.1u16Y0402 C8 C0.1u16Y0402C8 C0.1u16Y0402 C10 C0.1u16Y0402C10 C0.1u16Y0402 C13 C0.1u16Y0402C13 C0.1u16Y0402 C23 C0.1u16Y0402C23 C0.1u16Y0402

VCC5 VCC3

C36 X_C0.1u16Y0402C36 X_C0.1u16Y0402

VCC3_SB

C49 C0.1u16Y0402C49 C0.1u16Y0402 C55 X_C0.1u16Y0402C55 X_C0.1u16Y0402 C63 C0.1u16Y0402C63 C0.1u16Y0402 C69 X_C0.1u16Y0402C69 X_C0.1u16Y0402

-12V

C94 C0.1u16Y0402C94 C0.1u16Y0402 C103 X_C0.1u16Y0402C103 X_C0.1u16Y0402

VCC5

C115 C10u16Y1206C115 C10u16Y1206 C145 C10u16Y1206C145 C10u16Y1206

C301 X_C10u6.3X50805C301 X_C10u6.3X50805 C311 X_C10u6.3X50805C311 X_C10u6.3X50805

VCC3

C3 C0.1u16Y0402C3 C0.1u16Y0402 C5 C0.1u16Y0402C5 C0.1u16Y0402 C7 X_C0.1u16Y0402C7 X_C0.1u16Y0402 C9 X_C0.1u16Y0402C9 X_C0.1u16Y0402 C11 X_C0.1u16Y0402C11 X_C0.1u16Y0402

VCC5_SB

C81 X_C0.1u16Y0402C81 X_C0.1u16Y0402 C89 X_C0.1u16Y0402C89 X_C0.1u16Y0402 C15 X_C0.1u16Y0402C15 X_C0.1u16Y0402 C25 X_C0.1u16Y0402C25 X_C0.1u16Y0402

+12V

C51 C0.1u16Y0402C51 C0.1u16Y0402 C58 X_C0.1u16Y0402C58 X_C0.1u16Y0402 C65 X_C0.1u16Y0402C65 X_C0.1u16Y0402 C72 X_C0.1u16Y0402C72 X_C0.1u16Y0402

VCC3

C313 X_C10u6.3X50805C313 X_C10u6.3X50805

VCCP

C773 C0.1u16Y0402C773 C0.1u16Y0402 C769 X_C0.1u16Y0402C769 X_C0.1u16Y0402

C766 X_C0.1u16Y0402C766 X_C0.1u16Y0402 C78 X_C0.1u16Y0402C78 X_C0.1u16Y0402

C767 X_C0.1u16Y0402C767 X_C0.1u16Y0402 C768 X_C0.1u16Y0402C768 X_C0.1u16Y0402 C752 X_C0.1u16Y0402C752 X_C0.1u16Y0402 C765 X_C0.1u16Y0402C765 X_C0.1u16Y0402

C776 C0.1u16Y0402C776 C0.1u16Y0402 C775 C0.1u16Y0402C775 C0.1u16Y0402

C777 C0.1u16Y0402C777 C0.1u16Y0402

C780 X_C0.1u16Y0402C780 X_C0.1u16Y0402 C778 X_C0.1u16Y0402C778 X_C0.1u16Y0402 C779 C0.1u16Y0402C779 C0.1u16Y0402 C781 X_C0.1u16Y0402C781 X_C0.1u16Y0402

VCC_DDR

C349

X_C0.1u16Y0402

C348

X_C0.1u16Y0402

A A

MICRO-START INT'L CO.,LTD.

Title

EMI Reserved

Size Document Number Rev

Custom

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

1

15 36Tuesday, November 22, 2011

of

5

4

3

2

1

HUDSON PCIE/PCI/APU/LPC/CLK

U600E

A_RST# for LPC device; PCIE_RST# for APU PCIE device; PCIE_RST#2 FCH PCIE device

FCH_PCIE_RST#_R

D D

FCH_A_RST#_R

R527 33R0402R527 33R0402

R526 33R0402R526 33R0402

C585

C1000P50X0402

A_RST#

C584

X_C150p25N0402

PCIE_RST# 24,31,32,33

To PCIEX16,X1,LAN

A_RST# 25

To SIO,LPC debug

UMI_RX0P8 UMI_RX0N8 UMI_RX1P8 UMI_RX1N8 UMI_RX2P8 UMI_RX2N8 UMI_RX3P8 UMI_RX3N8

UMI_TX0P8 UMI_TX0N8 UMI_TX1P8 UMI_TX1N8 UMI_TX2P8 UMI_TX2N8 UMI_TX3P8 UMI_TX3N8

FCH_VDD11_RUN

GPP_TXC_0P32 GPP_TXC_0N32 GPP_TXC_1P32 GPP_TXC_1N32 GPP_TXC_2P32 GPP_TXC_2N32 MINI_TXC_P33 MINI_TXC_N33

C C

DISP_CLK10

For external clock generator mode: 100-MHz reference clock for the FCH. Spreadcapable. For internal clock generator mode: Not used. Left unconnected. The function is selected by the pin strap “CLKGEN” (pin LPCCLK1).

B B

C610 X_C10p50N0402C610 X_C10p50N0402

SIO_48M_CLK

DISP_CLK#10

Fusion Mode:100Mhz Non-Fusion Mode:200Mhz

APU_CLK10 APU_CLK#10

PE16_GXF_CLK31 PE16_GXF_CLK#31

PE1_GPP_CLK032 PE1_GPP_CLK0#32

PE1_GPP_CLK132 PE1_GPP_CLK1#32

PE1_GPP_CLK232 PE1_GPP_CLK2#32

PE_LAN_CLK24 PE_LAN_CLK#24

PE_MINI_CLK33 PE_MINI_CLK#33

SIO_48M_CLK25

FCH_VDD11_RUN

MACH@bios porting to 48M clock output

C468 C0.1u10X0402C468 C0.1u10X0402 C469 C0.1u10X0402C469 C0.1u10X0402 C467 C0.1u10X0402C467 C0.1u10X0402 C466 C0.1u10X0402C466 C0.1u10X0402 C464 C0.1u10X0402C464 C0.1u10X0402 C465 C0.1u10X0402C465 C0.1u10X0402 C462 C0.1u10X0402C462 C0.1u10X0402 C463 C0.1u10X0402C463 C0.1u10X0402

R386 590R1%0402R386 590R1%0402

Layout: Place within 1 inch

R451 2KR1%0402R451 2KR1%0402

R380 0R0402R380 0R0402 R379 0R0402R379 0R0402

INT

R412 0R0402R412 0R0402 R405 0R0402R405 0R0402

R423 0R0402R423 0R0402 R417 0R0402R417 0R0402

R461 0R0402R461 0R0402 R462 0R0402R462 0R0402

R463 0R0402R463 0R0402 R464 0R0402R464 0R0402

R465 0R0402R465 0R0402 R466 0R0402R466 0R0402

R443 0R0402R443 0R0402 R437 0R0402R437 0R0402

R681 0R0402R681 0R0402 R677 0R0402R677 0R0402

MACH@???DG:Leave NC if not used;

R460 22R0402R460 22R0402

C487 C22p50N0402C487 C22p50N0402

Y2

Y2 25MHZ18P_D-4

25MHZ18P_D-4

C451 C22p50N0402C451 C22p50N0402

1 2

Layout:Place x'tal within 1.5 inch of FCH

FCH_25M_X120 FCH_25M_X220

FCH_PCIE_RST#_R FCH_A_RST#_R

R387 2KR1%0402R387 2KR1%0402

C473 C0.1u10X0402C473 C0.1u10X0402 C474 C0.1u10X0402C474 C0.1u10X0402 C533 C0.1u10X0402C533 C0.1u10X0402 C534 C0.1u10X0402C534 C0.1u10X0402 C614 C0.1u10X0402C614 C0.1u10X0402 C615 C0.1u10X0402C615 C0.1u10X0402 C446 C0.1U10X0402C446 C0.1U10X0402 C322 C0.1U10X0402C322 C0.1U10X0402

GPP_RX0P32 GPP_RX0N32 GPP_RX1P32 GPP_RX1N32 GPP_RX2P32 GPP_RX2N32 MINI_RXP33 MINI_RXN33

FCH_DISP_CLKP_R FCH_DISP_CLKN_R

FCH_APU_CLKP_R FCH_APU_CLKN_R

FCH_GFX_CLKP_R FCH_GFX_CLKN_R

FCH_GPP_CLK0P_R FCH_GPP_CLK0N_R

FCH_GPP_CLK1P_R FCH_GPP_CLK1N_R

FCH_GPP_CLK2P_R FCH_GPP_CLK2N_R

FCH_GPP_CLK3P_R FCH_GPP_CLK3N_R

FCH_MINI_CLKP_R FCH_MINI_CLKN_R

CRB reserve 49.9R to GND

FCH_48M

R408

R408 1MR

1MR

FCH_25M_X1 FCH_25M_X2

UMI_RX0P_FCH UMI_RX0N_FCH UMI_RX1P_FCH UMI_RX1N_FCH UMI_RX2P_FCH UMI_RX2N_FCH UMI_RX3P_FCH UMI_RX3N_FCH

PCIE_CALRP PCIE_CALRN

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N MINI_TXP MINI_TXN

CLK_CALRN

FCH_25M_X1

FCH_25M_X2

AE30 AE32 AD33 AD31 AD28 AD29 AC30 AC32

AB33 AB31 AB28 AB29

AF29 AF31

AB26 AB27 AA24 AA23

AA27 AA26

AE2 AD5

Y33 Y31 Y28 Y29

V33 V31 W30 W32

W27 V27 V26 W26 W24 W23

F27

G30 G28

R26

T26

H33 H31

T24 T23

J30

K29 H27

H28

J27

K26

F33 F31

E33 E31

M23 M24

M27 M26

N25 N26

R23 R24

N27 R27

J26

C31

C33

PCIE_RST# A_RST#

UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N

UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N

PCIE_CALRP PCIE_CALRN

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N

GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N

CLK_CALRN

PCIE_RCLKP PCIE_RCLKN

DISP_CLKP DISP_CLKN

DISP2_CLKP DISP2_CLKN

APU_CLKP APU_CLKN

SLT_GFX_CLKP SLT_GFX_CLKN

GPP_CLK0P GPP_CLK0N

GPP_CLK1P GPP_CLK1N

GPP_CLK2P GPP_CLK2N

GPP_CLK3P GPP_CLK3N

GPP_CLK4P GPP_CLK4N

GPP_CLK5P GPP_CLK5N

GPP_CLK6P GPP_CLK6N

GPP_CLK7P GPP_CLK7N

GPP_CLK8P GPP_CLK8N

14M_25M_48M_OSC

25M_X1

25M_X2

HUDSON-2

U600E

Part 1 of 5

PCI CLKS

PCI EXPRESS INTERFACES

CLOCK GENERATOR

APU

S5 PLUS

?

PCICLK4/14M_OSC/GPO39

PCI INTERFACE

REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT3#/CLK_REQ7#/GPIO46

LPC

LDRQ1#/CLK_REQ6#/GPIO49

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

FRAME# DEVSEL#

STOP#

REQ1#/GPIO40

GNT1#/GPO44

GNT2#/SD_LED/GPO45

CLKRUN#

INTE#/GPIO32 INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LPCCLK0 LPCCLK1

LFRAME#

LDRQ0#

SERIRQ/GPIO48

DMA_ACTIVE#

PROCHOT#

APU_PG LDT_STP# APU_RST#

32K_X1

32K_X2

S5_CORE_EN

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

AF3 AF1 AF5 AG2 AF6

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12

AD23

AE12

AD24

AC12

AD25

AE13

AD26

AF13

AD27

AH13 AH14 AD15 AC15 AE16

CBE0#

AN3

CBE1#

AJ8

CBE2#

AN10

CBE3#

AD12 AG10 AK9

IRDY#

AL10

TRDY#

AF10

PAR

AE10 AH1

PERR#

AM9

SERR#

AH8

REQ0#

AG15 AG13 AF15

PREQ3#

AM17

GNT0#

AD16 AD13 AD21

PGNT#3

AK17 AD19

LOCK#

AH9 AF18

AE18 AC16 AD18

LPC_CLK0

B25

LPC_CLK1

D25

LPC_AD0

LAD0

D27

LPC_AD1

LAD1

C28

LPC_AD2

LAD2

A26

LPC_AD3

LAD3

A29

LPC_FRAME#

A31 B27 AE27

SERIRQ

AE19

G25 E28

APU_PG_R

E26

LDTSTOP_L_R

G26

APU_RST#_R

F26

FCH_32K_X1

G2

FCH_32K_X2

G4

S5_CORE_EN

H7

RTC_CLK

F1 F3

VBAT_FCH

E6

Layout:Place x'tal within 1.5 inch of FCH

FCH_32K_X1

A A

FCH_32K_X2

12

4

3

Y5

32.768KHZ12.5P_D-1

R519 20MRR519 20MR

C573

C18p50N

mach@CRB use 22pF

5

4

3

C18p50N

PLACE THESE COMPONENTS CLOSE TO U600, AND USE GROUND GUARD FOR 32K_X1 AND 32K_X2

C574

C18p50N

Layout: Place close to FCH

PCI_CLK_SIO_R PCI_CLK_SIO PCI_CLK2_R

PCIRST#

R529 33R0402R529 33R0402 R551 22R0402R551 22R0402

TP66TP66

PCI_CLK_DEBUG

CLR_CMOS

If PCI not implemented: Provide test points or other means to allowaccess for debug purposes. use these balls for alternate GPIO/GPO functions or leave unconnected.

AD23 20 AD24 20 AD25 20 AD26 20 AD27 20

PREQ3# 20

PGNT#3 20

LPC_CLK0 20 LPC_CLK1 20 LPC_AD[3..0] 25

LPC_AD[3..0]

LPC_FRAME# 25

SERIRQ 25

FCH_DMA_ACTIVE# 10

R447 0R0402R447 0R0402

R442 0R0402R442 0R0402

R450 0R0402R450 0R0402

TP63TP63

Layout: Place close to pin B1 ASAP 0603 size and X5R for CMOS issue

FCH_PROCHOT# 10

APU_PWRGD 7,10 LDTSTOP_L 10 APU_RST# 10

This signal is for enabling the standby power when S5 plus logic is enabled

RTC_CLK 20

C550

C546

C546 C0.1U25X

C0.1U25X

C550

C1u10X7R

2

PCI_CLK_SIO 25 PCI_CLK1 20 PCI_CLK_DEBUG 25 PCI_CLK3 20 PCI_CLK4 20

PCI_CLK_SIO PCI_CLK_DEBUG

C565 X_C10p50N0402C565 X_C10p50N0402 C598 X_C10p50N0402C598 X_C10p50N0402

CLEAR CMOS

VCC3

R534

R534 10KR0402

10KR0402

CLR_CMOS

Note: LDT_PG, LDT_STP# & LDT_RST# are OD and require a PU to the APU I/O rail. They are also in the S5 domain to prevent glitching at power up.

VBAT

R533 510R0402R533 510R0402

Title

Size Document Number Rev

C

Date: Sheet

1 2 3

H1X3M_RED-RH

CMOS CLEAR JUMPER CLR_COMS Clear CMOS

1 - 2

Normal

2 - 3 Clear CMOS

SERIRQ

R418 X_10KR0402R418 X_10KR0402

Layout: VBAT route 20mils

BAT1

BAT2P_BLACK-RH

MICRO-START INT'L CO.,LTD.

HUDSON PCIE/PCI/APU/LPC/CLK

K415-Virgo 0B

1

CLR_CMOS_X1

JUMP1X2A_RED-RH

6.0

16 36Tuesday, November 22, 2011

VCC3

of

5

4

3

2

1

HUDSON ACPI/USB/AZ/GPIO

mach@???DS require external PU;

VCC3_SB

D D

VCC3

VCC3_SB

VCC3

VCC3_SB

C C

+3VAUX_WLAN

VCC3_SB

AZ_SDOUT28 AZ_BIT_CLK28

AZ_SYNC28 AZ_RST#28

B B

R550 may stuff 15pF cap for EMI

A A

DG/CRB W/O PU resister

R525 X_10KR0402R525 X_10KR0402 R521 X_10KR0402R521 X_10KR0402

R568 10KR0402R568 10KR0402

Layout:Place close to FCH ASAP

FCH_PWRGD

mach@DG???PU to VCC3 rail and leave unconnected

R429 300R0402R429 300R0402

R566 X_22KR0402R566 X_22KR0402

R384 2.2KR0402R384 2.2KR0402 R385 2.2KR0402R385 2.2KR0402

R544 2.2KR0402R544 2.2KR0402 R543 2.2KR0402R543 2.2KR0402

R682 10KR0402R682 10KR0402

RN14 8P4R-10KR0402RN14 8P4R-10KR0402

1 3 5 7

RN13 8P4R-10KR0402RN13 8P4R-10KR0402

1 3 5 7

SLP_S3# SLP_S5#

FCH_WAKE#

C595 X_C1000P50X0402C595 X_C1000P50X0402

WD_PWRGD

FCH_RSMRST#

C559

C559 C1000P50X0402

C1000P50X0402

SCLK0 SDATA0

SCLK1 SDATA1

MINI_PWRON

OC#1

2

OC#3

4

OC#7

6

OC#6

8

OC#2

2

OC#4

4

OC#0

6

OC#5

8

USB Overcurrent Implemented: Connect to overcurrent signal from USB connector (note that these are programmable and can be flexibly assigned as needed). Configure for a

3.3-V swing (i.e. not 5-V) and use low-pass filter to prevent glitches during plug/unplug events. If USB ports are not powered in S4/S5 states and the FCH’s internal pullups are enabled, provide a diode between the FCH and overcurrent circuit (cathode towards the FCH) to prevent leakage from the FCH internal pullups in S4/S5 states.

Layout: Place close to FCH

5

AZ_SDATA_OUT_R AZ_BITCLK_R AZ_SYNC_R AZ_RST_R

AZ_SDIN

AZ_BIT_CLK AZ_SDIN

R547 33R0402R547 33R0402 R662 33R0402R662 33R0402 R663 33R0402R663 33R0402 R664 33R0402R664 33R0402

C562 15p50N0402C562 15p50N0402

R550 X_10KR0402R550 X_10KR0402 R554 X_10KR0402R554 X_10KR0402

FCH HAS INTE-GRATED PU RESISTER

VCC3_SB

R79 X_4.7KR0402R79 X_4.7KR0402 R168 X_10KR0402R168 X_10KR0402

IO_PME# LPC_SMI#

Inte-grated PU

Rise time ≤ 50-ms

+3.3V_S5 voltage rails ramp up at least 10-ms

before RSMRST# is deasserted

VCC3

R438 10KR0402R438 10KR0402

RSRMT# should be asserted when system power is being applied for the first time. RSMRST# should be deasserted sometime after S5 power is up, and should stay deasserted until system power is removed.

S0 POWER DOMAIN

ROUTE TO DIMMs,SIO

S5 POWER DOMAIN

ROUTE TO LAN,PCIE,Mini_PCIE

FCH_IDLEEXIT_L

SIO_GP25_SMI#25

MACH@ RESERVE TP

SLP_S3# SLP_S5#

FCH_TEST020 FCH_TEST120 FCH_TEST220

IO_PME# LPC_SMI#

R686

R541 X_0R0402R541 X_0R0402

R567 0R0402R567 0R0402

R556 15R0402R556 15R0402 R584 15R0402R584 15R0402

SCLK0 SDATA0 SCLK1 SDATA1

SLP_S3#25,26,27 SLP_S5#25,26,27,30 PSOUT#25

FCH_PWRGD25,27

A20GATE25 KBRST#25

0R0402

FP_RST#27,34

PE_WAKE#24,25,31,32,33

FCH_THERMTRIP#10

IO_RSMRST#25

SPKR34 SCLK012,25 SDATA012,25 SCLK131,32,33 SDATA131,32,33

MINI_PWRON33

SPI_HOLD#_R18

FCH_IDLEEXIT_L10

mach@verify the ports being used

OC#730 OC#630 OC#530 OC#430 OC#320,30 OC#220,30 OC#120,30

OC#0

OC#020,30

Inte-grated PU

AZ_SDIN28

FOR GPIO[226:209] KBC Not Implemented: Use for alternate available function or leave not connected.

AZ_BITCLK_R AZ_SDATA_OUT_R

AZ_SDIN AZ_SYNC_R AZ_RST_R

TP35TP35 TP34TP34

CHASSIS_ID225 CHASSIS_ID125 MB_ID125 MB_ID025

N_RI25

4

FCH_GEVENT4#

PSOUT# FCH_PWRGD

FCH_TEST0 FCH_TEST1 FCH_TEST2

FCH_WAKE#

WD_PWRGD FCH_RSMRST#

MINI_PWRON

SPI_HOLD#_R

FCH_IDLEEXIT_L

CHASSIS_ID2 CHASSIS_ID1

MB_ID1 MB_ID0

SLP_S3#_R SLP_S5#_R

AB6

RI#

W7 W2

T10

AE22 AG19

C26

R10

AF19

AG24 AE24 AE26 AF22 AH17 AG18 AF24 AD26 AD25

AG25 AG22

AG26

W8

V10 AA8

AF25

AB3 AB1 AA2

AD6

AE4

K19 J19 J21

D21 C20 D23 C22

F21 E20 F20 A22 E18 A20 J18 H18 G18 B21 K18 D19 A18 C18 B19 B17 A24 D17

PCIE_RST2#/GEVENT4# RI#/GEVENT22#

R2

SPI_CS3#/GBE_STAT1/GEVENT21# SLP_S3#

T3

SLP_S5# PWR_BTN#

J4

PWR_GOOD

N7

TEST0

T9

TEST1/TMS TEST2

V9

GA20IN/GEVENT0# KBRST#/GEVENT1# PME#/GEVENT3#

R9

LPC_SMI#/GEVENT23# LPC_PD#/GEVENT5#

T5

SYS_RESET#/GEVENT19#

U4

WAKE#/GEVENT8#

K1

IR_RX1/GEVENT20#

V7

THRMTRIP#/SMBALERT#/GEVENT2# WD_PWRGD

RSMRST#

U2

CLK_REQ4#/SATA_IS0#/GPIO64 CLK_REQ3#/SATA_IS1#/GPIO63 SMARTVOLT1/SATA_IS2#/GPIO50 CLK_REQ0#/SATA_IS3#/GPIO60 SATA_IS4#/FANOUT3/GPIO55 SATA_IS5#/FANIN3/GPIO59 SPKR/GPIO66 SCL0/GPIO43 SDA0/GPIO47 SCL1/GPIO227

T7

SDA1/GPIO228

R7

CLK_REQ2#/FANIN4/GPIO62 CLK_REQ1#/FANOUT4/GPIO61 IR_LED#/LLB#/GPIO184

J2

SMARTVOLT2/SHUTDOWN#/GPIO51 DDR3_RST#/GEVENT7#/VGA_PD

V8

GBE_LED0/GPIO183 SPI_HOLD#/GBE_LED1/GEVENT9#

Y6

GBE_LED2/GEVENT10# GBE_STAT0/GEVENT11# CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

BLINK/USB_OC7#/GEVENT18#

M7

USB_OC6#/IR_TX1/GEVENT6#

R8

USB_OC5#/IR_TX0/GEVENT17#

T1

USB_OC4#/IR_RX0/GEVENT16#

P6

USB_OC3#/AC_PRES/TDO/GEVENT15#

F5

USB_OC2#/TCK/GEVENT14#

P5

USB_OC1#/TDI/GEVENT13#

J7

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#

T8

AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO167 AZ_SDIN1/GPIO168

Y5

AZ_SDIN2/GPIO169

Y3

AZ_SDIN3/GPIO170

Y1

AZ_SYNC AZ_RST#

PS2_DAT/SDA4/GPIO187 PS2_CLK/CEC/SCL4/GPIO188 SPI_CS2#/GBE_STAT2/GPIO166

PS2KB_DAT/GPIO189 PS2KB_CLK/GPIO190 PS2M_DAT/GPIO191 PS2M_CLK/GPIO192

KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217 KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/XDB0/GPIO223 KSO_15/XDB1/GPIO224 KSO_16/XDB2/GPIO225 KSO_17/XDB3/GPIO226

Wake On Modem Header

N_RI RI#

+12VActive Low

HighNormal -12V

R578 10KR0402R578 10KR0402

R577

R577 10KR0402

10KR0402

B

C621

C621 X_C1U16X5

X_C1U16X5

U600A

HUDSON-2

Part 4 of 5

HD AUDIO

EMBEDDED CTRL

?

INT 10k PU

RI#RI#

CE

Q68

C620

C620 X_C1000P50X0402

X_C1000P50X0402

N-SST3904_SOT23

3

USB MISCUSB 1.1

ACPI / WAKE UP EVENTS

USB 2.0

GPIO

USB OC

USB 3.0

EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198

EC_PWM2/EC_TIMER2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER3/GPIO200

USBCLK/14M_25M_48M_OSC

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

SCL3_LV/GPIO195

SDA3_LV/GPIO196

14M_25M_48M_OSC

G8

USB_RCOMP

B9

Layout: Place within 1'' of FCH

H1

USB_FSD1N

H3 H6

USB_FSD0N

H5

USB_HSD13P

H10

USB_HSD13N

G10

USB_HSD12P

K10

USB_HSD12N

J12

USB_HSD11P

G12

USB_HSD11N

F12

USB_HSD10P

K12

USB_HSD10N

K13

USB_HSD9P

B11

USB_HSD9N

D11

USB_HSD8P

E10

USB_HSD8N

F10

USB_HSD7P

C10

USB_HSD7N

A10

USB_HSD6P

H9

USB_HSD6N

G9

USB_HSD5P

A8

USB_HSD5N

C8

USB_HSD4P

F8

USB_HSD4N

E8

USB_HSD3P

C6

USB_HSD3N

A6

USB_HSD2P

C5

USB_HSD2N

A5

USB_HSD1P

C1

USB_HSD1N

C3

USB_HSD0P

E1

USB_HSD0N

E3

USBSS_CALRP

C16

USBSS_CALRN

A16

USB_SS_TX3P

A14

USB_SS_TX3N

C14

USB_SS_RX3P

C12

USB_SS_RX3N

A12

USB_SS_TX2P

D15

USB_SS_TX2N

B15

USB_SS_RX2P

E14

USB_SS_RX2N

F14

USB_SS_TX1P

F15

USB_SS_TX1N

G15

USB_SS_RX1P

H13

USB_SS_RX1N

G13

USB_SS_TX0P

J16

USB_SS_TX0N

H16

USB_SS_RX0P

J15

USB_SS_RX0N

K15

FCH_GPO193

SCL2/GPIO193

H19

FCH_GPI194

SDA2/GPIO194

G19

SCLK3

G22

SDATA3

G21

FCH_GPI197

E22

FCH_GPI198

H22 J22 H21

KSI_0/GPIO201

K21

KSI_1/GPIO202

K22

KSI_2/GPIO203

F22

KSI_3/GPIO204

F24

KSI_4/GPIO205

E24

KSI_5/GPIO206

B23

KSI_6/GPIO207

C24

KSI_7/GPIO208

F18

USB13+ 29 USB13- 29

USB12+ 29 USB12- 29

USB11+ 29 USB11- 29

USB10+ 29 USB10- 29

USB9+ 29 USB9- 29

USB8+ 29 USB8- 29

USB6+ 33 USB6- 33

USB5+ 29 USB5- 29

USB4+ 29 USB4- 29

USB3+ 29 USB3- 29

USB2+ 29 USB2- 29

USB1+ 29 USB1- 29

USB0+ 29 USB0- 29

FCH_GPIO199 20

FCH_GPO200 23

TP80TP80

USB_SS_TX3P 29 USB_SS_TX3N 29

USB_SS_RX3P 29 USB_SS_RX3N 29

USB_SS_TX2P 29 USB_SS_TX2N 29

USB_SS_RX2P 29 USB_SS_RX2N 29

USB_SS_TX1P 29 USB_SS_TX1N 29

USB_SS_RX1P 29 USB_SS_RX1N 29

USB_SS_TX0P 29 USB_SS_TX0N 29

USB_SS_RX0P 29 USB_SS_RX0N 29

TP81TP81 TP82TP82

R491 11.8KR1%0402R491 11.8KR1%0402

R483 1KR1%0402R483 1KR1%0402 R484 1KR1%0402R484 1KR1%0402

FCH_GPO200

FOR GPIO[208:197] KBC Not Implemented: Use for alternate available function or leave not connected.

MODE SWITCH HEADER

Model_Ctrl

FCH_GPO193

GP0

FCH_GPI197 FCH_GPI198

2

mach@Rerouting the USB pairs follow layout

USB11 FRONT PANEL USB10 FRONT PANEL USB9 FRONT PANEL USB8 FRONT PANEL USB7 FRONT PANEL USB6 FRONT PANEL

USB3 USB2 BOTTOM USB2 USB2 TOP USB1 LAN USB BOTTOM USB0 LAN USB TOP

FCH_VDD_11_SSUSB_S

FOR Pin H19,G19 Use as GPIO or configure as one of the following: 10-kΩ 5% pull-up resistor to +3.3V_S5. 10-kΩ 5% pull-down resistor.

FCH_GPO193 FCH_GPI194 FCH_GPI197 FCH_GPI198 FCH_GPO200

MODE_SW_HEADER

1

MODE_TRIG

43 65

H2X3[2]M_BLACK-RH

MODE_TRIG

Note:Must can trap SMI/SCI.

KEY Mode_Triggy GP1

R724 X_0R0402R724 X_0R0402 R672 0R0402R672 0R0402

R67310KR0402 R67310KR0402 R700X_10KR0402 R700X_10KR0402 R72110KR0402 R72110KR0402 R72210KR0402 R72210KR0402 R72310KR0402 R72310KR0402

VCC3_SB

Mode Postion

FCH_GPI194 FCH_GEVENT4#

Title

HUDSON ACPI/USB/AZ/GPIO

Size Document Number Rev

C

Date: Sheet

GP0/GP1 0/0

COOL

0/1

AUTO

1/0

TUROR RESERVED

1/1GND

MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

1

17 36Tuesday, November 22, 2011

of

5

4

3

2

1

HUDSON SATA/VGA/SPI/HWM

D D

SATA[3::0]Route to iSATA GEN III 6.0 Gbit/S

SATA[5::4]Route to e-SATA

C C

GEN II 3.0 Gbit/S

FCH_VDD11_RUN

External Clock Generator Mode: Connect to 25.000-MHz XTAL or connect SATA_X1/X2 balls to 100MHz differential clock from external clock generator. Integrated Clock Mode: Leave unconnected.

B B

LAYOUT: ROUTE SATA TX DIFF PAIR @ 100 OHM+/-10% RX DIFF PAIR @ 90 OHM+/-10%

TP83TP83

TP84TP84

SATA_TX0+ SATA_TX0-

SATA_RX0SATA_RX0+

SATA_TX1+ SATA_TX1-

SATA_RX1SATA_RX1+

SATA_TX2+ SATA_TX2-

SATA_RX2SATA_RX2+

SATA_TX3+ SATA_TX3-

SATA_RX3SATA_RX3+

SATA_TX4+ SATA_TX4-

SATA_RX4SATA_RX4+

SATA_LED#

SATA_CALRP SATA_CALRN

FCH_SATA_X1

FCH_SATA_X2

SATA_TX0+23 SATA_TX0-23

SATA_RX0-23 SATA_RX0+23

SATA_TX1+23 SATA_TX1-23

SATA_RX1-23 SATA_RX1+23

SATA_TX2+23 SATA_TX2-23

SATA_RX2-23 SATA_RX2+23

SATA_TX3+23 SATA_TX3-23

SATA_RX3-23 SATA_RX3+23

SATA_TX4+23 SATA_TX4-23

SATA_RX4-23 SATA_RX4+23

Layout: Place within 1'' of FCH

R388 1KR1%0402R388 1KR1%0402 R389 1KR1%0402R389 1KR1%0402

SATA_LED#34

FANOUT020

PIN K3,K5,K6: Use as GPIO182 or configure as one of the following: 10-kΩ 5% pull-up resistor to +3.3V_S5. 10-kΩ 5% pull-down resistor.

FCH_TALERT#10

FCH_TALERT#

AK19 AM19

AN20 AN22

AH20

AH22 AM23

AK23 AH24

AN24

AN26

AH26 AN29

AK27 AM27

AN31

AH33 AH31

AD22

AG21

AH16 AM15

AK15 AN16

AL20

AL22

AJ20 AJ22

AJ24

AL24 AL26

AJ26

AL28

AL29

AL31 AL33

AJ33 AJ31

AF28 AF27

AF21

AJ16

AL16

K6 K5 K3 M6

SATA_TX0P SATA_TX0N

SATA_RX0N SATA_RX0P

SATA_TX1P SATA_TX1N

SATA_RX1N SATA_RX1P

SATA_TX2P SATA_TX2N

SATA_RX2N SATA_RX2P

SATA_TX3P SATA_TX3N

SATA_RX3N SATA_RX3P

SATA_TX4P SATA_TX4N

SATA_RX4N SATA_RX4P

SATA_TX5P SATA_TX5N

SATA_RX5N SATA_RX5P

NC6 NC7

NC8 NC9

NC10 NC11

NC12 NC13

SATA_CALRP SATA_CALRN

SATA_ACT#/GPIO67

SATA_X1

SATA_X2

FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54

FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58

TEMPIN0/GPIO171 TEMPIN1/GPIO172 TEMPIN2/GPIO173 TEMPIN3/TALERT#/GPIO174

HUDSON-2

?

SERIAL ATA

HW MONITOR

U600B

Part 2 of 5

SD CARD

SPI ROM

VGA DAC

VGA MAINLINK

GBE LAN

SD_CLK/SCLK_2/GPIO73

SD_CMD/SLOAD_2/GPIO74

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

ROM_RST#/SPI_WP#/GPIO161

VGA_DDC_SDA/GPO70 VGA_DDC_SCL/GPO71

ML_VGA_HPD/GPIO229

VIN2/SDATI_1/GPIO177

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

SD_CD#/GPIO75

SD_WP/GPIO76

SD_DATA2/GPIO79 SD_DATA3/GPIO80

GBE_COL GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXCLK

GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0

GBE_RXCTL/RXDV

GBE_RXERR

GBE_TXCLK

GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0

GBE_TXCTL/TXEN

GBE_PHY_PD

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164 SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

VGA_RED

VGA_GREEN

VGA_BLUE

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

VGA_DAC_RSET

AUX_VGA_CH_P AUX_VGA_CH_N

AUXCAL

ML_VGA_L0P ML_VGA_L0N ML_VGA_L1P ML_VGA_L1N ML_VGA_L2P ML_VGA_L2N ML_VGA_L3P ML_VGA_L3N

VIN0/GPIO175 VIN1/GPIO176

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

GBE_COL

AC4

GBE_CRS

AD3 AD9

GBE_MDIO

W10 AB8 AH7 AF7 AE7 AD7 AG8

GBE_RXERR

AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7

GBE_PHY_INTR

W9

V6 V5 V3 T6 V1

L30 L32 M29

M28 N30

M33 N32

K31 V28

V29 U28 T31

T33 T29 T28 R32 R30 P29 P28

C29 N2

M3 L2 N4 P1 P3 M1 M5

NC1

AG16

NC2

AH10

NC3

A28

NC4

G27

NC5

L4

Layout:For SPI Trace length within 4''

SPI_DATAIN SPI_DATAOUT_R SPI_CLK_R SPI_CS#_R SPI_WP#_R

HUDSON_VGA_R

R402 150R1%0402R402 150R1%0402

HUDSON_VGA_G

R401 150R1%0402R401 150R1%0402

HUDSON_VGA_B

R403 150R1%0402R403 150R1%0402

Layout: R within 1''

DAC_RSET AUX_VGA_CH_P

AUX_VGA_CH_N AUXCAL

R383 100R1%0402R383 100R1%0402

ML_VGA_HPD

PIN N2,M3,L2,N4,P1,P3,M1,M5 Use as GPIO182 or configure as one of the following: 10-kΩ 5% pull-up resistor to +3.3V_S5. 10-kΩ 5% pull-down resistor.

R587 0R0402R587 0R0402 R588 0R0402R588 0R0402 R573 0R0402R573 0R0402

R400 715R1%0402R400 715R1%0402

SPI_CLK

SPI_DATAOUT SPI_CLK SPI_CS#

HUDSON_VGA_R 22 HUDSON_VGA_G 22 HUDSON_VGA_B 22

HUDSON_VGA_HSYNC 22 HUDSON_VGA_VSYNC 22

HUDSON_VGA_SDAT 22 HUDSON_VGA_SCLK 22

FCH_VDD11_RUN

DP1_TX0P 10 DP1_TX0N 10 DP1_TX1P 10 DP1_TX1N 10 DP1_TX2P 10 DP1_TX2N 10 DP1_TX3P 10 DP1_TX3N 10

C628

X_C10p50N0402

VCC3_SB VCC3_ROM

D52

B140-13-F_SMA-RH

SPI_CS# SPI_WP#_R

MACH@Reserve 0R serial resisters for SI overshoot/undershoot debug

32M

U19

ROM

GBE NOT ENABLED

VCC3_SB

R563 10KR0402R563 10KR0402

1

2

3

4

5

6

7

8

RN8 8P4R-10KR0402RN8 8P4R-10KR0402

SPI ROM & DEBUG HEADER

+

EC57 CD10u16EL5

1 2

C639 C0.1u16Y0402C639 C0.1u16Y0402

R570

R580

1KR0402

R572 0R0402R572 0R0402 R571 X_0R0402R571 X_0R0402

10KR0402

SPI_DATAIN_R SPI_WP# SPI_CLK

SPI_HOLD#

SPI_CS# SPI_HOLD#

VGA HPD

VCC3

R431

R431 X_10KR0402

X_10KR0402

ML_VGA_HPD

R430 X_10KR0402R430 X_10KR0402

R607 0R0402R607 0R0402

GBE_MDIO GBE_COL

GBE_CRS GBE_RXERR GBE_PHY_INTR

U926

1

CS

2

DO

3

WP GND4DI

SPI FLASH-8P_BLACK-RH

R600 X_0R0402R600 X_0R0402

VCC3_ROM

SPI_DEBUG1

1 2 3 4 5 7 8 9

H2X5[10]M-2PITCH_BLACK-RH-2

B

VCC

HLOD

CLK

SPI_DATAOUTSPI_DATAIN

6

VCC_DDR

CE

VCC3_ROMVCC3_ROM

8 7 6 5

SPI_HOLD#_R 17

SPI_CLK

Q59

Q59 SST3904_SOT23

SST3904_SOT23

R441

R441 1KR0402

1KR0402

R601

R601 10KR0402

10KR0402

SPI_HOLD#SPI_DATAIN SPI_DATAOUT

DP1_HPD_VGA_C 10

R409 100KR0402R409 100KR0402

AUX_VGA_CH_P AUX_VGA_CH_N

R407 100KR0402R407 100KR0402

A A

5

4

3

2

C441 C0.1u10X0402C441 C0.1u10X0402 C442 C0.1u10X0402C442 C0.1u10X0402

VCC3

DP1_AUXP_C 10 DP1_AUXN_C 10

R436

R435

1.8KR0402

Title

Size Document Number Rev

Date: Sheet

HUDSON_VGA_R HUDSON_VGA_G HUDSON_VGA_B

MICRO-START INT'L CO.,LTD.

HUDSON SATA/VGA/SPI/HWM

C

K415-Virgo 0B

C764 X_C10p50N0402C764 X_C10p50N0402 C763 X_C10p50N0402C763 X_C10p50N0402 C762 X_C10p50N0402C762 X_C10p50N0402

1

18 36Tuesday, November 22, 2011

of

5

4

3

2

1

HUDSON POWER&DECOUPLING

Connected directly to the power plane with

U600C

4

HUDSON-2

?

U600C

Part 3 of 5

PCI/GPIO I/O

CLKGEN I/O

PCI EXPRESS

MAIN LINK

GBE LAN

SERIAL ATA

USB

USB SS

POWER

VCC3

L29 220L200mA-300-RHL29 220L200mA-300-RH

CORE S0

3.3V_S5 I/O

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8 VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1 VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM_S

VDDIO_AZ_S

L31

220L2A-50

VCC3

D D

mach@???if VGA translater is not used, power rails tied to GND. (VDDPL_33_DAC,VDDPL_33_ML,VDDAN_33_DAC)

mach@Internally generated 1.8V supply for the RGB outputs???

C C

+1.1VDUAL

+1.1VDUAL_D3

R482 0R0805R482 0R0805

Hudson-2 design:Tie to GND (preferred) VDDPL_33_SSUSB_S VDDAN_11_SSUSB_S_[5:1] VDDCR_11_SSUSB_S_[4:1]

B B

LAYOUT: ROUTE THE POWER TRACES 15MILS WIDTH AT LEAST PLACE THE DECOUPING CAPS CLOSE TO FCH ASAP PLACE FB<=1" ,CAPS <=0.2"

VCC3

VDDPL_3.3V FCH_VDDPL_33_MLDAC

L32 220L200mA-300-RHL32 220L200mA-300-RH

C501

C2.2u6.3X50402

VCC3_SB

mach@ CRB DNI???

FCH_VDDPL_33_USB_S VDDPL_3.3V_PCIE

L44 220L200mA-300-RHL44 220L200mA-300-RH

C541

C540

A A

C540

C2.2u6.3X50402

C1u6.3X50402-HF

5

+3.3V_FCH_R

R488 0R0805R488 0R0805

FCH_VDDPL_33_MLDAC

FCH_VDDPL_33_SSUSB_S

FCH_VDD11_RUN

mach@???GbE MAC is not enalbed, power rails tied to GND. (VDDIO_33_GBE_S,VDDIO_GBE_S,VDDCR_11_GBE_S)

VCC3_SB AVDD33_USB

L46

220L2A-50

L42 220L2A-50L42 220L2A-50

FCH_VDD_11_SSUSB_S

C746

C536

C538

C10u6.3X50805

C2.2u6.3X50402

C530

C526

C22u6.3X50805-RH

VDDPL_3.3V

FCH_VDDAN_33_DAC_R FCH_VDDPL_33_USB_S

VDDPL_3.3V_PCIE VDDPL_3.3V_SATA

L60

220L200mA-300-RH

AVDD11_USB

C548

C537

C733

C0.1u10X0402

C1u6.3X50402-HF

VCC3

L26 220L200mA-300-RHL26 220L200mA-300-RH

C1u6.3X50402-HF

C458 X_C2.2u6.3X50402C458 X_C2.2u6.3X50402

C545

C22u6.3X50805-RH

C10u6.3X50805

C731

C0.1u10X0402

L30 220L200mA-300-RHL30 220L200mA-300-RH

C735

C1u6.3X50402-HF

VDDPL_11_DAC FCH_VDD11_RUN

C747

C2.2u6.3X50402

60mils

C740

C1u6.3X50402-HF

20mils

C547

C2.2u6.3X50402

C730

C0.1u10X0402

C732

C1u6.3X50402-HF

15mils 15mils

C738

C1u6.3X50402-HF

C736

C0.1u10X0402

C734

C0.1u10X0402

C737

Pankor

C741

C1u6.3X50402-HF

470 mA

C0.1u10X0402

C484

C452

VDDIO_33_PCIGP_3

AE9

VDDIO_33_PCIGP_4

AD10

VDDIO_33_PCIGP_5

AG7

VDDIO_33_PCIGP_6

AC13

VDDIO_33_PCIGP_7

AB12

VDDIO_33_PCIGP_8

AB13

VDDIO_33_PCIGP_9

AB14

VDDIO_33_PCIGP_10

AB16

VDDPL_33_SYS

H24

47 mA

VDDPL_33_DAC

V22

20 mA

VDDPL_33_ML

U22

12 mA

VDDAN_33_DAC

T22

30 mA

VDDPL_33_SSUSB_S

L18

11 mA

VDDPL_33_USB_S

D7

14 mA

VDDPL_33_PCIE

AH29

11 mA

VDDPL_33_SATA

AG28

12 mA

LDO_CAPLDO_CAP

LDO_CAP

M31

VDDPL_11_DAC

V21

7 mA

VDDAN_11_ML_1

Y22

226 mA

VDDAN_11_ML_2

V23

VDDAN_11_ML_3

V24

VDDAN_11_ML_4

V25

VDDIO_33_GBE_S

AB10

VDDCR_11_GBE_S_1

AB11

VDDCR_11_GBE_S_2

AA11

VDDIO_GBE_S_1

AA9

VDDIO_GBE_S_2

AA10

VDDAN_33_USB_S_1

G7

VDDAN_33_USB_S_2

H8

VDDAN_33_USB_S_3

J8

VDDAN_33_USB_S_4

K8

VDDAN_33_USB_S_5

K9

VDDAN_33_USB_S_6

M9

VDDAN_33_USB_S_7

M10

VDDAN_33_USB_S_8

N9

VDDAN_33_USB_S_9

N10

VDDAN_33_USB_S_10

M12

VDDAN_33_USB_S_11

N12

VDDAN_33_USB_S_12

M11

VDDAN_11_USB_S_1

U12

140 mA

VDDAN_11_USB_S_2

U13

VDDCR_11_USB_S_1

T12

42 mA

VDDCR_11_USB_S_2

T13

VDDAN_11_SSUSB_S_1

P16

282 mA

VDDAN_11_SSUSB_S_2

M14

VDDAN_11_SSUSB_S_3

N14

VDDAN_11_SSUSB_S_4

P13

VDDAN_11_SSUSB_S_5

P14

VDDCR_11_SSUSB_S_1

N16

424 mA

VDDCR_11_SSUSB_S_2

N17

VDDCR_11_SSUSB_S_3

P17

VDDCR_11_SSUSB_S_4

M17

C483

C0.1u10X0402

C2.2u6.3X50402

For low current PLL, analog and IO power rails, a minimum trace width of 15 mils must be used, even if the formula above shows that a thinner trace is acceptable. The 15 mil minimum trace width is required to minimize noise coupling; if necessary, thinner trace can be used but not for more than 300 mils of trace length

It is recommended that each power supply or regulator

C2.2u6.3X50402

on the motherboard be located within 3.0" of its respective load to minimize voltage drop and potential noise issues. To calculate the minimum power delivery trace width, use the formula: Vdroop = I*R, where R=ρ*L/A (ρ = resistivity of material, L = trace length, A = trace cross-sectional area). Vdroop must be < 2.5% of the nominal power rail voltage under maximum current conditions

VDDIO_33_PCIGP_1

AB17

102 mA

VDDIO_33_PCIGP_2

AB18

C741

width ≥ 100 mils with area fill under the FCH.

T14

1414 mA

T17 T20 U16 U18 V14 V17 V20 Y17

H26 J25 K24 L22 M22 N21 N22 P22

AB24 Y21 AE25 AD24 AB23 AA22 AF26 AG27

AA21 Y20 AB21 AB22 AC22 AC21 AA20 AA18 AB20 AC19

N18 L19 M18 V12 V13 Y12 Y13 W11

G24

N20 M20

J24

M8

AA4

340 mA

1088 mA

1337 mA

272 mA

70 mA

5 mA

26 mA

59 mA

5 mA

C727

C1u6.3X50402-HF

C460

C2.2u6.3X50402

C476

C1u6.3X50402-HF

C729

C1u6.3X50402-HF

C543

VDDXL_3.3V

15mils

C1u6.3X50402-HF

20mils

VDDAN_3.3V_HWM

20mils

FCH_VDDAN_33_DAC_R

C493

C494

C0.1u10X0402

C2.2u6.3X50402

VDDPL_3.3V_SATA

C478

C2.2u6.3X50402

FCH_VDD11_RUN

C438

C447

C2.2u6.3X50402

C22u6.3X50805-RH

C754

C1u6.3X50402-HF

C455

C1u6.3X50402-HF

C728

C1u6.3X50402-HF

+3.3VALW_R

20mils

C739

C1u6.3X50402-HF

VDDCR_1.1V

C447

C448

C449

C723

C544

C22u6.3X50805-RH

C1u6.3X50402-HF

VDD_C

C477

C459

R499 0RR499 0R

VDDAN_11_CLK

C1u6.3X50402-HF

C720

C755

C724

C456

C726

VDDPL_1.1V

VDDIO_AZ

R565 0RR565 0R

C599

C597

X_C0.1u10X0402

C1u6.3X50402-HF

VCC3_SB

L37 220L200mA-300-RHL37 220L200mA-300-RH

R381 4.7KR0402R381 4.7KR0402

+12V

FCH_VDD11_RUN

C495

C496

C0.1u10X0402

C2.2u6.3X50402

VDDPL_11_SYS_S Leakage Patch

3

NB_VCC1P1

R390 0R0805R390 0R0805 R397 0R0805R397 0R0805

FCH_VDD11_RUN

C721

C722

C1u6.3X50402-HF

VCC3_SB

FCH_VDDPL_33_SSUSB_S

C521

Pankor

C2.2u6.3X50402

VDDAN_11_CLK

G

S

D

Q35

N-AO3400_SOT23-RH

L55 X_220L200mA-300-RHL55 X_220L200mA-300-RH

Pankor

Power Rails Hudson D3 Hudson D2

NB_VCC1P1

VDDCR_11_[9:1]

VDDAN_11_CLK_[8:1]

VDDAN_11_PCIE_[8:1]

VDDAN_11_SATA_[10:1]

VDDAN_11_ML_[4:1]

VDDPL_11_DAC

VCC3

VDDIO_33_PCIGP_[10:1]

VDDPL_33_SYS

VDDPL_33_DAC

VDDPL_33_ML

VDDPL_33_PCIE

VDDPL_33_SATA

VDDAN_33_DAC

VCC3_SB

VDDIO_33_S_[8:1]

VDDIO_AZ_S

VDDXL_33_S

VDDAN_33_HWM_S

VDDIO_GBE_S[2:1]

VDDIO_33_GBE_S

VDDPL_33_USB_S

VDDAN_33_USB_S_[12:1]

VDDPL_33_SSUSB_S

+1.1VDUAL

VDDCR_11_S_[2:1]

VDDCR_11_GBE_S[2:1]

VDDPL_11_SYS_S

VDDAN_11_USB_S_[2:1]

VDDCR_11_USB_S_[2:1]

VDDAN_11_SSUSB_S_[5:1]

VDDCR_11_SSUSB_S_[4:1]

VCC3_SB

L33 220L200mA-300-RHL33 220L200mA-300-RH

FCH_VDD11_RUN

VDD_C

+1.1VDUAL

VDDPL_11_SYS_S should be tied

C497

to +1.1V_S5 rail if Wake on LAN or USB 3.0 Wake (Hudson-D3 only) is supported; otherwise, it can be tied to +1.1V_S0 rail.

C2.2u6.3X50402

Stuff Q35,L35 for Hudson D3 Stuff L55,L54 for Hudson D2

max

4412 mA

1120 mA 1414 mA

340 mA 1088 mA 1337 mA 226 mA

7 mA

max

102 mA 47 mA 20 mA 12 mA 11 mA 12 mA 30 mA

max

59 mA 26 mA 5 mA 12 mA 145 mA 2 mA 14 mA 470 mA

11 mA 0 mA

max

1293 mA 272 mA 63 mA 70 mA 140 mA 42 mA

282 mA 424 mA

L54 X_220L200mA-300-RHL54 X_220L200mA-300-RH

Pankor

L35 220L200mA-300-RHL35 220L200mA-300-RH

2

319 mA

659 mA

GND

0 mA 0 mA

C506

VDDXL_3.3V

C2.2u6.3X50402

VDDPL_1.1V

C515

C2.2u6.3X50402

U600D

Part 5 of 5

GROUND

C725

C2.2u6.3X50402

C583

C2.2u6.3X50402

C518

C1u6.3X50402-HF

VDDAN_3.3V_HWM

C564

C0.1u10X0402

1

U600D

VSSPL_DAC VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

VDDCR_1.1V

VSS

T25

VSS

T27

VSS

U6

VSS

U14

VSS

U17

VSS

U20

VSS

U21

VSS

U30

VSS

U32

VSS

V11

VSS

V16

VSS

V18

VSS

W4

VSS

W6

VSS

W25

VSS

W28

VSS

Y14

VSS

Y16

VSS

Y18

VSS

AA6

VSS

AA12

VSS

AA13

VSS

AA14

VSS

AA16

VSS

AA17

VSS

AA25

VSS

AA28

VSS

AA30

VSS

AA32

VSS

AB25

VSS

AC6

VSS

AC18

VSS

AC28

VSS

AD27

VSS

AE6

VSS

AE15

VSS

AE21

VSS

AE28

VSS

AF8

VSS

AF12

VSS

AF16

VSS

AF33

VSS

AG30

VSS

AG32

VSS

AH5

VSS

AH11

VSS

AH18

VSS

AH19

VSS

AH21

VSS

AH23

VSS

AH25

VSS

AH27

VSS

AJ18

VSS

AJ28

VSS

AJ29

VSS

AK21

VSS

AK25

VSS

AL18

VSS

AM21

VSS

AM25

VSS

AN1

VSS

AN18

VSS

AN28

VSS

AN33 T21

L28 K33 N28

EFUSE

R6

19 36Tuesday, November 22, 2011

of

HUDSON-2

VSS

A3

VSS

A33

VSS

B7

VSS

B13

VSS

D9

VSS

D13

VSS

E5

VSS

E12

VSS

E16

VSS

E29

VSS

F7

VSS

F9

VSS

F11

VSS

F13

VSS

F16

VSS

F17

VSS

F19

VSS

F23

VSS

F25

VSS

F29

VSS

G6

VSS

G16

VSS

G32

VSS

H12

VSS

H15

VSS

H29

VSS

J6

VSS

J9

VSS

J10

VSS

J13

VSS

J28

VSS

J32

VSS

K7

VSS

K16

VSS

K27

VSS

K28

VSS

L6

VSS

L12

VSS

L13

VSS

L15

VSS

L16

VSS

L21

VSS

M13

VSS

M16

VSS

M21

VSS

M25

VSS

N6

VSS

N11

VSS

N13

VSS

N23

VSS

N24

VSS

P12

VSS

P18

VSS

P20

VSS

P21

VSS

P31

VSS

P33

VSS

R4

VSS

R11

VSS

R25

VSS

R28

VSS

T11

VSS

T16

VSS

T18

VSSAN_HWM

N8

VSSXL

K25

VSSPL_SYS

H25

?

Layout: VSSPL_SYS;VSSAN_HWM CONNECT TO GND WITH A SEPREATED VIA

+1.1VDUAL

R474 0RR474 0R

VCC3_SB

L47 220L200mA-300-RHL47 220L200mA-300-RH

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

MICRO-START INT'L CO.,LTD.

HUDSON POWER&DECOUPLING

K415-Virgo 0B

5

4

3

2

1

FCH REQUIRED STRAPS

D D

C C

RTC_CLK16 PCI_CLK116 PCI_CLK316 PCI_CLK416 LPC_CLK016 LPC_CLK116

FCH_GPIO19917

MACH@All power must be removed after changing S5_PLUS_MODE strap value.

RTCCLK

PULL HIGH

PULL LOW

S5 PLUS MODE DISABLED

DEFAULT

S5 PLUS MODE ENABLED

VCC3_SB

R540

R540 10KR0402

10KR0402

PCI_CLK1

ALLOW PCIE GEN2

DEFAULT

FORCE PCIE GEN1

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAPS

DEFAULT

FCH DEBUG STRAPS

Provided test point access for lab use. FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

TP25TP25 TP50TP50

B B

TP51TP51 TP53TP53 TP52TP52

PCI_AD27 PCI_AD23

PULL HIGH PULL DOWN

USE PCI PLL

DEFAULT

BYPASS PCI PLL

FCH PCIE EEPROM STRAPS

A A

5

TP22TP22 TP23TP23

AD27 AD26 FCH_25M_X1 AD25 AD24 AD23

PCI_AD26

RESERVED

Normal REFCLK Termination

Inverted REFCLK Termination

PREQ3# PGNT#3

4

AD27 16 AD26 16 AD25 16 AD24 16 AD23 16

PCI_AD25 PCI_AD24

USE DEFAULT

DEFAULT DEFAULT

PCIE STRAPS

USE EEPROM PCIE STRAPS

PREQ3# 16 PGNT#3 16

R546

R546 10KR0402

10KR0402

R545

R545 X_10KR0402

X_10KR0402

DISABLE PCI MEM BOOT

DEFAULT

ENABLE PCI MEM BOOT

VCC3 VCC3_SB VCC3_SBVCC3_SBVCC3

R549

R549 X_10KR0402

X_10KR0402

R548

R548 10KR0402

10KR0402

PCI_CLK4

Reserved

Required setting for intergrated CLOCk MODE

DEFAULT

R448

R448 X_10KR0402

X_10KR0402

R564

R564 10KR0402

10KR0402

TP54TP54 TP56TP56 TP60TP60 TP62TP62 TP61TP61

3

R449

R449 10KR0402

10KR0402

LPC_CLK0

EC ENABLED

EC DISABLED

DEFAULT

FCH ICE DEBUG /JTAG TEST PINS

LPC_CLK1

INTERNAL CLOCK GEN ENABLED

INTERNAL CLOCK GEN DISABLED

FCH_TEST1 OC#0 OC#1 OC#2 OC#3

R444

R444 10KR0402

10KR0402

R445

R445 X_10KR0402

X_10KR0402

DEFAULT

FCH_JTAG_TMS FCH_JTAG_TRST# FCH_JTAG_TDI FCH_JTAG_TCK FCH_JTAG_TDO

R471

R471 X_2.2KR0402

X_2.2KR0402

R472

2.2KR0402

GPIO199

LPC ROM

SPI ROM

DEFAULT

TP24TP24

TP17TP17 TP15TP15

TP55TP55 TP58TP58

VCC3_SB

OC#0 17,30 OC#1 17,30 OC#2 17,30 OC#3 17,30

FCH XOR CHAIN TEST

FCH_25M_X2

FCH_TEST0 FCH_TEST2

R586 X_2.2KR0402R586 X_2.2KR0402

2

FANOUT0 18

FCH_25M_X1 16 FCH_25M_X2 16

FCH_TEST0 17 FCH_TEST2 17

1

2

XOR_TEST

X_H1X2M_BLACK-RH

Title

Size Document Number Rev

B

Date: Sheet

FCH XOR CHAIN OUTPUT

FCH XOR CHAIN REF CLOCK

TEST1 TEST0TEST2

0 1 X Enable test mode

FCH_TEST1 17

MICRO-START INT'L CO.,LTD.

HUDSON STRAPS

K415-Virgo 0B

Description

XOR_TEST_X1

SHORTING PLUG

X_JUMP1X2A_RED-RH

6.0

20 36Tuesday, November 22, 2011

1

of

5

4

3

2

1

HDMI CONN,

DP CONOFIGERATION TABLE

INTERFACE

DP

D D

VCC5

C C

U52

DP0_TX2P_HDMI DP0_TX2N_HDMI

DP0_TX0P_HDMI DP0_TX0N_HDMI

B B

U52

1 2

4 5

3

DP0_HDMI_CLK

DP0_HDMI_DATA

10

NC

9

NC

7

NC

6

NC

X_ESD-PDY050003-2510-RH

8

G

C224

C224 C0.1u16Y0402

C0.1u16Y0402

DP0_TX2P_HDMI DP0_TX2N_HDMI

DP0_TX0P_HDMI DP0_TX0N_HDMI

VCC5

C237 X_C0.1u16Y0402C237 X_C0.1u16Y0402

5

3

261

R236 604R1%0402R236 604R1%0402 R233 604R1%0402R233 604R1%0402

R239 604R1%0402R239 604R1%0402 R243 604R1%0402R243 604R1%0402

HDMI_IMPEDANCE

R227 604R1%0402R227 604R1%0402 R231 604R1%0402R231 604R1%0402

R246 604R1%0402R246 604R1%0402 R251 604R1%0402R251 604R1%0402

DS

Q39

Q39 N-2N7002_SOT23

N-2N7002_SOT23

DP0_HPD_HDMI

4

U21

X_CMD ( CM1293A-04SO )

DP0_TX2P DP0_TX2N

DP0_TX1P DP0_TX1N

DP0_TX0P DP0_TX0N

DP0_TX3P DP0_TX3N

DP0_HPD_HDMI

DP0_TXCN_HDMI DP0_TXCP_HDMI

DP0_TX1N_HDMI DP0_TX1P_HDMI

R268 10KR0402R268 10KR0402

R183

R183 100KR0402

100KR0402

DP0_HDMI_CLK DP0_HDMI_DATA

DP0_HPD_HDMI

U53

1 2

4 5

3

R453

X_0R/6

B

C251

X_C0.1u16Y0402

R581 33R0402R581 33R0402 R685 33R0402R685 33R0402

R690 33R0402R690 33R0402

C338

X_C10p50N0402

10

NC

9

NC

7

NC

6

NC

X_ESD-PDY050003-2510-RH

8

VCC3

VCC_DDR

R618

0R/6

CE

Q40

Q40 N-SST3904_SOT23

N-SST3904_SOT23

R210 110R0402R210 110R0402

R269

R269 1KR0402

1KR0402

C340

DP0_TXCN_HDMI DP0_TXCP_HDMI

DP0_TX1N_HDMI DP0_TX1P_HDMI

TRINITYLIANO

DP0_HPD_HDMI_C 10

HDMI

DP0_TX0P10 DP0_TX0N10

DP0_TX1P10 DP0_TX1N10

DP0_TX2P10 DP0_TX2N10

DP0_TX3P10 DP0_TX3N10

C369

X_C10p50N0402

DP0_TX2P DP0_TX0P_HDMI DP0_TX1N_HDMI DP0_TX2N DP0_TX0N_HDMI

DP0_TX0P DP0_TX2P_HDMI DP0_TX0N DP0_TX2N_HDMI

LEVEL SHIFT using I2C Repeater

VCC3

TRINITY

DP0_AUXP_C10

A A

DP0_AUXN_C10

5

DP0_AUXP_C

DP0_AUXN_C

R619

R620

2.2KR0402

VCC3

R624

0R/6

VDD_VGA_HDMI

G2

D1

G1

Q107

S1

Q107 NN-2N7002D

NN-2N7002D

S2

D2

G2

D1

G1

Q108

Q108 NN-2N7002D

NN-2N7002D

S2

D2

4

R454

2.2KR0402

VDD_VGA_HDMI

R455

2.2KR0402

DP0_HDMI_CLK

DP0_HDMI_DATA

3

DP PORT OF FM1

DP0_TX2P_HDMI

R235 X_0RR235 X_0R

DP0_TX2N_HDMI

R232 X_0RR232 X_0R

DP0_TX1P_HDMI

R238 X_0RR238 X_0R

DP0_TX1N_HDMI

R242 X_0RR242 X_0R

DP0_TX0P_HDMI

R229 X_0RR229 X_0R

DP0_TX0N_HDMI

R225 X_0RR225 X_0R

DP0_TXCP_HDMI

R245 X_0RR245 X_0R

DP0_TXCN_HDMI

R250 X_0RR250 X_0R

DP0_HDMI_CLK_CN DP0_HDMI_DATA_CN

DP0_HPD_HDMI_CN

VDD_VGA_HDMI

C454

L12-9008054-M09/L12-9008044-T34/L12-9008054-M09

L12

3

2

4

1

CMC-L12-9008104-RH

L13

3

2

4

1

CMC-L12-9008104-RH

DP0_TX0P_HDMI DP0_TX1N_HDMI

DP0_TX0N_HDMI

DP0_TX2P_HDMI

DP0_TX2N_HDMI

C192

C0.1u16Y0402

X_C10u10Y0805

0123

Ch 2Ch 1Ch 0ChannelClock

R228

X_180R0402-RH

R234

X_180R0402-RH

HDMI

1

D2+

2

D2 Shield

3

D2-

4

D1+

5

D1 Shield

6

D1-

7

D0+

8

D0 Shield

9

D0-

10

CK+

11

CK Shield

12

CK-

13

CE Remote

14

NC

15

DDC CLK

16

DDC DATA

17

GND

18

+5V

19

HP DET

HDMI19P_BLACK-HF

N5Y-19M0231-L06

DP0_TX1N DP0_TX1P

DP0_TX3N DP0_TX3P

21

SHELL1

MEC1

20

SHELL2

L14

3 4

CMC-L12-9008104-RH

L15

3 4

CMC-L12-9008104-RH

DP0_TX1P_HDMI

DP0_TXCN_HDMI

DP0_TXCP_HDMI

2

DP0_TX1P_HDMI

1

DP0_TXCN_HDMI

2

DP0_TXCP_HDMI

1

HDMI footprint(HDMI_D19_4)_Colay

DP0_TX2P_HDMI DP0_TX2N_HDMI

DP0_TX1P_HDMI DP0_TX1N_HDMI

DP0_TX0P_HDMI DP0_TX0N_HDMI

DP0_TXCP_HDMI DP0_TXCN_HDMI

DP0_HDMI_CLK_CN DP0_HDMI_DATA_CN

VDD_VGA_HDMI

DP0_HPD_HDMI_CN

R241

X_180R0402-RH

R249

X_180R0402-RH

2

HDMI_1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

Title

SWITCH&DP/HDMI CONN.

Size Document Number Rev

C

Date: Sheet

21

SHELL1

D2+

D2+ D2 Shield

D2 Shield D2-

D2-

23

D1+

D1+ D1 Shield

D1 Shield D1-

D1D0+

D0+ D0 Shield

D0 Shield

MEC1

D0-

D0CK+

CK+ CK Shield

CK Shield CK-

CKCE Remote

CE Remote NC

NC DDC CLK

DDC CLK DDC DATA

DDC DATA

22

GND

GND +5V

+5V HP DET

HP DET

20

SHELL2

X_HDMI_D19_6

MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

VCC5 VCC5

1

C222

C0.1u16Y0402

C271

C0.1u16Y0402

21 36Tuesday, November 22, 2011

of

8

7

6

5

4

3

2

1

VGA CONNECTOR

D D

R932-R934 CLOSE TO CRT CONNECTOR, THE TRACE IMPEDANCE BETWEEN NB AND 150OHM RESISTOR SHOULD BE 37OHM+/-15%, THE TRACE IMPEDANCE BETWEEN THE 2 150OHM

RESISTOR SHOULD BE 50 OHM +/-15%, THE IMPEDANCE BETWEEN THE 2ND RESISTOR

TO THE CONNECTOR SHOULD BE 75OHM+/-15%

mach@The value of L,C refer to demo board,maybe adjusted for test Layout:PLACE L 90 DEGREE

R258 4.7KR0402R258 4.7KR0402

+12V

G

S

D

VCC5

C C

D

Q34

N-APM2308AC-TRL_SOT23-3-RH

FS1

1 2

F-MICROSMD110

VDD_VGA_HDMI

C201

C10u10Y0805

C207

C0.1u16Y0402

HUDSON_VGA_R18

R276

R276 150R1%0402

150R1%0402

C276

X_C1p50N0402-RH

HUDSON_VGA_G18

R273

R273 150R1%0402

150R1%0402

C264

X_C1p50N0402-RH

HUDSON_VGA_B18

R271

R281

R279

4.7KR0402

HUDSON_VGA_SDAT18

HUDSON_VGA_SCLK18

R278R278

R282R282

DDCDATA_5V

DDCCLK_5V

R271 150R1%0402

150R1%0402

C258

X_C1p50N0402-RH

FROM EACH OTHER

L200RL20

0R

L190RL19

0R

L160RL16

0R

VGA_R

VGA_G

VGA_B

L21

68n300mA

C275

X_C3.3p50N0402

L18

68n300mA

C267

X_C3.3p50N0402

L17

68n300mA

C257

X_C3.3p50N0402

CLOSE TO VGA Connector

C274

C10p25N0402-RH-2

C266

C10p25N0402-RH-2

C256

C10p25N0402-RH-2

VDD_VGA_HDMI VDD_VGA_HDMI VCC5 VCC5

VCC5

D21

BAV99-7-F_SOT23-LF

Y

VCC5

D20

BAV99-7-F_SOT23-LF

Y

VCC5

D19

BAV99-7-F_SOT23-LF

Y

C269 C0.1u16Y0402C269 C0.1u16Y0402

X

Z

C262 C0.1u16Y0402C262 C0.1u16Y0402

X

Z

C249 C0.1u16Y0402C249 C0.1u16Y0402C267

X

Z

VDD_VGA_HDMI

PLACE ESD PROTECTION DIODES

1. CLOSE TO CONNECTOR PINS

2. DIRECTLY ON SIGNAL TRACES

3. +5V & GND TRACE TO DIODE SHOULDBE LESS THAN 100MILS AND 20MILS WIDE

4. THE ESD DIODE SHOULD BE THE FIRST DEVICE

FROM CONNECTOR

BAV99

Y

D24

C284

Z

X

C0.1u16Y0402

DDCCLK_CONN VSYNC_CONN HSYNC_CONN DDCDATA_CONN

C241

C0.1u16Y0402

3

Y

D18

BAV99

Z

X

C250

X_C100P50N0402

Y

D23

C0.1u16Y0402

4

D23

BAV99

Z

X

C297

VCC5

C228 C0.1u16Y0402C228 C0.1u16Y0402

53

1

HUDSON_VGA_VSYNC18

B B

HUDSON_VGA_HSYNC18

A A

8

2

U18

VCC5

53

1 2

U18

C239 C0.1u16Y0402C239 C0.1u16Y0402

U20

AHCT1G126GV_SOT23-5-RH

7

4

VSYNC_5V

C219

C219 X_C100P50N0402

X_C100P50N0402

HSYNC_5V

C234

C234 X_C100P50N0402

X_C100P50N0402

6

DDCCLK_5V

R283 33R0402R283 33R0402

VSYNC_5V

R263 27R0402R263 27R0402

HSYNC_5V

R264 27R0402R264 27R0402

DDCDATA_5V

R277 33R0402R277 33R0402

5

C279

Y

D17

BAV99

C283

D17

C218

Z

C229

X

C0.1u16Y0402

15 14 13 12 11

VGA

DSUB-VGAF_BLUE-RH-2

DSUB-VGAF_BLUE-RH-2 5 10 4 9 3 8 2 7 1 6

C208

C208 C0.1u16Y0402

C0.1u16Y0402

BLUE_CONN GREEN_CONN RED_CONN

16 17

X_C100P50N0402

X_C18P50N0402

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

2

MICRO-START INT'L CO.,LTD.

TRAVIS & VGA CONN.

K415-Virgo 0B

22 36Tuesday, November 22, 2011

1

of

5

iSATA CONNECTOR

Multiple eSATA function

SATA_RX0+ ST_RX0

C609 C0.01U16X0402C609 C0.01U16X0402

SATA_RX0+18

SATA_RX0-

SATA_RX0-18

SATA_TX0-

SATA_TX0-18

SATA_TX0+

SATA_TX0+18

D D

SATA_RX1+

SATA_RX1+18 SATA_RX3+18 SATA_RX1-18

SATA_TX1-

SATA_TX1-18

SATA_TX1+

SATA_TX1+18

1 2

C604 C0.01U16X0402C604 C0.01U16X0402

1 2

C590 C0.01U16X0402C590 C0.01U16X0402

1 2

C586 C0.01U16X0402C586 C0.01U16X0402

1 2

C522 C0.01U16X0402C522 C0.01U16X0402

1 2

C519 C0.01U16X0402C519 C0.01U16X0402

1 2

C516 C0.01U16X0402C516 C0.01U16X0402

1 2

C510 C0.01U16X0402C510 C0.01U16X0402

1 2

N5N-07M1901-L06

Layout:For Gen 3.0,trace length within 3''

SATA1

X1

7

RX+

6

RX-

5 4 3 2 1

X2

SATA7PM_RED-ST-RH-1

SATA2

X1

7 6 5 4 3 2 1

X2

SATA7PM_RED-ST-RH-1

SERIAL_ATA_9P

RX-

GNDGND

TX-

TX+

GND

X2

X1

RX+

RX-

GNDGND

TX-

TX+

GND

X2

ST_RX#0 ST_TX#0

ST_RX#1SATA_RX1ST_TX#1

ST_TX1

4

SATA3

X1

SATA_RX2+

C608 C0.01U16X0402C608 C0.01U16X0402

SATA_RX2+18 SATA_RX2-18

SATA_TX2-18 SATA_TX2+18

SATA_RX3-18

SATA_TX3+18

SATA_RX2SATA_TX2-

SATA_TX2+

SATA_RX3+ SATA_RX3-

SATA_TX3-

SATA_TX3-18

SATA_TX3+

1 2

C601 C0.01U16X0402C601 C0.01U16X0402

1 2

C592 C0.01U16X0402C592 C0.01U16X0402

1 2

C588 C0.01U16X0402C588 C0.01U16X0402

1 2

C523 C0.01U16X0402C523 C0.01U16X0402

1 2

C520 C0.01U16X0402C520 C0.01U16X0402

1 2

C513 C0.01U16X0402C513 C0.01U16X0402

1 2

C507 C0.01U16X0402C507 C0.01U16X0402

1 2

ST_RX2 ST_RX#2

ST_TX#2 ST_TX2ST_TX0

ST_RX3ST_RX1 ST_RX#3

ST_TX#3 ST_TX3

7 6 5

GNDGND

4 3 2

GND

1

X2

SATA7PM_RED-ST-RH-1

SATA4

X1

7 6 5

GNDGND

4 3 2

GND

1

X2

SATA7PM_RED-ST-RH-1

3

eSATA Conn. WO re-driver

X1

RX+

RX-

TX-

TX+

X2

X1

RX+

RX-

TX-

TX+

X2

ST_TX4 ST_TX#4

ST_RX#4 ST_RX4

SATA_RX4+18 SATA_RX4-18

SATA_TX4-18

SATA_TX4+18

U33

1 2

4 5

3

C512 C0.01U16X0402C512 C0.01U16X0402

1 2

C517 C0.01U16X0402C517 C0.01U16X0402

1 2

C524 C0.01U16X0402C524 C0.01U16X0402

1 2

C527 C0.01U16X0402C527 C0.01U16X0402

1 2

ST_TX4

10

NC

ST_TX#4

9

NC

ST_RX#4

7

NC

ST_RX4

6

NC

X_ESD-PDY050003-2510-RH

8

FCH_GPO20017

R617

FCH_GPO200

1KR0402

2

Layout:For onboard eSATA conn. without redriver IC,trace length within 6''

B

ST_RX4 ST_RX#4

ST_TX#4 ST_TX4

VCC5_SB

R604

4.7KR0402

CE

Q96

Q96 N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

X1

7 6 5 4 3 2 1

X2

eSATA

X1

RX-

GNDGND

TX-

GND

X2

SATA_7P-4

1KR0402

RX+

TX+

40mils

5VDIMM VCC5_SSD

C808

C809

C809 C0.1u16X0402

C0.1u16X0402

C808 C0.1u16X0402

C0.1u16X0402

G

Q95

P-P06P03LCG_SOT89-3-RH

D S

C805

C805 C10u16X50805-HF

C10u16X50805-HF

R656

C807

C807 C0.1u16X0402

C0.1u16X0402

1

SSD_POWER

1 2 3 4 5 6

BH1X6H-2PITCH_WHITE-RH

CPUFAN/SYSTEMFAN/POWERFA

C C

CPUFAN_PWM1 SYSFAN_PWM1 PWRFAN_PWM1

Co-lay3PINSMARTFANcircui

B B

t

+12V +12V

R707

U63A

X_8.2KR0402

1

X_LM358D_SOIC8

R710 X_0R0805R710 X_0R0805

PWRFAN_PWM1

R712 X_15K/4R712 X_15K/4

3

+

2

-

4 8

R709 X_10KR1%0402R709 X_10KR1%0402

R711

X_2KR1%0402

+12V

U63B

A A

5 6

U63B

+

-

4 8

7

X_LM358D_SOIC8

5

C64 X_C0.1u16Y0402C64 X_C0.1u16Y0402 C647 X_C0.1u16Y0402C647 X_C0.1u16Y0402 C678 X_C0.1u16Y0402C678 X_C0.1u16Y0402

R708

R708 X_0R1206

X_0R1206

X_P-P06P03LDG_TO252-RH

G

Q91

D S

C676

X_C0.1u16Y0402

AUX_12V

4

N

VCC5

R48

CPUFAN_PWM25

CPUFAN_PWM

VCC5

D

4.7KR0402

D

G

S

R668

4.7KR0402

Q52

Q52 N-2N7002_SOT23

N-2N7002_SOT23

VCC5

G

R669

D

S

VCC3

R40

4.7KR0402

4.7KR0402 X_4.7KR0402

X_4.7KR0402

Q60

Q60 N-2N7002_SOT23

N-2N7002_SOT23

R16 100R0402R16 100R0402

VCC3

R329

R396

VCC5

R331

4.7KR0402

SYSFAN_PWM

SYSFAN_PWM25

4.7KR0402

VCC5

G

D

S

R395

4.7KR0402

Q48

Q48 N-2N7002_SOT23

N-2N7002_SOT23

D

Q55

G

S

N-2N7002_SOT23

4.7KR0402

4.7KR0402 X_4.7KR0402

X_4.7KR0402

R332 100R0402R332 100R0402

VCC5 VCC3

R705

R704

VCC5

R353

4.7KR0402

PWRFAN_PWM25

4.7KR0402

3

VCC5

G

D

S

R702

4.7KR0402

Q89

Q89 N-2N7002_SOT23

N-2N7002_SOT23

4.7KR0402

D

Q90

G

S

N-2N7002_SOT23

X_4.7KR0402

R703 100R0402R703 100R0402

VCC3

VCC5

D2

D1

X_1N4148W-FD2X_1N4148W-F

X_1N4148W-FD1X_1N4148W-F

VCC3

VCC5VCC5

D26

D25

X_1N4148W-F

VCC3VCC5

D30

D31

X_1N4148W-F

2

CPU FAN

+12V

D4 1N4148W-F_SOD123-RHD4 1N4148W-F_SOD123-RH R39 4.7KR0402R39 4.7KR0402

CPUFAN_PWM1

C39

C39 C0.1u16Y0402

C0.1u16Y0402

+

12

EC2

EC2 CD100u16EL5-RH

CD100u16EL5-RH

SYSTEM FAN

+12V

D27 1N4148W-F_SOD123-RHD27 1N4148W-F_SOD123-RH R342 4.7KR0402R342 4.7KR0402

SYSFAN_PWM1

C356

C356 C0.1u16Y0402

C0.1u16Y0402

+

12

EC30

EC30 CD100u16EL5-RH

CD100u16EL5-RH

POWER FAN

+12V

D75 1N4148W-F_SOD123-RHD75 1N4148W-F_SOD123-RH R701 4.7KR0402R701 4.7KR0402

PWRFAN_PWM1

R706

R706 0R1206

0R1206

AUX_12VAUX_12V

C643 C0.1u16Y0402C643 C0.1u16Y0402

+

12

EC90

EC90 CD100u16EL5-RH

CD100u16EL5-RH

0 to +3 V amplitude fan

4 3 2 1

1

tachometer input.

CPUFAN_TAC 25

R37

R37 10KR0402

10KR0402

SYSFAN_TAC 25

R344

R344 10KR0402

10KR0402

PWRFAN_TAC 25

R349

R349 10KR0402

10KR0402

N32-1030451-H06 3pin fan

23 36Tuesday, November 22, 2011

of

R38 27KR0402R38 27KR0402

CPU_FAN

BH1X4B_brown-RH

R343 27KR0402R343 27KR0402

SYS_FAN

BH1X4B_white-RH

R352 27KR0402R352 27KR0402

PWR_FAN

BH1X4B_white-RH

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

MICRO-START INT'L CO.,LTD.

SATA//eSATA/PS2/ FAN

K415-Virgo 0B

5

RTL8111F-VB-CG

LAN_EESK/LED1_R

R6660RR666 0R

VDD33

VDD10

R345 2.49KST/4R345 2.49KST/4

D D

VDD10

VDD33

C C

R507 place close to pin 46 as possible

ROUTE 100 OHM DIFF

TR_D0+ TR_D0-

TR_D1+ TR_D1-

TR_D2+ TR_D2-

TR_D3+ TR_D3-

RTL8111F-VB-CG-RH

1 2 3 4 5 6 7 8

9 10 11 12

U28

MDIP0 MDIN0 AVDD10 MDIP1 MDIN1 AVDD10(NC) MDIP2(NC) MDIN2(NC) AVDD10(NC) MDIP3(NC) MDIN3(NC) AVDD33(NC)

AVDD3348AVDD33

DVDD10

13

VDD10

RSET

46

47

45

RSET

AVDD10

SMBCLK(NC)14SMBDATA(NC)15CLKREQB

16

LAN_SDATA

CLK_LANI

CLK_LAN2

LAN_LED0_LINK100#

40

42

41

43

AVDD33

CKXTAL244CKXTAL1

DVDD10(NC)

HSIP17HSIN18REFCLK_P19REFCLK_N20EVDD1021HSOP22HSON

EVDD10

LAN_EESK/LED1

LAN_GPO

38

39

37

LED0

DVDD33

GPO/SMBALERT

24

23

3.3v Power on rise time : 1~100ms.

MAX: 163mA

+LAN_3VSB

L24 X_220L2A-50-RHL24 X_220L2A-50-RH

CP4CP4

B B

width>60mil

REGOUT_VDD10

CHOKE8

1 2

CH-4.7u0.85A170mS-HF

CHOKE12 close to Pin 36 within 0.2''

C763,C868 close to CHOKE12 within 0.2''

8105E POWER Consumption

A A

10 M Idle/TxRx

100 M Idle/TxRx

S0 ALDPS

27 39 42 47 48 12

C345

C529

C10u6.3X50805

C351

C381

C0.1u16X0402

C10u6.3X50805

3.3V mW

14/75

43/66

3.2

5

C361

C354

C0.1u16Y0402

C361

C0.1u16Y0402

C743

C0.1u16Y0402

C359

C0.1u16Y0402

C364

29 45 41 6 9313

C360

C744

C368

C0.1u16Y0402

46/248

142/218

11 12/66

Place close to pin 31,37,40

LAN_LED0_LINK100# LAN_EESK/LED1 LAN_EEDO/LED3

LED1/EESK

GND

C0.1u16Y0402

36

REGOUT

35

VDDREG

34

VDDREG

33

ENSWREG

LED3/EEDO

LANWAKEB

ISOLATEB

Pin49: 9 via from top layer to GND layer and make the via at the center of IC.

LAN_RXN LAN_RXP

8105E: unstuff

8111E/F: stuff

C380

C0.1u16Y0402

EECS

DVDD10 DVDD33 PERSTB

EEDI

GND

VDD33

C370

LAN_EEDI

32

LAN_EEDO/LED3

31

LAN_EECS

30 29 28 27

LAN_ISOLATE#

26

PCIE_RST#

25

49

C384 C0.1u10X0402C384 C0.1u10X0402 C383 C0.1u10X0402C383 C0.1u10X0402

C358

C366

C0.1u16Y0402

8111E POWER Consumption

10 M Idle/TxRx

100 M Idle/TxRx

Giga Idle/TxRx

ALDPS

4

C353 X_C1000P50X0402C353 X_C1000P50X0402 C362 X_C1000P50X0402C362 X_C1000P50X0402 C367 X_C1000P50X0402C367 X_C1000P50X0402

REGOUT_VDD10

VDD33 VDD33

R347 10KR0402R347 10KR0402 R667 0RR667 0R R350 10KR0402R350 10KR0402

VDD10 VDD33

C378

X_C680p50N0402

PE_LAN_CLK# PE_LAN_CLK

VDD10

8105E: unstuff

8111E/F: stuff

C0.1u16Y0402

4

AVDD33_REG

PE_WAKE# 17,25,31,32,33

LAN_RXC_N 8 LAN_RXC_P 8 PE_LAN_CLK# 16 PE_LAN_CLK 16 LAN_TXC_N 8 LAN_TXC_P 8

VDD33

VDD10

CLK_LAN2

CLK_LANI

VDD33

ENSWREG:3.3V-Enable SW

LAN_EEDO/LED3_R

MACH@Reserve PU at FCH side

PCIE_RST# 16,31,32,33

width>40mil WITHIN 0.2'' OF PIN 34,35

C346

C4.7u6.3X5

WITHIN 0.2'' OF PIN21

R361 0RR361 0R

C385

3.3V mW

31/44

135/163 452/538

4

40/218

102/145

13

C375

C0.1u16Y0402

C1u10X7R

VDD33

EVDD10

C382

C0.1u16Y0402

R330

R330 X_1MR

X_1MR

1 2

LAN_ISOLATE#

3

C341 C27p50N0402-RHC341 C27p50N0402-RH

Y1

Y1 25MHZ18P_D-4

25MHZ18P_D-4

C347 C27p50N0402-RHC347 C27p50N0402-RH

VCC3

R359

R359 1KR0402

1KR0402

R358

R358 15K/4

15K/4

N58-22F0431-U30(10/100)

3

TR_D3TR_D2TR_D1TR_D0-

TR_D3+ TR_D2+ TR_D1+ TR_D0+

R713 0RR713 0R R714 0RR714 0R R715 0RR715 0R R716 0RR716 0R

R717 0RR717 0R R718 0RR718 0R R719 0RR719 0R R720 0RR720 0R

2

USE Efuse/BIOS PATCH WITHOUT ASF FUNCTION

LAN_EECS LAN_EESK/LED1_R LAN_EEDI LAN_EEDO/LED3_R

U60

TR_D3-_CN TR_D2-_CN TR_D1-_CN TR_D0-_CN

TR_D3+_CN TR_D2+_CN TR_D1+_CN TR_D0+_CN

TR_D2+_CN TR_D2-_CN

TR_D3+_CN

U60

1 2

4 5

3

LED3_ACT LED0_LINK100# LED1_LINK1000#

The center-tap of transformer must be tied together

and connect to GND with 0.01 u cap.

R291

R291 0R0402

0R0402

8111E/F: stuff

8105E: unstuff

N58-22F0851-F02/N58-22F0851-I60 30u

N58-22F0951-I60

Link

Active

1000 Green

100

10

19

20

21

22

Green

2

TR_D2+_CN

10

NC

TR_D2-_CN

9

NC

TR_D3+_CN

7

NC

TR_D3-_CNTR_D3-_CN

6

NC

X_ESD-PDY050003-2510-RH

8

12

D64

ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

8111E: unstuff

8111E/F: stuff

R428 X_0R0402R428 X_0R0402

Yellow Blinking Orange Green None

Yellow

Orange

VDD33

12

D66

D65

C320

C320 X_C0.01U16X0402

X_C0.01U16X0402

1 2

8111E: unstuff

8105E: stuff

VDD33

10/100-LanGiga-Lan

N58-22F0431-U30

Link

Yellow Blinking

Active 100

None

10

19

20

Yellow

21

22

Green

1

U49

1

CS

VCC

2

SK

DC

3

DI

ORG

4

DO

GND

X_HT93LC46-8 SOP-A-RH

AVL PN:M33-93C46F3-S10

R341 1KR0402R341 1KR0402

R433 X_1KR0402R433 X_1KR0402 R360 10KR0402R360 10KR0402

8111E/F: stuff

8105E: unstuff

LAN_CONN_TCT LAN-CONN_RCT/GND

LAN_LED0_LINK100#

LAN_EESK/LED1_R

LAN_GPO

LAN_SDATA

TR_D0+_CN TR_D0-_CN

TR_D1+_CN

TR_D1-_CN

VDD33_R LAN_CONN_TCT LAN-CONN_RCT/GND

8111E/F: 220R

8105E: 510R

R348 220RR348 220R

TR_D3-_CN TR_D2-_CN TR_D1-_CN TR_D0-_CN

TR_D3+_CN TR_D2+_CN TR_D1+_CN TR_D0+_CN

R616 75R0402R616 75R0402

8111E/F: 220R

8105E: unstuff

R340 220RR340 220R

R425 X_510RR425 X_510R

8111E: unstuff

8105E: 510R

only support LED0+LED1/LED1+LED3 dual color LED combinations when using EEPROM

Title

LAN-RTL8111F-VB-CG

Size Document Number Rev

C

Date: Sheet

VDD33

8 7 6 5

1 2

4 5

K415-Virgo 0B

C372

X_C0.1u16Y0402

GPO: 1: Link up 0: Link down

U61

3

TP11TP11

TP12TP12

TP16TP16

TP13TP13 TP14TP14

TR_D0+_CN

10

NC

TR_D0-_CN

9

NC

TR_D1+_CN

7

NC

TR_D1-_CN

6

NC

X_ESD-PDY050003-2510-RH

8

12

D67

D68

ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

LED3_ACTLAN_EEDO/LED3_R

4-

TD-

9

3-

10

2-

11

1-

12

PWR

13

GND

14

4+

15

169

TD+

3+

16

2+

17

1+

18

LED0_LINK100#

LED1_LINK1000#

MICRO-START INT'L CO.,LTD.

1

12

D69

20 22

VDD33

PE_LAN_CLK#

VDD33

R477

R477 75R

75R

VDD33_R

21

USB_LANB

USB_LANB RJ45_USBX2_TX-RH-3

RJ45_USBX2_TX-RH-3

19

VDD10

PCIE_RST# PE_LAN_CLK

24 36Tuesday, November 22, 2011

of

5

C43 X_C0.1u16Y0402C43 X_C0.1u16Y0402 C120 C22p50N0402C120 C22p50N0402

C129 C22p50N0402C129 C22p50N0402 C122 15p50N0402C122 15p50N0402

C177 X_C0.1u16Y0402C177 X_C0.1u16Y0402 C178 X_C0.1u16Y0402C178 X_C0.1u16Y0402

SERIRQ16

LPC_AD[3..0]16

D D

A_RST#16

PCI_CLK_SIO16 LPC_FRAME#16

SIO_48M_CLK16

PWRFAN_TAC23

PWRFAN_PWM23

CPUFAN_TAC23

CPUFAN_PWM23

SYSFAN_TAC23

SYSFAN_PWM23

R176 0R0402R176 0R0402

C147 C4.7u6.3X5C147 C4.7u6.3X5

C C

B B

PCI_CLK_DEBUG16

SDATA012,17

SCLK012,17

17

SIO_GP25_SMI#

R128 0R0402R128 0R0402 R122 0R0402R122 0R0402

A_RST# PCI_CLK_SIO

LPC_FRAME# SIO_48M_CLK

SIO_SDATA0 SIO_SCLK0

R256 0R0402R256 0R0402

LPC_AD0

R257 0R0402R257 0R0402

LPC_AD1

R261 0R0402R261 0R0402

LPC_AD2

R265 0R0402R265 0R0402

LPC_AD3

R270 0R0402R270 0R0402

A_RST# PCI_CLK_SIO SERIRQ_SIO LPC_FRAME#

SIO_48M_CLK LPC_AD0_SIO LPC_AD1_SIO LPC_AD2_SIO LPC_AD3_SIO

VIN_VDDP/VDDRSIO_VLDT_EN

VIN_VDIMM VIN_CPUCORE SIO_VREF VR_TEMP_DA EXT_SYS_TEMP

SIO_SDATA0 SIO_SCLK0

RIA# DCDA#

SOUTA

SINA

DTRA# RTSA#

DSRA# CTSA#

SIO_WAKE

SIO_GP25_SMI#

LPC Debug

LPC_DEBUG

1 2

A_RST#

3

5

LPC_AD1 LPC_AD2

9

LPC_AD3

11

LPC_FRAME#

13

BH2X7[10]-2PITCH_BLACK-RH-1

Pull High &Reserved

SERIRQ_SIOSERIRQ LPC_AD0_SIO LPC_AD1_SIO LPC_AD2_SIO LPC_AD3_SIO LPC_FRAME#

U914

10

LRESET#

2

PCICLK

3

SERIRQ

9

LFRAME#

1

IOCLK

7

LAD0

6

LAD1

5

LAD2

4

LAD3

64

GP04/AUXFANIN0

59

GP00/AUXFANOUT0

60

CPUFANIN

61

CPUFANOUT

62

SYSFANIN

63

SYSFANOUT

48

VIN2/VLDT

49

VDIMM/VIN3

51

CPUVCORE

52

VREF

53

VIN4/AUXTIN0

54

CPUTIN

22

MSDA/SDA/GP42/BEEP

23

MSCL/SCL/GP41

20

GP87/RIA#

19

GP86/DCDA#

18

GP85/SOUTA(TEST MODE1)

17

GP84/SINA

16

(24M_48M_SEL)DTRA#/GP83

15

(2E_4E_SEL)RTSA#/GP82

14

DSRA#/GP81

13

CTSA#/GP80

43

CIRRX/GP24/IRRX1

44

GP25/CIRTX1/IRTX1(AMDPWR_EN)

NCT5533D-RH

VCC5

VCC3

4

LPC_ID0LPC_AD0

6 87

12 14

R45

R45 10KR0402

10KR0402

VCC3

R1024.7KR0402 R1024.7KR0402

R98X_4.7KR0402 R98X_4.7KR0402

R99X_4.7KR0402 R99X_4.7KR0402 R100X_4.7KR0402 R100X_4.7KR0402 R101X_4.7KR0402 R101X_4.7KR0402 R108X_4.7KR0402 R108X_4.7KR0402

PSON#/AMD_PSON#

PWROK/AMD_PWROK

RSTOUT0#/GP74 RSTOUT1#/GP75

GP56/VCORE_EN

GP57/VLDT_EN

GP54/SLP_SUS#

DEEP_S5/3VSBSW

Wakeupevent

C136 X_C0.01u16X0402C136 X_C0.01u16X0402

SIO_WAKE

VCC3

KBRST#

GA20M KDAT/GP20 KCLK/GP21 MDAT/GP22 MCLK/GP23

PSIN#

PSOUT#

RSMRST#

SLP_S3# SLP_S5#

ATXPGD

GP26/TSIC

PECI/TSID

DPWROK#

PCHVSB

AVCC

3VSB

VBAT

CPUD-/AGND



R699 0R0402R699 0R0402

4

R132 X_10KR0402R132 X_10KR0402 R130 X_10KR0402R130 X_10KR0402

12 11 27 26 25 24

29 28 47 31 38 36 30

SIO_AMD_PWRGD

37 35 34

56 58 57

VTT

SIO_VCORE_EN

40

SIO_GP57

39 33 41

PCHVSB_DETECT

45

DEEP_S5

32

8

VCC

50

21 46

SIO_HWM_AGND

55

42

VSS

VCC3_ALW

R194

X_4.7KR0402

B

Q88

Q88 X_N-MMBT3904_NL_SOT23

X_N-MMBT3904_NL_SOT23

C E

A20GATE KBRST#

5VDIMM

R65

X_4.7KR0402

KBRST#

A20GATE SIO_GP20 SIO_GP21 SIO_GP22 SIO_GP23

PSOUT#

IO_RSMRST#

ATX_PSON#

PWR_LED SIO_VDUAL_EN

SIO_TSI_CLK SIO_TSI_DAT

R272 10K_R0402R272 10K_R0402

SIO_AVCC

16 mil

VCC3_ALW

R195

10KR0402

VCC3_SB

USB_EN 30

KBRST# 17 A20GATE 17

PSIN# 34 PSOUT# 17 IO_RSMRST# 17

SLP_S3# 17,26,27

SLP_S5# 17,26,27,30

ATX_PWROK 7,26,27,33,34 ATX_PSON# 34

PWR_LED 34 SIO_VDUAL_EN 26

R164 0R0402R164 0R0402 R165 0R0402R165 0R0402

SIO_GP57 26

USB_EN

R346 4.7KR0402R346 4.7KR0402

R105 0R0402R105 0R0402

VBAT_IO

C127

X_C1u10X

PE_WAKE# 17,24,31,32,33

VCC3_ALW

R4 4.7KR0402R4 4.7KR0402 R416 4.7KR0402R416 4.7KR0402

2 4 6 8

R8 1KR1%0402R8 1KR1%0402

APU_SIC 10 APU_SID 10

VCCP

SYS5VSB_OFF 26

D13

1N4148W

R432 10KR0402R432 10KR0402

IO_RSMRST#

SIO_VDUAL_EN

SIO_GP20

1

SIO_GP21

3

SIO_GP22

5

SIO_GP23

7

R158

VBAT

1KR0402

VCC3

L7 600L500mA-300_0805L7 600L500mA-300_0805

SIO_HWM_AGND

SIO_GP57

PSOUT#

C498

C180p50N0402

C134 C0.1u10X0402C134 C0.1u10X0402

C135 C10u6.3X50805C135 C10u6.3X50805

C54 C10u6.3X50805C54 C10u6.3X50805

C117 C0.1u10X0402C117 C0.1u10X0402

VCC_DDR

C146

C10u6.3X50805

L8

600L500mA-300_0805

3

TEMP SENSOR

External Thermal diode Mode

CHASSIS_ID217 CHASSIS_ID117

Current mode

MB_ID117 MB_ID017

RN1

8P4R-2.2KR0402

VCC3

VCC3_ALW

Voltage Divider

9 voltage sensors (including VCC, AVCC, VSB, VBAT)

R178 X_10KR1%0402R178 X_10KR1%0402

VCCP

C138

C0.1u10X0402

VIN 0~2.048V

SIO_AVCC

R177 X_10KR1%0402R177 X_10KR1%0402

R354 4.7KR0402R354 4.7KR0402

R355 4.7KR0402R355 4.7KR0402

SERIAL PORT 1

VCC5

C653

C0.1u16Y0402

NRIA NCTSA# NDSRA# NSINA NDCDA#

RTSA# DTRA# SOUTA

2

VR_TEMP_DA

SIO_HWM_AGND VR_TEMP_DC

CHASSIS_ID2 CHASSIS_ID1

C2200p50X0402

MB_ID1 MB_ID0

C502

CP22 X_CPCP22 X_CP

CHASSIS_ID1

CHASSIS_ID2

MB_ID0

MB_ID1

CHASSIS_ID1 CHASSIS_ID2

SIO AMD POWER SEQUENCE

VCC3

The timing delay between each step is 10~15 mS

PIN 38 SLP_S5# PIN 31 SLP_S3# PIN 30 PSON# DESCRETE VDIMM_EN CIRCUIT PIN 49 VDIMM_IN PIN 40 VCORE_EN

SIO_VCORE_EN

PIN 51 VCORE_IN

VIN_CPUCORE

SIO_HWM_AGND

VIN_VDIMM

SIO_HWM_AGND

20

2 3 4 7 9

16 15 13 11

U48

VCC RA1 RA2 RA3 RA4 RA5

DA1 DA2 DA3 GND

GD75232_SSOP20

PIN 39 VLDT_EN

SIO_VLDT_EN

PIN 48 VLDT_IN

PIN 37 AMD_PWRGD

SIO_AMD_PWRGD

SIO_PWRGD INCLUDES TRADITIONAL VCC3 POWER READY CONDITION

1

VDD

19

RY1

18

RY2

17

RY3

14

RY4

12

RY5

5

DY1

6

DY2

8

DY3

10

VSS

Place Within APU solder side area

C2200p50X0402

External Thermal diode Mode Current mode

R64 X_10KR0402R64 X_10KR0402 R47 10KR0402R47 10KR0402

R63 X_10KR0402R63 X_10KR0402 R46 X_10KR0402R46 X_10KR0402

C157 X_C0.1u16Y0402C157 X_C0.1u16Y0402 C504 X_C0.1u16Y0402C504 X_C0.1u16Y0402

R478 X_10KR0402R478 X_10KR0402 R599 X_10KR0402R599 X_10KR0402 R598 X_10KR0402R598 X_10KR0402

+12COM_1 RIA# CTSA# DSRA# SINA DCDA#

NRTSA NDTRA NSOUTA

-12COM_1

SIO_VREF

Place close to VRM VDDNB MOSFET(Q37)

CE

C499

EXT_SYS_TEMP

CP21 X_CPCP21 X_CP L48

L48 X_120L600mA-250

X_120L600mA-250

R679 10KR0402R679 10KR0402 R220 X_10KR0402R220 X_10KR0402

R676 10KR0402R676 10KR0402 R678 X_10KR0402R678 X_10KR0402

SIO_VCORE_EN SIO_VLDT_EN SIO_AMD_PWRGD

R603 X_0R0402R603 X_0R0402

R470 X_10KR0402R470 X_10KR0402

R473 X_0R0402R473 X_0R0402

C652 C0.1u50YC652 C0.1u50Y

D51 BAS32L_LL34D51 BAS32L_LL34

D62 BAS32L_LL34D62 BAS32L_LL34

C677 C0.1u50YC677 C0.1u50Y

B

Q25

Q25 N-SST3904_SOT23

N-SST3904_SOT23

C500 C2200p50X0402C500 C2200p50X0402 SEN_HEADER

SEN_HEADER

1 2 3

H2X3[4]M_BLACK-RH

VCC3_SB

VCORE_EN_R 7,27

CPU_VDDP_VDDR_EN 27

FCH_PWRGD 17,27

+12V

-12V

R675

X_10KR1%0402

R311 X_0R0402R311 X_0R0402

RT5

X_10KRT1%

R422 X_0R0402R422 X_0R0402

65

SIO_HWM_AGND

VCC3_SB

CHASSIS TYPE 25L

DEFAULT

17L 13L 10L

MB_ID0 MB_ID1

C508

X_C2200p50X0402

SIO_HWM_AGND

CHASSIS_ID2

CHASSIS_ID1

C756 X_C0.1u16Y0402C756 X_C0.1u16Y0402 C806 X_C0.1u16Y0402C806 X_C0.1u16Y0402

CHASSIS_ID2CHASSIS_ID1

1

00

TinianPangkor

1

0

1

Place close to VRM VDD MOSFET(Q81)

VR_TEMP_DA1

CE

B

Q97

X_N-SST3904_SOT23

VR_TEMP_DC1

11 0 10

RT6

X_10KRT1%

NRTSA

C662 C330p50XC662 C330p50X

NDSRA#

C659 C330p50XC659 C330p50X

NCTSA#

SUPER I/O STRAPPING RESISTOR

2E_4E_SEL

R208 1KR0402R208 1KR0402

VCC3

R212 X_1KR0402R212 X_1KR0402 R186 1KR0402R186 1KR0402

VCC3

R198 X_1KR0402R198 X_1KR0402

VCC3

R175 4.7KR0402R175 4.7KR0402

R209 1KR0402R209 1KR0402

R185 X_47KR1%0402-RHR185 X_47KR1%0402-RH

A A

24M_48M_SEL

TEST_MODE1

SIO_GP25_SMI#

5

RTSA#

DTRA#

SOUTA

NCT5533D POWER ON STRAPPING PIN

Name 0 PowerPIN

15

16 VCC

24M_48M_SEL

TEST_MODE1

18

44

2E2E_4E_SEL

24MHz

TEST MODE 1 DSISABLE

AMD PWR SEQ

4

1

4E

48MHz

TEST MODE1 ENABLE

ENABLE AMD PWR SEQ

VCC

VSB

VSBAMDPWR_EN DISABLE

Description

I/O Configuration Address

Clock Source Selection

1K Pull Low Recommend

AMD SEQ FUNCTION

3

C664 C330p50XC664 C330p50X

NRIA

C666 C330p50XC666 C330p50X

NDCDA#

C660 C330p50XC660 C330p50X

NSOUTA

C663 C330p50XC663 C330p50X

NSINA

C661 C330p50XC661 C330p50X

NDTRA

C665 C330p50XC665 C330p50X

Stuff When COM Port unstuff

SINA

R94 X_4.7KR0402R94 X_4.7KR0402

DSRA#

R118 X_4.7KR0402R118 X_4.7KR0402

DCDA#

R87 X_4.7KR0402R87 X_4.7KR0402 D54

CTSA#

R119 X_4.7KR0402R119 X_4.7KR0402

RIA#

R86 X_4.7KR0402R86 X_4.7KR0402

VCC3

COM2 HEADER

COM2

NDCDA#

1 2

NSINA NRTSA

3 4

NSOUTA

5

NDTRA

7 8 9 10

H2X6[11]M_GREEN-RH

NRIA

X

D54

S-BAT54C_SOT23

2

Y

NDSRA# NCTSA#

6

NRIA COM_GPIO2

12

Z

Close to COM2 PORT header

R300 0R0402R300 0R0402

C674

C674 C0.1u16Y0402

C0.1u16Y0402

N_RI 17

SIO_GP20

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

MICRO-START INT'L CO.,LTD.

SUPER I/O NCT5533D

K415-Virgo 0B

1

25 36Tuesday, November 22, 2011

of

5

VCC5_SB Power Switch

Tune 5VSB inrush current to 2A from 4A

Layout: Place close to

UP7706 pin3 ASAP

D D

SYS5VSB_OFF25

High--------Q20 OFF Low---------Q20 ON

ATX_5VSB

+

12

EC55

.CD1000U6.3EL11.5

Option for Normal State

R552 X_0R1206R552 X_0R1206 R553 X_0R1206R553 X_0R1206

12

+

R514

EC54

249KR1%

X_CD10u16EL5

R531

10KR0805

Soft Start

S0,S1,S3

Q62

DS

P-P06P03LCG_SOT89-3-RH

G

C566

C566 C1U16X5

C1U16X5

EC75 prevent ATX_5VSB inrush current over 2A

EC67:Prevent 5VSB viberation

if there is no viberation on VCC5_SB, place EC67 at ATX_5VSB side

4

Trace Width 80mils.

VCC5_SB

12

+

EC56

EC56 .CD1000U6.3EL11.5

.CD1000U6.3EL11.5

VDUAL_EN

ATX_5VSB

12

+

R535 X_0R0402R535 X_0R0402

R522 10KR1%0402R522 10KR1%0402

EC52

.CD1000U6.3EL11.5

C571

C10u10Y0805

ATX_5VSB

VCC3_WAKE_EN

SIO_GP5725

3

+LAN_3VSB POWER

R538 10RR538 10R

4

U35

1

POK

2

EN

VCTRL

3

VIN

5

VREF

GND8GND

9

R855 X_0R0402R855 X_0R0402 R856 4.7KR0402R856 4.7KR0402

S0,S1,S3,S5

C557 C1U10YC557 C1U10Y

6

VOUT

C539

C0.015u16X0402

7

FB

UP0104PSU8_PSOP8-HF

CE

Q98

B

N-SST3904_SOT23

VCC3_WAKE_EN

R495

R495 10KR1%0402

10KR1%0402

R503

3.09KR1%0402-RH

+LAN_3VSB

C475

C10u10Y0805

2

+

12

EC46

CD470u6.3SO-RH

ATX_5VSB

C558

C10u10Y0805

Pd=( Vin - Vout] * Imax = (5 - 2.5) V * 0.2 Amp = 0.5 W

VCC3_ALW POWER

U37

U37 UP0111AMA5-00_SOT23-5-HF

UP0111AMA5-00_SOT23-5-HF

1

C0.1u16Y0402

VIN

3

EN

C555

mach@Stuff when turn off VCC3_WAKE on S5 state

VOUT

FB

GND

4

2

0.8 V

1

S0,S1,S3,S5,DEEP_S5

5

C556

C0.1u16Y0402

R512

3.16KR1%0402

R2

R513

1KR1%0402

R1

VCC3_ALW

C568

C563

C10u10Y0805

C22u6.3X1206

Vo=0.8*(R1+R2)/R1

0.75V@2A

5VDIMM FOR DDR

R293 510R0402R293 510R0402

C C

VCC5

R294 10KR0402R294 10KR0402

ATX_PWROK7,25,27,33,34

SLP_S3#_R652

VCC5_SB

CRB: MODE Low support S0/S3

SLP_S5#_R687

R299 X_4.7KR0402R299 X_4.7KR0402

Hi support S0/S3/S5

5VDIMM_5V

C309 X_C0.1u16Y0402C309 X_C0.1u16Y0402

U23

S3#55VSB_DRV

6

S5#

MODE

4

MODE

R295

0R0402

R298 10R0402R298 10R0402 C325 X_C0.1u16Y0402C325 X_C0.1u16Y0402

1

2

5VSB

5VCC

5VCC_DRV

GND

3

UP7501M8_SOT23-8-RH

For special PSU sequence

VCC3

B B

R323

X_1KR0402

R322

X_4.7KR0402

SLP_S3#17,25,27 SLP_S5#17,25,27,30

VCC5_SB

R306

X_47KR1%0402-RH

D

G

S

Q51

X_N-2N7002_SOT23

R562 15R0402R562 15R0402 R687 15R0402R687 15R0402

C333

X_C0.1u16Y0402

G

SLP_S3#_R652 SLP_S5#_R687

CPU VDDA_25 POWER

VCC5_SB

R557 10RR557 10R

ATX_PWROK7,25,27,33,34

A A

R362 10KR0402R362 10KR0402

VCC3

C389

4

1

POK

CNTL

2

EN

3

C390

C10u10Y0805

X_C0.1u16Y0402

5

VIN

5

NC

GND8GND

9

Pd=( Vin - Vout] * Imax = (3.3 - 2.5) V * 0.75Amp = 0.6 W

VCC5_SB

5VSBDRV1

7

5VDRV1

8

R284

1.5KR-RH

+12V

5VDIMM_5V

D

Q50

S

X_N-2N7002_SOT23

SLP_S5#_R687 30

C782 X_C0.1u16Y0402C782 X_C0.1u16Y0402

U54

UP0105PSW8_PSOP8-HF

6

VOUT

7

FB

0.8 V

PD=1.9 W

Vo=0.8*(R1+R2)/R1

C212 C18000p16X0402C212 C18000p16X0402

C294

C0.022u50X

Layout:Route 50 mils AND 500 mils LONG (USE 2x25 mil TRACES TO EXIT BALL FIELD)

C373

X_C0.1u16Y0402

VCC5_SB

G

Q47

D S

P06P03LCG_SOT89

D

Q46

G

S

N-45N02_TO252-RH

R286

200KR0402

VCC5

R285

56KR1%0402

2.5V@0.75 A

R351

2.1KR1%0402

R2

R356

1KR1%0402

R1

4

5VDRV1_EN 30

VDDA_25

C374

12

X_C10u10Y0805

5VDIMM

+

EC29

EC29 CD100u16EL5-RH

CD100u16EL5-RH

C247

X_C0.1u16Y0402

L:S5 H:S0,S1,S3

VDUAL_EN

VCC3_SB

VCC5_SB

VCC3_SB

R594

X_0R0402

R595 0R0402R595 0R0402

C630

C10u10Y0805

VCC3_SB_POK

R523 X_0R0402R523 X_0R0402 R485 0R0402R485 0R0402

+

12

EC71

X_CD100u16EL5-RH

VCC3_SB POWER

VCC5_SB

VCC3_SB

VCC5_SB

C525 C10u10Y0805C525 C10u10Y0805

C260 X_C0.1u16Y0402C260 X_C0.1u16Y0402

R596 10RR596 10R

R413

X_10KR0402

VCC3_SB_POK

1

VCC3_SB_EN

2 3

5

C253

X_C0.1u16Y0402

1.1VDUAL POWER

R496 10RR496 10R

U55 UP0104PSU8_PSOP8-HFU55 UP0104PSU8_PSOP8-HF

1

POK

2

EN

3

VIN

5

VREF

GND8GND

Pd=( Vin - Vout] * Imax = (3.3 - 1.1) V * TBD Amp

3

U40

POK EN VIN

VREF

C542 X_C0.1u16Y0402C542 X_C0.1u16Y0402

4

VOUT

VCTRL

FB

9

PD=1.9W

C625 C1U10YC625 C1U10Y

4

VOUT

VCTRL

GND8GND

UP0104PSU8_PSOP8-HF

9

S0,S1,S3

6

7

0.8 V

S0,S1,S3

6

C594

C0.015u16X0402

7

FB

1.V@1.3A----D3

C783

C0.015u16X0402

Vo=0.8*(R1+R2)/R1

For option

R674 0R0805R674 0R0805

0.6A----D2

R489

R2

1KR1%0402

R479

R1

2.61KR1%0402

+1.1VDUAL+1.1VDUAL_D3

R555

R555 10KR1%0402

10KR1%0402

R559

3.09KR1%0402-RH

C528

VCC3_SB

C616

C10u10Y0805

+1.1VDUAL

+

12

C10u10Y0805

12

+

EC53

.CD1000U6.3EL11.5

EC47

CD100u16EL5-RH

2

H:S5 L:S0,S1,S3

SYS5VSB_OFF25

SIO GPIO L:VCC3_WAKE on@ S5 H:VCC3_WAKE off@S5

SIO_VDUAL_EN25

SIO_VDUAL_EN SYS5VSB_OFF

+

12

EC28

ATX_5VSB

VTT_DDR POWER

VCC_DDRVTT_DDR

VCC5

8

NC3

7

NC2

6 5

NC1

C350

R327

R327 1KR1%0402

1KR1%0402

C343

R328

1KR1%0402

.CD1000U6.3EL11.5

C339 X_C0.1u16Y0402C339 X_C0.1u16Y0402

U26

1

VIN

2

GND

3

REFIN

4

VOUT

9

GND

UP0109PSW8_PSOP8-HF

C0.1u16Y0402

VCNTL

DUAL POWER CONTROL

ATX_5VSB

R623

R623 X_20KR1%0402

R629

R629 X_4.7KR0402

X_4.7KR0402

G

R382 X_4.7KR0402R382 X_4.7KR0402

R670 X_0R0402R670 X_0R0402 R411 X_4.7KR0402R411 X_4.7KR0402

B

1 2

R630

X_4.7KR0402

VCC5 VCC3

12

+

EC19

EC65

.CD1000U6.3EL11.5

Title

ACPI UPI & SYS POWER

Size Document Number Rev

Custom

K415-Virgo 0B

Date: Sheet

X_20KR1%0402

VDUAL_EN

VDUAL_EN=NAND (SYS5VSB_OFF . SIO_VDUAL_EN)

DS

C640

Q76

Q76 X_N-2N7002_SOT23

X_N-2N7002_SOT23

X_C0.1u16Y0402

CE

Q36

R665

X_0R0402

VCC3

X_N-SST3904_SOT23

U64

5

INB

VCC

INA

GND3OUTY

CD1000U6.3EL11.5

MICRO-START INT'L CO.,LTD.

R671 X_0R0402R671 X_0R0402

4

X_TC7SH00FU_SSOP5-RH

+

12

+

12

EC33

.CD1000U6.3EL11.5

1

EC45

X_.CD1000U6.3EL11.5

26 36Monday, November 28, 2011

of

R649

R649 X_4.7KR0402

X_4.7KR0402

VDUAL_EN

C1U10Y

5

POWER EN & PWRGD LOGIC CIRCUIT

VCC5_SB 5VDIMM

R174 4.7KR0402R174 4.7KR0402

R202 4.7KR0402R202 4.7KR0402

B

CE

Q28

Q24

N-SST3904_SOT23

D D

SLP_S5#_R68717

VCC5_SB

VCC_DDR

R26

4.7KR0402

R25

R25 X_4.7KR0402

X_4.7KR0402

C C

OD,10KR PU TO 5V

VRM_PWRGD7

B B

NB_VCC1P1

R628 8.2KR0402R628 8.2KR0402

VRM_PWRGD CPU_VDDP_VDDR_EN

VRM_PWRGD

SLP_S3#17,25,26

ATX_PWROK7,25,26,33,34

FP_RST#17,34

VCC5_SB

4.7KR0402

R589

R560

R560 X_10KR0402

X_10KR0402

R30

4.7KR0402

CE

B

Q2

Q2 N-SST3904_SOT23

N-SST3904_SOT23

C27

C4.7u6.3X5

D41

S-RB751V-40_SOD323-RH

D40

S-RB751V-40_SOD323-RH

D9 S-RB751V-40_SOD323-RHD9 S-RB751V-40_SOD323-RH D8 S-RB751V-40_SOD323-RHD8 S-RB751V-40_SOD323-RH D7 S-RB751V-40_SOD323-RHD7 S-RB751V-40_SOD323-RH

SYS_PWRGD

CE

B

Q67

Q67 N-SST3904_SOT23

N-SST3904_SOT23

C600

C600 C1U10Y

C1U10Y

G

CE

B

R29

R29 10KR0402

10KR0402

VCORE_EN_R

DS

Q1

Q1 N-2N7002_SOT23

N-2N7002_SOT23

NBCORE_ENVRM_PWRGDVRM_PWRGD

DS

Q27

G

N-2N7002_SOT23

R173 4.7KR0402R173 4.7KR0402

VCC3_SB

R585

R585 10KR0402

10KR0402

DS

Q69

G

N-2N7002_SOT23

TO VCORE_EN CONTROL

VCORE_EN_R 7,25

C19

C0.1u16Y0402

CPU_VDDP_VDDR_EN 25

FCH_PWRGD_R

ATX_PWROK 7,25,26,33,34

DDR_EN

C171

X_C0.1u16Y0402

4

DDR III 1.5V POWER

C172 C0.1u10X0402C172 C0.1u10X0402

C176 C1000P50X0402C176 C1000P50X0402

CPU_VDD POWER

C491 C0.1u10X0402C491 C0.1u10X0402

C486 C470P50X0402C486 C470P50X0402

+12V

S-BAT54C_SOT23

5VDIMM

R215 2KR1%0402R215 2KR1%0402

1.2V@15A

R421 3.09KR1%0402-RHR421 3.09KR1%0402-RH

CPU_VDDP_VDDR_EN

1.5V@22A

X

D16

Y

DDR_EN

7

DDR_FB

6

0.8 V

R222

1.1KR1%0402

7

6

0.8 V

R427

2KR1%0402

Z

U16

COMP/DIS

FB

U32

COMP/DIS

FB

3

+12V

S-BAT54C_SOT23

R240

2.2R0805

C183 C1U25X0805C183 C1U25X0805

5

DDR_BOOT

1

BST

DDR_HG

2

VCC

TG

DDR_PHASE

8

PHASE

DDR_LG

4

BG

GND

NCP1579DR2G

3

C173 X_C0.01U16X0402C173 X_C0.01U16X0402

R216 976R1%0402R216 976R1%0402

+12V

R426

2.2R0805

C489 C1U25X0805C489 C1U25X0805

5

CPU_VDD_BOOT

1

BST

CPU_VDD_HG

2

VCC

TG

CPU_VDD_PHASE

8

PHASE

CPU_VDD_LGCPU_VDD_FB

4

BG

GND

NCP1579DR2G

3

C492 X_C0.01U16X0402C492 X_C0.01U16X0402

R424 1KR1%0402R424 1KR1%0402

2

X

D15

Z

Q33

R219

R219 1R0805

1R0805

Q33

D

G

S

N-P0903BD

R218

R218 10KR1%0402

10KR1%0402

Q30

D

G

S

N-P0603BD

G

Y

R244 1R0805R244 1R0805

R237

7.32KR1%0402-HE

DDR_HG_R

C175C0.22u25X-HFC175C0.22u25X-HF

R213 X_1KR1%0402R213 X_1KR1%0402

VDDIOFB+10

R224 0R0402R224 0R0402

+12V

S-BAT54C_SOT23

D42

X

R415 1R0805R415 1R0805

R371

18.7KR1%0402-RH

Y

Z

C482C0.22u25X-HFC482C0.22u25X-HF

CPU_VDD_HG_R

R369

R369 1R0805

1R0805

Q54

D

G

S

N-P0903BD

R367

R367 10KR1%0402

10KR1%0402

Q53

D

G

S

N-P0603BD

R434 X_1KR1%0402R434 X_1KR1%0402

VDDR&VDDP IS COMBINED BY DEFAULT VDDP_PWMONLY FOR NORMAL OPERATION(VDDR/VDDP COMBINED MODE) VDDR_PWMIS FOR DEBUG/OC MODE (SEPERATE VDDR/VDDP)

5VDIMM_IN

C245

C215

+

12

EC14

C10u10X50805

X_C0.1u16Y0402

D

S

Q29

N-P0603BD

X_C0.1u16Y0402

CHOKE3 CH-1.1u35A1.7m-RHCHOKE3 CH-1.1u35A1.7m-RH

1 2

R200

2.2R1206

C155

C155 C2200p50X0402

C2200p50X0402

CD470u6.3SO-RH

R223 56R0402R223 56R0402

C440

C391

+

12

EC40

C10u10X50805

X_C0.1u16Y0402

CHOKE10 CH-1.1u35A1.7m-RHCHOKE10 CH-1.1u35A1.7m-RH

CPU_VDDP POWER

CD470u6.3SO-RH

1 2

R368

2.2R1206

C429

C429 C2200p50X0402

C2200p50X0402

VDDP and VDDR support two separate power planes with single regulator

1.2 V@5A

CPU_VDD CPU_VDDP CPU_VDDRCPU_VDD

R337 0R0805R337 0R0805 R336 0R0805R336 0R0805

+

12

EC13

CD470u6.3SO-RH

+

12

EC35

CD470u6.3SO-RH

CHOKE5

CH-1.2u15A3.0m-RH

1 2

C193

C1u10X7R

CHOKE9

CH-1.2u15A3.0m-RH

1 2

C480

C1u10X7R

1

5VDIMM

C265

X_C0.1u16Y0402

+

12

+

12

EC18

EC20

CD1000u63EL11.5-RH

VCC3

C379

X_C0.1u16Y0402

CPU_VDD output 15A OCP:26A

CPU_VDD

+

12

EC32

CD470u6.3SO-RH

CPU_VDDR POWER

R339 0R0805R339 0R0805 R338 0R0805R338 0R0805

VCC_DDR output 22A OCP:38A

VCC_DDR

+

12

+

12

EC24

EC12

CD1000u63EL11.5-RH

+

12

EC38

.CD1000U6.3EL11.5

1.2 V@5A

NB_VCC1P1 POWER

A A

FCH_PWRGD_R

C618 X_C0.1u16Y0402C618 X_C0.1u16Y0402

53

U41

VCC

1

A

Y

2

B

GND

X_AHCT1G126GV_SOT23-5-RH

4

R592 33R0402R592 33R0402

5

VCC3_SB

Rise time ≤ 50-ms. Fall time ≤ 1-ms Deasserted at least 80-ns before VDDCR_11 drops below 5% of its nominal value

FCH_PWRGD

FCH_PWRGD 17,25

NBCORE_EN

4

VCC3

R376

R376 10KR0402

10KR0402

C431

X_C0.1u16Y0402

1.1V@5A

0.8 V

R375

2.55KR1%0402

U30

1

EN

VCC

2

DRV

GND FB3SOFT-S

NCP102SNT1G_TSOP6-RH

3

+12V

6 5

NB_VCC1P1_SS

4

C430

C430 C1U16X5

C1U16X5

C433

1 2

C0.01U16X0402

R370 100R1%R370 100R1%

R373

R373 10KR1%0402

10KR1%0402

C434

C434 C100P50N0402

C100P50N0402

C20 X_C1500p50X0402C20 X_C1500p50X0402

NB_VCC1P1_DRV_RNB_VCC1P1_DRV

C432 C0.022u50XC432 C0.022u50X

R374 1KR1%0402R374 1KR1%0402

CPU_VDD

Q57

D

G

S

N-45N02_TO252-RH

Pd=33 W@Tc=100 °C

C457

C1U16X5

C439 C10u10Y0805C439 C10u10Y0805

2

+

12

C450

X_C10u10X50805

NB_VCC1P1

+

12

EC37

.CD1000U6.3EL11.5

EC36

.CD1000U6.3EL11.5

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet

MICRO-START INT'L CO.,LTD.

FCH CORE & DDR Power

K415-Virgo 0B

1

27 36Thursday, November 24, 2011

of

5

Audio Codec ALC892 (Co-Lay 662/888S)

Default is ALC892

JD resistors should be placed as close as possible to the sense pin of CODEC.

HP_SNS

R591 39.2KR1%0402R591 39.2KR1%0402

MIC_SNS

R590 20KR1%0402R590 20KR1%0402

CEN_JD

Sense_A

C626

C10u10X50805

FPAUD_PRESENCE#

REGREF

GPIO1

D58

S-BAT54A_SOT23

Z

D57

X_S-BAT54A_SOT23

C624

R582 10KR1%0402R582 10KR1%0402

ALC888S/892:stuff ALC662: NC

45 46 47

SPDIFO

48 13

HP_OUT-L

14

HP_OUT-R

15

MIC_IN-L

16

MIC_IN-R

17 18 19

20

C591

C0.1u10X0402

R575 X_0R0402R575 X_0R0402 R574 X_0R0402R574 X_0R0402

ALC662-VC:stuff ALC888S/892/662-VD:NC

Y X

MIC_R_1 MIC_L_1

HP_R_1 HP_L_1

R515

R515 1KR0402

1KR0402 R516

R516 1KR0402

1KR0402 R507

R507 51R0402

51R0402 R508

R508 51R0402

51R0402

D60

D60 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

D59

D59 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

D61

D61 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

FRONT-L

Sense_B

35

33

34

U39

NC

Sense B

FRONT-L

SIDE-L SIDE-R SPDIFI/EAPD SPDIFO

Sense A LINE2-L LINE2-R MIC2-L MIC2-R CD-L CD-GND

CD-R

DVDD11GPOI0/DMIC-CLK2GPIO1/DMIC-DATA3DVSS14SDATA-OUT5BCLK6DVSS27SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP

R641 4.7KR0402R641 4.7KR0402 R643 4.7KR0402R643 4.7KR0402

R645 X_4.7KR0402R645 X_4.7KR0402 R647 X_4.7KR0402R647 X_4.7KR0402

12

D63

D63 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

D D

FRONT-JD

R532 5.1KR1%0402R532 5.1KR1%0402

LINE1-JD

R517 10KR1%0402R517 10KR1%0402

MIC1-JD

R537 20KR1%0402R537 20KR1%0402

SURR_JD

R542 39.2KR1%0402R542 39.2KR1%0402

ALC888S/892:stuff ALC662: NC

VCC3

C C

ALC892 ALC888S-VC ALC662-VD

Pin 3

REGREF GPIO0

Pin 4

GPIO1 GPIO1

ALC662-VC

GPIO1

DVSS

Front Audio Jack

MIC2-VREFO

LINE2-VREFO

B B

MIC_IN-R

C575 C4.7u10X50805-HFC575 C4.7u10X50805-HF

MIC_IN-L

C576 C4.7u10X50805-HFC576 C4.7u10X50805-HF

+

HP_OUT-R HP_OUT-L

+

EC48 CD100u16EL5-RH

1 2

+

EC49 CD100u16EL5-RH

1 2

Audio Power

ALC662/888S: stuff ALC892/662-VD: unstuff

Trace Width 40mils.

D46 X_1N4148W-F_SOD123-RHD46 X_1N4148W-F_SOD123-RH

+12V

A A

R518 X_10R0805R518 X_10R0805

EC51

X_CD100u16EL5-RH

+

12

X_C0.1u16Y0402

5

U36

VIN3VOUT

C587

GND

X_L78L05N_TO92-3

2

Reference resistor for Jack Detection(close to the codec)

Spilt by DGND

AVDD5

C0.1u10X0402

C0.1u10X0402 C634

C634

FRONT-R

SURR_L

SURR_R

CENO

LFE

R597 20KR1%0402R597 20KR1%0402

36

37

FRONT-R

REALTEK

AL892/662

12

44

39

40

42

43

38

41

LFE

JDREF

AVSS2

AVDD2

SURR-L

SURR-R

CENTER

PIN37-VREFO

MIC1-VREFO-L

LINE1-VREFO

LINE2-VREFO

MIC1-VREFO-R

AZ_SDIN_R

REGREF

FPAUD_PRESENCE#

R569 0R0402R569 0R0402

ALC662-VC:NC ALC892/888S/662-VD:stuff

1/16W, 2.5V, max:25mA

F_AUDIO

3

MIC_R

5

MIC_L

7

HP_R HP_L

11 13

H2X7[14]M_ORANGE-RH

R642

R648

X_22KR0402

22KR0402

R644

R646

X_22KR0402

22KR0402

Analog Area Digital Area

Digital Area Analog Area

1

Analog Area Digital Area

21

MIC1-L

22

MIC1-R

23

LINE1-L

24

LINE1-R

25

AVDD1

26

AVSS1

27

VREF

28 29 30

MIC2-VREFO

31 32

ALC892-CG,A2

12

R561 22R0402R561 22R0402 R420 33R0402R420 33R0402

C607

291

HP_SNS

4

MIC_SNS

6 8 10 12

FPAUD_PRESENCE#

3.3V Level GPIO Codec GPIO1

VCC5_SB

Pd=( Vin - Vout] * Imax = (12 - 5 ) V * 0.1Amp = 0.7 W SPEC:PD(max) to 25°C = 625 mW

4

Layout Follow Route

PIN.36

PIN.46

PIN.47

PIN.1 PIN.12

MIC1-IN-L MIC1-IN-R

LINE1-IN-L LINE1-IN-R

C605 C22u6.3X5-HFC605 C22u6.3X5-HF

C622 C10u10X50805C622 C10u10X50805

LDOVDD

C602

15p50N0402

C22p50N0402

D44

X_B140-13-F_SMA-RH

AVDD5_R

C551

MIC1-VREFO-L

MIC2-VREFO LINE2-VREFO

MIC1-VREFO-R

C589

15p50N0402

VCC3

C0.1u10X0402

4

PIN.25

AVDD5

AZ_RST#

C582

C270P50N0402

X_JUMPER-1X2A_GREEN-RH-1

Short Pin3 & Pin5

R579

R579 10KR0402

10KR0402

C617

C617 X_C0.1u16Y0402

X_C0.1u16Y0402

R511 X_0RR511 X_0R

X5R

C554

ALC 662/888S/892 : stuff

C10u10X50805

PIN.24PIN.37

PIN.13PIN.48

Analog Area Digital Area

AZ_RST# 17 AZ_SYNC 17 AZ_SDIN 17 AZ_BIT_CLK 17 AZ_SDOUT 17

F_AUDIO_X1

6.0

AVDD5

Layout: C554 place close to L40

Rear Phone Jack 3 IN 1

EC42

CD10u16EL5

+

LINE1-IN-L L_INL_0

1 2

+

LINE1-IN-R

1 2

EC44

CD10u16EL5

EC69

EC69 CD100u16EL5-RH

CD100u16EL5-RH

+

FRONT-L F_L_0

1 2

+

1 2

EC70

EC70 CD100u16EL5-RH

CD100u16EL5-RH

MIC1-VREFO-L MIC1-VREFO-R

X_CD10u16EL5

+

EC41

1 2

C561

C561 C560

C560

C4.7u10X50805-HF

+

EC43

1 2

X_CD10u16EL5

ALC888S/892: 4.7uX5R,1KR,22KR reserved ALC662: 10u EL,75R,22KR stuffed

In order to meet Vista Premium requirement, ALC892/888S:MLCC input cap MUST use X5R dielectric material and 10V DC rated voltage. ALC662:10uF DIP caps and 22K pull-down resistors

2*3 N58-25F0191-K06

ALC892 PART

ALC662-VC/88S:NC ALC892/662-VD:stuff

VCC5_SB

5.1V

R481

R481 1KR0402

1KR0402

L_INR_0

R476

1KR0402

R487

R487 75R0402

75R0402

F_R_0FRONT-R F_R_1

R494

R494 75R0402

75R0402

R498 2.2KR0402R498 2.2KR0402 R505 2.2KR0402R505 2.2KR0402

C4.7u10X50805-HF

1KR0402

M_INL_0MIC1-IN-L

R510

M_INR_0MIC1-IN-R

R509

1KR0402

1*3 N54-13F0331-K06

A=SURR B=CEN/BAS C=SPDIFOUT D=LINE IN E=LINE OUT F=MIC

Digital Area

Analog Area

21

L40

D43

60n900mA_0805-RH-2

MMSZ5231BT1G-RH

AVDD5_R LDOVDD

R576 0RR576 0R

PIN 29:Reference for integrated regulator

L_INR_1

F_L_1

M_INL_1 M_INR_1

3

L_INL_1

3

R475

R475 22KR0402

22KR0402 R480

R480 22KR0402

22KR0402

D35

D35 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH D34

D34 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

12

R493

R493 22KR0402

22KR0402 R486

R486 22KR0402

22KR0402

D39

D39 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH D33

D33 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

R504

R504 X_22KR0402

X_22KR0402 R497

R497 X_22KR0402

X_22KR0402

D32

D32 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH D29

D29 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

Layout:place close to Pin 3 ASAP

D4 D1 DP

LINE1-JD

AUDIOJACKX5_SPDIFX1-RH

FRONT-JD

AUDIOJACKX5_SPDIFX1-RH

MIC1-JDAZ_BIT_CLK_R

12

AUDIOJACKX5_SPDIFX1-RH

1 2 1 2 1 2

C631 C0.1u16Y0402C631 C0.1u16Y0402 C514 C1000P50X0402C514 C1000P50X0402 C675 C1000P50X0402C675 C1000P50X0402 C567 C1000P50X0402C567 C1000P50X0402

DQ

E4 E1 EP

EQ

F5 F4

F1 FP FQ

CP15CP15 CP6CP6 CP16CP16

C627

C627 C10u10X50805

C10u10X50805

12

Tied at one point only under the codec or near the codec

REGREF

LIN_IN

LIN_OUT

MIC1

AUDIOD

4

AUDIOE

2

AUDIOF

2

Rear Phone Jack 6 IN 1

+

SURR_L SURR_L_0 SURR_R SURR_R_0

+

EC62 CD10u16EL5

1 2

+

EC63 CD10u16EL5

1 2

+

EC58 CD10u16EL5

1 2

+

EC59 CD10u16EL5

1 2

ALC888S/892:stuff ALC662: NC

EMI

For EMI Placement close to Codec chip

LINE1-IN-R

C577 X_C100P50N0402C577 X_C100P50N0402

LINE1-IN-L

C578 X_C100P50N0402C578 X_C100P50N0402

FRONT-R

C633 X_C100P50N0402C633 X_C100P50N0402

FRONT-L

C629 X_C100P50N0402C629 X_C100P50N0402

MIC1-IN-R

C579 X_C100P50N0402C579 X_C100P50N0402

MIC1-IN-L

C580 X_C100P50N0402C580 X_C100P50N0402

SURR_R

C636 X_C100P50N0402C636 X_C100P50N0402

SURR_L

C635 X_C100P50N0402C635 X_C100P50N0402

LFE

C637 X_C100P50N0402C637 X_C100P50N0402

CENO

C638 X_C100P50N0402C638 X_C100P50N0402

Sense_B

C623 X_C0.1u16Y0402C623 X_C0.1u16Y0402

2

LFE_0LFE LFE_1

SPDIFO SPDIFO_C

R469 10R0402R469 10R0402

AVDD(5V)

75R0402

SURR_L_1

R635

SURR_R_1

R632

R632 75R0402

75R0402

R631

R631 22KR0402

22KR0402 R634

R634 22KR0402

22KR0402

D37

D37 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH D36

D36 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

75R0402

CENO_1CENO CENO_0

R627

R627 R622

R622 75R0402

75R0402

R621

R621 22KR0402

22KR0402 R626

R626 22KR0402

22KR0402

D28

D28 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH D38

D38 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

C490

C0.1u16X0402

VCC5

C488

C488 C100P50N0402

C100P50N0402

ALC892 ALC888S-VC ALC662-VD

45.8mA 61mA

11mA 41mA

ALC662-VC

40.5mA

41.5mA

23.4mADVDD(3.3V)

10.8mA

Title

Size Document Number Rev

Custom

Date: Sheet

1

SURR

AUDIOA

5 A4 A1 AP

SURR_JD

AQ

AUDIOJACKX5_SPDIFX1-RH

12

3

CEN/BAS

B4 B1 BP

CEN_JD

12

AUDIOC

TX

A

DRIVE

B

IC

C

LED

TP29TP29

ALC892/662

K415-Virgo 0B

BQ

AUDIOJACKX5_SPDIFX1-RH

AVDD5

MICRO-START INT'L CO.,LTD.

1

AUDIOB

AUDIOJACKX5_SPDIFX1-RH

1

of

28 36Tuesday, November 22, 2011

E

NEAR USB CONNECTOR

4 4

3 3

SVCC2

U12

U12 CMD ( CM1293A-04SO )

CMD ( CM1293A-04SO )

52

SBD8-

614

SBD8+

USB9USB9+ USB8USB8+

SBD4SBD4+

USB5+ USB5- SBD5USB4+ USB4-

R169 X_0RR169 X_0R R160 X_0RR160 X_0R R179 X_0RR179 X_0R R171 X_0RR171 X_0R

SVCC1

614

R313 X_0RR313 X_0R R312 X_0RR312 X_0R R315 X_0RR315 X_0R R314 X_0RR314 X_0R

3

U24

U24 CMD ( CM1293A-04SO )

CMD ( CM1293A-04SO )

52

3

SBD5+ SBD4+

SBD4-

REAR PANEL USB CONNECTOR

SBD9-

SBD9+

SBD9SBD9+ SBD8SBD8+

SBD5+ SBD5-

L3

USB9-17

USB9+17

USB8-17

USB8+17

USB4-17

USB4+17

USB5-17

USB5+17

4

CMC-L12-9008104-RH

L5

4

CMC-L12-9008104-RH

L22

4

CMC-L12-9008104-RH

L23

4

CMC-L12-9008104-RH

231

USB 2.0 trace length REAR side within 18''; FRONT side within 6''

SBD9SBD9+

SBD8SBD8+

SBD4SBD4+

SBD5SBD5+

FRONT USB PIN HEADER

SVCC6

U42

U42 X_CMD ( CM1293A-04SO )

X_CMD ( CM1293A-04SO )

52

SBD0+ SBD0-

USB1+ USB1USB0+

SBD2+

2 2

SBD2- SBD3-

USB3+ USB3USB2+ USB2-

1 1

614

R608 X_0RR608 X_0R R609 X_0RR609 X_0R R610 X_0RR610 X_0R R611 X_0RR611 X_0R

SVCC5

614

R612 X_0RR612 X_0R R613 X_0RR613 X_0R R614 X_0RR614 X_0R R615 X_0RR615 X_0R

SBD1+ SBD1-

3

SBD1+ SBD1SBD0+ SBD0-USB0-

U43

U43 X_CMD ( CM1293A-04SO )

X_CMD ( CM1293A-04SO )

52

SBD3+

3

SBD3+ SBD3SBD2+ SBD2-

USB1-17 USB1+17

USB0-17 USB0+17

USB3-17 USB3+17

USB2-17 USB2+17

L50

4

CMC-L12-9008104-RH

L51

4

CMC-L12-9008104-RH

L52

4

CMC-L12-9008104-RH

L53

4

CMC-L12-9008104-RH

SBD1-

231

SBD1+

SBD0SBD0+

SBD0-

231

SBD0+

SBD3-

231

SBD3+

SBD2- SBD3-SBD3SBD2+

SBD2-

231

SBD2+

D

SVCC2

C788 X_C0.1U16Y0402C788 X_C0.1U16Y0402

USB1

9

11

5

1 2

UP

3 4

1

10

DOWN

USBAX2M_BLACK-RH

SVCC1

X_C0.1u16Y0402

X_C0.1u16Y0402 C290

C290 USB_LANA

USB_LANA

5

PWR

6

USB-

7

USB+

8

GND

1

PWR

2

USB-

3

USB+

4

GND

RJ45_USBX2_TX-RH-3

F_USB1

1 2 3 4

6

5 7 8 9 10

12

H2X6[11]M_YELLOW-RH

F_USB2

1 2 3 4

6

5 7 8 9 10

12

H2X6[11]M_YELLOW-RH

DOWN

5 6 7 8

12

23

GND

24

GND

25

GND

UP

26

GND

27

GND

28

GND

29

GND

30

GND

SBD1SBD1+

SBD3+

SBD9- SBD8SBD9+

SBD5SBD5+

SBD4SBD4+

SVCC6

SVCC5

SBD8+

C

USB 3.0 trace length Front pin header within 3.5''

USB_SS_TX2P_C

R161 0RR161 0R

USB_SS_TX2N_C

R170 0RR170 0R

USB_SS_RX2N

R180 0RR180 0R

USB_SS_RX2P

R172 0RR172 0R

USB_SS_TX2P17 USB_SS_TX2N17

USB_SS_RX2P17 USB_SS_RX2N17

USB_SS_TX3P17 USB_SS_TX3N17

USB_SS_RX3P17 USB_SS_RX3N17

SBD13SBD13+

USB_SS_TX3P_C USB_SS_TX3N_C

USB_SS_RX3N USB_SS_RX3P

USB12USB12+ USB13USB13+

C300 C0.1u10X0402C300 C0.1u10X0402

USB_SS_TX2N USB_SS_TX2N_C USB_SS_TX2N_R

C315 C0.1u10X0402C315 C0.1u10X0402

USB_SS_RX2P USB_SS_RX2P_R

R149 0RR149 0R R154 0RR154 0R

R159 0RR159 0R R157 0RR157 0R

C328 C0.1u10X0402C328 C0.1u10X0402

USB_SS_TX3N USB_SS_TX3N_RUSB_SS_TX3N_C

C334 C0.1u10X0402C334 C0.1u10X0402

USB_SS_RX3P USB_SS_RX3P_R USB_SS_RX3N USB_SS_RX3N_R

SVCC7

U14

U14 X_CMD ( CM1293A-04SO )

X_CMD ( CM1293A-04SO )

52

SBD12-

614

SBD12+

3

SBD12-

R214 X_0RR214 X_0R

SBD12+

R211 X_0RR211 X_0R

SBD13-

R221 X_0RR221 X_0R

SBD13+

R217 X_0RR217 X_0R

USB_SS_RX2N_R USB_SS_RX2P_R

USB_SS_TX2N_R USB_SS_TX2P_R

SBD12+ SBD12-

USB_SS_TX2P_R USB_SS_TX2N_R

USB_SS_RX2N_R USB_SS_RX2P_R

USB_SS_TX2P_CUSB_SS_TX2P USB_SS_TX2P_R

USB_SS_TX3P_R USB_SS_TX3N_R

USB_SS_RX3N_R USB_SS_RX3P_R

USB_SS_TX3P_CUSB_SS_TX3P USB_SS_TX3P_R

USB12+17

USB12-17

USB13-17

USB13+17

F_USB_30

B18

RSVD

B17

RSVD

B16

RSVD

B15

VBUS

B14

VBUS

B13

GND

B12

GND

B11

GND

B10

STDA SSRX-

B9

STDA SSRX+

B8

GND

B7

STDA SSTX-

B6

STDA SSTX+

B5

GND

B4

D+

B3

D-

B2

GND

B1

RSVD

SLOT-PCI36P_WHITE-2PITCH-RH-10

USB_SS_RX2N_R USB_SS_RX2P_R USB_SS_RX2P_R

USB_SS_RX3N_R USB_SS_RX3P_R

L4 X_CMC-L12-9008054-RHL4 X_CMC-L12-9008054-RH

231

4

231

4

L6 X_CMC-L12-9008054-RHL6 X_CMC-L12-9008054-RH

USB_SS_TX3N_R USB_SS_TX3P_R USB_SS_TX3P_R

USB_SS_TX2N_R USB_SS_TX2P_R

L1 X_CMC-L12-9008054-RHL1 X_CMC-L12-9008054-RH

231

4

231

4

L2 X_CMC-L12-9008054-RHL2 X_CMC-L12-9008054-RH

4

X2

A18

RSVD

SVCC7SVCC8

A17

RSVD

A16

RSVD

A15

VBUS

A14

VBUS

A13

GND

A12

GND

X1

A11

GND

A10 A9 A8

GND

A7

STDA SSTX-

A6 A5

GND

A4

D+

A3

D-

A2

GND

A1

RSVD

USB_SS_RX2N_RUSB_SS_RX2N

L10

231

CMC-L12-9008104-RH

L11

231

CMC-L12-9008104-RH

USB_SS_RX3N_R USB_SS_RX3P_R

USB_SS_TX3N_R USB_SS_TX3P_R

SBD13+ SBD13-

U34

1 2

4 5

U57

1 2

4 5

NC

NC NC

NC

NC NC

NC

X_ESD-ESD3V3U4ULC-RH

3

8

10

NC

9

NC

7

NC

6

NC

X_ESD-ESD3V3U4ULC-RH

3

8

SBD12+ SBD12-

SBD13SBD13+

USB_SS_RX2N_R

10 9

USB_SS_RX3N_R

7

USB_SS_RX3P_R

6

USB_SS_TX3N_R

USB_SS_TX2N_R USB_SS_TX2P_R

B

USB 3.0 trace length Rear connector within 8''

USB_SS_TX0P_C

R248 0RR248 0R

USB_SS_TX0N_C

R377 0RR377 0R

USB_SS_RX0N

R378 0RR378 0R

USB_SS_RX0P

R357 0RR357 0R

USB_SS_TX0P

USB_SS_TX0P17

USB_SS_TX0N

USB_SS_TX0N17

USB_SS_RX0N17

USB_SS_TX1N17

USB_SS_RX1N17

USB_SS_RX0P17

USB_SS_TX1P17

USB_SS_RX1P17

SBD10SBD10+

USB_SS_RX0P USB_SS_RX0P_R

USB_SS_TX1P_C

R150 0RR150 0R

USB_SS_TX1N_C

R392 0RR392 0R

USB_SS_RX1N

R394 0RR394 0R

USB_SS_RX1P

R393 0RR393 0R

USB_SS_TX1P USB_SS_TX1N

USB_SS_RX1P USB_SS_RX1P_R

SVCC4

U15

U15 X_CMD ( CM1293A-04SO )

X_CMD ( CM1293A-04SO )

52

614

USB10-

R398 X_0RR398 X_0R

USB10+

R404 X_0RR404 X_0R

USB11-

R399 X_0RR399 X_0R

USB11+

R406 X_0RR406 X_0R

SBD10SBD10+

SVCC3

USB_SS_TX0P_R USB_SS_TX0N_R

USB_SS_RX0P_R USB_SS_RX0N_R

C190 C0.1u10X0402C190 C0.1u10X0402 C443 C0.1u10X0402C443 C0.1u10X0402

C160 C0.1u10X0402C160 C0.1u10X0402 C182 C0.1u10X0402C182 C0.1u10X0402

SBD11SBD11+

3

USB_SS_TX0P_R USB_SS_TX0N_R

USB_SS_RX0N_R USB_SS_RX0P_R

USB_SS_TX1P_R USB_SS_TX1N_R

USB_SS_RX1N_R USB_SS_RX1P_R

SBD10SBD10+ SBD11SBD11+

USBA

9

SSTX2+

1

VBUS2

8

SSTX2-

2

D2-

4

GND

3

D2+

6

SSRX2+

7

GND_D

5

SSRX2-

USBAX2M_BLUE-RH

AVL:N53-18M0041-I60 N53-18M0021-F02

USB_SS_TX0P_C USB_SS_TX0N_C

USB_SS_TX1P_C USB_SS_TX1N_C

19

GND

20

USB_SS_TX1P_R USB_SS_TX1N_R

USB_SS_TX0P_R USB_SS_TX0N_R

L62 X_CMC-L12-9008054-RHL62 X_CMC-L12-9008054-RH

231

4

231

4

L61 X_CMC-L12-9008054-RHL61 X_CMC-L12-9008054-RH

USB_SS_RX0P_R USB_SS_RX0N_R

USB_SS_RX1P_R USB_SS_RX1N_R USB_SS_RX1N_R

L27 X_CMC-L12-9008054-RHL27 X_CMC-L12-9008054-RH

231

4

231

4

L25 X_CMC-L12-9008054-RHL25 X_CMC-L12-9008054-RH

USB10+17 USB10-17

USB11+17

USB11-17

4

CMC-L12-9008104-RH

4

CMC-L12-9008104-RH

USB_SS_TX1P_R USB_SS_TX1N_R

USB_SS_RX1P_R USB_SS_RX1N_R

USB

USBAX2M_BLUE-RH

A

U59

1 2

4 5

3

USB_SS_TX0P_R USB_SS_TX0N_R

USB_SS_RX0N_RUSB_SS_RX0N

U58

1 2

4 5

USB_SS_TX1P_R USB_SS_TX1N_R

USB_SS_RX1N_RUSB_SS_RX1N

L34

231

L28

231

SBD11SBD11+

USB_SS_TX1P_R

10

NC

USB_SS_TX1N_R

9

NC

USB_SS_TX0P_R

7

NC

USB_SS_TX0N_R

6

NC

X_ESD-ESD3V3U4ULC-RH

8

10

NC

9

NC

7

NC

6

NC

X_ESD-ESD3V3U4ULC-RH

3

8

SBD10+ SBD10-

SBD11+ SBD11-

SVCC4

USBB

18

SSTX2+

10

VBUS2

17

SSTX2-

11

D2-

13

GND

12

D2+

15

SSRX2+

16

GND_D

14

SSRX2-

USBAX2M_BLUE-RH

USB_SS_RX0P_R USB_SS_RX0N_R

USB_SS_RX1P_R

21

GND

22

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Date: Sheet of

E

D

C

B

Date: Sheet

MICRO-START INT'L CO.,LTD.

USB POWER/CONNECTORS

Custom

K415-Virgo 0B

A

of

29 36Tuesday, November 22, 2011

8

7

6

5

4

3

2

1

USB 2.0 0.5A pert port

VCC5

Place close to UP7536 pin1

VCC5_SB

VCC5

U22

D D

5VDRV1_EN26

OC#117,20

USB_EN25

VCC5

5VDRV1_EN26

OC#517

USB_EN25

C C

U22

5 6

4

EC61

12

+

X_.CD1000U6.3EL11.5

U47

5 6

4

S3# OC#

EN

S3# OC#

EN

1

2

VOUT1

5VSB

5VCC

VOUT2

GND

UP7536BMA8_SOT23-8-HF

3

1

2

VOUT1

5VSB

5VCC

VOUT2

GND

UP7536BMA8_SOT23-8-HF

3

C66

C66 C10u16X50805-HF

C10u16X50805-HF

7

8

VCC5_SB

C67

C67 C10u16X50805-HF

C10u16X50805-HF

7

8

SVCC1

C291

EC21

+

12

C0.1u16Y0402

.CD1000U6.3EL11.5

SVCC5

EC68

C645

+

12

C0.1u16Y0402

.CD1000U6.3EL11.5

VCC5

1

2

U13

5VDRV1_EN26

5

S3#

6

OC#217,20

USB_EN25

OC#

5VSB

5VCC

4

EN

GND

3

VCC5

1

2

U46

5VDRV1_EN26

5

S3#

6

OC#617

USB_EN25

OC#

5VSB

5VCC

4

EN

GND

3

USB 3.0 0.9A pert port

VCC5_SB

VCC5

1

2

U9

5VDRV1_EN26

5

S3#

6

OC#317,20

USB_EN25

OC#

VOUT1

5VSB

5VCC

EN

VOUT2

GND

UP7536BMA8_SOT23-8-HF

3

4

VCC5

1

2

U7

B B

5VDRV1_EN26

OC#017,20

USB_EN25

U7

5

S3#

6

OC#

VOUT1

5VSB

5VCC

EN

VOUT2

GND

UP7536BMA8_SOT23-8-HF

3

4

7

8

7

8

VCC5_SB

C75

C75 C10u16X50805-HF

C10u16X50805-HF

+

12

C71

C71 C10u16X50805-HF

C10u16X50805-HF

SVCC7

EC75

C86

+

12

.CD1000U6.3EL11.5

SVCC3

EC3.CD1000U6.3EL11.5+EC3.CD1000U6.3EL11.5

VCC5

1

2

U8

C84C0.1u16Y0402 C84C0.1u16Y0402

5VDRV1_EN26

5

S3#

6

OC#417

USB_EN25

OC#

VOUT1

5VSB

5VCC

EN

VOUT2

GND

UP7536BMA8_SOT23-8-HF

3

4

VCC5

1

2

U10

5VDRV1_EN26

C0.1u16Y0402

5

S3#

6

OC#717

USB_EN25

OC#

4

EN

VOUT1

5VSB

5VCC

VOUT2

GND

UP7536BMA8_SOT23-8-HF

3

7

8

7

VOUT1

8

VOUT2

UP7536BMA8_SOT23-8-HF

7

VOUT1

8

VOUT2

UP7536BMA8_SOT23-8-HF

VCC5_SB

7

8

VCC5_SB

C73

C73 C10u16X50805-HF

C10u16X50805-HF

SVCC8

EC76

+

12

.CD1000U6.3EL11.5

VCC5_SB

C68

C68 C10u16X50805-HF

C10u16X50805-HF

VCC5_SB

C70

C70 C10u16X50805-HF

C10u16X50805-HF

C76

C76 C10u16X50805-HF

C10u16X50805-HF

+

12

C445

C0.1u16Y0402

C167

C646

C654

C648

SVCC2

C165

EC8

+

12

C0.1u16Y0402

.CD1000U6.3EL11.5

X_C0.1u16Y0402

C293

C91

C0.1u16Y0402

C804

C114

C0.1u16Y0402

X_C0.1u16Y0402

SVCC1 SVCC5 SVCC6SVCC2 SVCC4 SVCC7

SVCC6

C669

C672

C151

C453

C289

EC67

C644

+

12

C0.1u16Y0402

.CD1000U6.3EL11.5

C289

C0.1u16Y0402

For EMI Placement close to ESD doide power pin.

C672

C742

C0.1u16Y0402

USB power discharge circuit

RN3

Q71

C

B

E

NPN-MMBT2222A-7

RN5

2 4 6 8

Q43

8P4R-270R

RN4

2 4 6 8

8P4R-270R

Q23

RN2

2 4 6 8

8P4R-270R

Q18

SVCC_DIS

C641

X_C0.1u16Y0402

D

G

S

D

G

S

D

G

S

R605 10KR0402R605 10KR0402

ATX_5VSB

R606 8.2KR0402R606 8.2KR0402

SLP_S5#17,25,26,27

SVCC4

EC5.CD1000U6.3EL11.5+EC5.CD1000U6.3EL11.5

C150C0.1u16Y0402 C150C0.1u16Y0402

X_C0.1u16Y0402

SVCC1

SVCC2

SVCC3

C642

1 3 5 7

N-2N7002_SOT23

1 3 5 7

N-2N7002_SOT23

1 3 5 7

N-2N7002_SOT23

D

Q19

G

S

N-2N7002_SOT23

D

Q72

G

S

N-2N7002_SOT23

D

Q70

G

S

N-2N7002_SOT23

D

Q77

G

S

N-2N7002_SOT23

D

Q79

G

S

N-2N7002_SOT23

1 3 5 7

RN3

8P4R-270R

RN16

8P4R-270R

RN15

8P4R-270R

RN17

8P4R-270R

RN18

8P4R-270R

2 4 6 8

Lenovo Consumer MB common spec V0 2: Must reserve ESD protection diode on USB front header 5V_Dual power.

SVCC4 SVCC5 SVCC6SVCC1 SVCC2

12

SVCC4

SVCC5

12

D22

X_ESD-SFI0603ML080C-LF-RH

D12

D14

X_ESD-SFI0603ML080C-LF-RH

Use low-pass filter to prevent glitches duringplug/unplug events.

OC#0

C111 C0.1u16Y0402C111 C0.1u16Y0402

OC#1

C96 C0.1u16Y0402C96 C0.1u16Y0402

OC#2

C116 C0.1u16Y0402C116 C0.1u16Y0402

OC#5

C603 C0.1u16Y0402C603 C0.1u16Y0402

OC#6

C748 C0.1u16Y0402C748 C0.1u16Y0402

OC#7

C749 C0.1u16Y0402C749 C0.1u16Y0402

SVCC6

SVCC7

SVCC8

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

MICRO-START INT'L CO.,LTD.

USB POWER/DISCHARGE

K415-Virgo 0B

SVCC7

12

D48

D56

D49

X_ESD-SFI0603ML080C-LF-RH

of

30 36Tuesday, November 22, 2011

VCC5_SB

Q99

X_N-2N7002_SOT23

USB_EN

C174

X_C0.1u16Y0402

5

4

3

2

1

R440

4.7KR0402

DS

G

SLP_S5#_R68717

A A

8

R698 8.2KR0402R698 8.2KR0402

10KR0402

7

R691

C655

C655 C1U10Y

C1U10Y

CE

Q101

B

N-SST3904_SOT23

6

8

7

6

5

4

3

2

1

PCI Express Slot x16

VCC3

R364 X_4.7KR0402R364 X_4.7KR0402 R365 X_4.7KR0402R365 X_4.7KR0402 R363 X_4.7KR0402R363 X_4.7KR0402

D D

C C

B B

A A

R366 X_4.7KR0402R366 X_4.7KR0402

PE_JTAG_TDI PCIE_RST# PE_JTAG_TMS PE_JTAG_TCK PE_JTAG_TRST#

+LAN_3VSB

PE_WAKE#17,24,25,32,33

GFX_TXC_15P

GFX_TXC_15P8

GFX_TXC_15N

GFX_TXC_15N8

GFX_TXC_14P

GFX_TXC_14P8

GFX_TXC_14N

GFX_TXC_14N8

GFX_TXC_13P

GFX_TXC_13P8

GFX_TXC_13N

GFX_TXC_13N8

GFX_TXC_12P

GFX_TXC_12P8

GFX_TXC_12N

GFX_TXC_12N8

GFX_TXC_11P

GFX_TXC_11P8

GFX_TXC_11N

GFX_TXC_11N8

GFX_TXC_10P

GFX_TXC_10P8

GFX_TXC_10N

GFX_TXC_10N8

GFX_TXC_9P

GFX_TXC_9P8

GFX_TXC_9N

GFX_TXC_9N8

GFX_TXC_8P

GFX_TXC_8P8

GFX_TXC_8N

GFX_TXC_8N8

GFX_TXC_7P

GFX_TXC_7P8

GFX_TXC_7N

GFX_TXC_7N8

GFX_TXC_6P

GFX_TXC_6P8

GFX_TXC_6N

GFX_TXC_6N8

GFX_TXC_5P

GFX_TXC_5P8

GFX_TXC_5N

GFX_TXC_5N8

GFX_TXC_4P

GFX_TXC_4P8

GFX_TXC_4N

GFX_TXC_4N8

GFX_TXC_3P

GFX_TXC_3P8

GFX_TXC_3N

GFX_TXC_3N8

GFX_TXC_2P

GFX_TXC_2P8

GFX_TXC_2N

GFX_TXC_2N8

GFX_TXC_1P

GFX_TXC_1P8

GFX_TXC_1N

GFX_TXC_1N8

GFX_TXC_0P

GFX_TXC_0P8

GFX_TXC_0N

GFX_TXC_0N8

SCLK1

SCLK117,32,33

SDATA1

SDATA117,32,33

VCC3

PE_JTAG_TRST#

PE_WAKE#

PCI EXPRESS x16 Slot

+12V

PCIE16X

X2

B1

12V#B1

B2

12V#B2

B3

RSVD#B3

B4

GND#B4

B5

SMCLK

B6

SMDAT

B7

GND#B7

B8

3.3V#B8

B9

JTAG1

B10

3.3VAUX

B11

WAKE#

B12

RSVD#B12

B13

GND#B13

B14

HSOP0

B15

HSON0

B16

GND#B16

B17

PRSNT2#

B18

GND#B18

B19

HSOP1

B20

HSON1

B21

GND#B21

B22

GND#B22

B23

HSOP2

B24

HSON2

B25

GND#B25

B26

GND#B26

B27

HSOP3

B28

HSON3

B29

GND#B29

B30

RSVD#B30

B31

PRSNT2##B31

B32

GND#B32

B33

HSOP4

B34

HSON4

B35

GND#B35

B36

GND#B36

B37

HSOP5

B38

HSON5

B39

GND#B39

B40

GND#B40

B41

HSOP6

B42

HSON6

B43

GND#B43

B44

GND#B44

B45

HSOP7

B46

HSON7

B47

GND#B47

B48

PRSNT2##B48

B49

GND#B49

B50

HSOP8

B51

HSON8

B52

GND#B52

B53

GND#B53

B54

HSOP9

B55

HSON9

B56

GND#B56

B57

GND#B57

B58

HSOP10

B59

HSON10

B60

GND#B60

B61

GND#B61

B62

HSOP11

B63

HSON11

B64

GND#B64

B65

GND#B65

B66

HSOP12

B67

HSON12

B68

GND#B68

B69

GND#B69

B70

HSOP13

B71

HSON13

B72

GND#B72

B73

GND#B73

B74

HSOP14

B75

HSON14

B76

GND#B76

B77

GND#B77

B78

HSOP15

B79

HSON15

B80

GND#B80

B81

PRSNT2##B81

B82

RSVD#B82

X1

SLOT-PCI164P_BLACK-2PITCH-RH-21

PRSNT1#

12V#A3

JTAG2 JTAG3 JTAG4 JTAG5

3.3V#A10 PWRGD

GND#A12 REFCLK+

REFCLK-

GND#A15

HSIP0 HSIN0

GND#A18

RSVD

GND#A20

HSIP1

HSIN1 GND#A23 GND#A24

HSIP2

HSIN2 GND#A27 GND#A28

HSIP3

HSIN3 GND#A31

RSVD#A32

RSVD#A33

GND#A34

HSIP4

HSIN4 GND#A37 GND#A38

HSIP5

HSIN5 GND#A41 GND#A42

HSIP6

HSIN6 GND#A45 GND#A46

HSIP7

HSIN7 GND#A49

RSVD#A50

GND#A51

HSIP8

HSIN8 GND#A54 GND#A55

HSIP9

HSIN9 GND#A58 GND#A59

HSIP10

HSIN10 GND#A62 GND#A63

HSIP11

HSIN11 GND#A66 GND#A67

HSIP12

HSIN12 GND#A70 GND#A71

HSIP13

HSIN13 GND#A74 GND#A75

HSIP14

HSIN14 GND#A78 GND#A79

HSIP15

HSIN15 GND#A82

VCC3

From Clock Gen

PE16_GXF_CLK 16 PE16_GXF_CLK# 16

GFX_RX15P 8 GFX_RX15N 8

GFX_RX14P 8 GFX_RX14N 8

GFX_RX13P 8 GFX_RX13N 8

GFX_RX12P 8 GFX_RX12N 8

GFX_RX11P 8 GFX_RX11N 8

GFX_RX10P 8 GFX_RX10N 8

GFX_RX9P 8 GFX_RX9N 8

GFX_RX8P 8 GFX_RX8N 8

GFX_RX7P 8 GFX_RX7N 8

GFX_RX6P 8 GFX_RX6N 8

GFX_RX5P 8 GFX_RX5N 8

GFX_RX4P 8 GFX_RX4N 8

GFX_RX3P 8 GFX_RX3N 8

GFX_RX2P 8 GFX_RX2N 8

GFX_RX1P 8 GFX_RX1N 8

GFX_RX0P 8 GFX_RX0N 8

C428 X_C0.1u16Y0402C428 X_C0.1u16Y0402

PCIE_RST# 16,24,32,33

+

12

EC34

Placement Close To PCIE16_X1

VCC3+12V +12V

C427

C424

C425

C426

+LAN_3VSB

C436

C435

+12V

A1 A2

12V

A3 A4

GND

3.3V

PE_JTAG_TCK

A5

PE_JTAG_TDI

A6 A7

PE_JTAG_TMS

A8 A9 A10

PCIE_RST#

A11

A12

PE16_GXF_CLK

A13

PE16_GXF_CLK#

A14 A15

GFX_RX15P

A16

GFX_RX15N

A17 A18

A19 A20

GFX_RX14P

A21

GFX_RX14N

A22 A23 A24

GFX_RX13P

A25

GFX_RX13N

A26 A27 A28

GFX_RX12P

A29

GFX_RX12N

A30 A31 A32

A33 A34

GFX_RX11P

A35

GFX_RX11N

A36 A37 A38

GFX_RX10P

A39

GFX_RX10N

A40 A41 A42

GFX_RX9P

A43

GFX_RX9N

A44 A45 A46

GFX_RX8P

A47

GFX_RX8N

A48 A49

A50 A51

GFX_RX7P

A52

GFX_RX7N

A53 A54 A55

GFX_RX6P

A56

GFX_RX6N

A57 A58 A59

GFX_RX5P

A60

GFX_RX5N

A61 A62 A63

GFX_RX4P

A64

GFX_RX4N

A65 A66 A67

GFX_RX3P

A68

GFX_RX3N

A69 A70 A71

GFX_RX2P

A72

GFX_RX2N

A73 A74 A75

GFX_RX1P

A76

GFX_RX1N

A77 A78 A79

GFX_RX0P

A80

GFX_RX0N

A81 A82

MICRO-START INT'L CO.,LTD.

Title

C0.1u16Y0402

CD470u16EL11.5-RH

8

7

6

C0.1u16Y0402

X_C0.1u16Y0402

5

C0.1u16Y0402

X_C0.1u16Y0402

4

3

2

Title

Size Document Number Rev

Custom

Date: Sheet

MICRO-START INT'L CO.,LTD.

PCI EXPRESS X16

K415-Virgo 0B

31 36Tuesday, November 22, 2011

1

of

8

D D

7

6

5

4

3

2

1

PCI EXPRESS X1 Slot-1 PCI EXPRESS X1 Slot-3

+LAN_3VSB

SCLK1

SCLK117,31,33

SDATA1

SDATA117,31,33

PE_WAKE#17,24,25,31,33

GPP_TXC_0P16

C C

GPP_TXC_0N16

PE_WAKE# PCIE_RST#

+12V +12V

PCIE1X_1

VCC3

PCIE1X_1

B1

12V

B2

12V#B2

B3

RSVD

B4

GND

B5

SMCLK

B6

SMDATA

B7

GND#B7

B8

3.3V

B9

JTAG1

B10

3.3VAUX

B11

WAKE_#

B12

RSVD#B12

B13

GND#B13

B14

HSOP0+

B15

HSOP0-

B16

GND#B16

B17

PRSNT2_#

B18

GND#B18

SLOT-PCI36_BLACK-2PITCH-RH-4

PRSNT1_#

12V#A2 12V#A3

GND#A4

JTAG2 JTAG3 JTAG4 JTAG5

3.3V#A9

3.3V#A10 PWRGD

GND#A12 REFCLK+

REFCLK-

GND#A15

HSIP0+

HSIP0-

GND#A18

X1

X2

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 X1

A12 A13 A14 A15 A16 A17 A18 X2

VCC3

PCIE_RST#

PCIE_RST# 16,24,31,33

PE1_GPP_CLK0 16 PE1_GPP_CLK0# 16

GPP_RX0P 16 GPP_RX0N 16

GPP_TXC_2P16 GPP_TXC_2N16

SCLK1 SDATA1

PE_WAKE#

+LAN_3VSB

+12V +12V

PCIE1X_3

VCC3

PCIE1X_3

B1

12V

B2

12V#B2

B3

RSVD

B4

GND

B5

SMCLK

B6

SMDATA

B7

GND#B7

B8

3.3V

B9

JTAG1

B10

3.3VAUX

B11

WAKE_#

B12

RSVD#B12

B13

GND#B13

B14

HSOP0+

B15

HSOP0-

B16

GND#B16

B17

PRSNT2_#

B18

GND#B18

SLOT-PCI36_BLACK-2PITCH-RH-4

PRSNT1_#

12V#A2 12V#A3

GND#A4

JTAG2 JTAG3 JTAG4 JTAG5

3.3V#A9

3.3V#A10 PWRGD

GND#A12 REFCLK+

REFCLK-

GND#A15

HSIP0+

HSIP0-

GND#A18

X1

X2

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 X1

A12 A13 A14 A15 A16 A17 A18 X2

VCC3

PE1_GPP_CLK2 16 PE1_GPP_CLK2# 16

GPP_RX2P 16 GPP_RX2N 16

+12V

PCI EXPRESS X1 Slot-2

SCLK1 SDATA1

PE_WAKE#

+LAN_3VSB

B B

GPP_TXC_1P16 GPP_TXC_1N16

A A

8

+12V +12V

PCIE1X_2

VCC3

7

PCIE1X_2

B1

12V

B2

12V#B2

B3

RSVD

B4

GND

B5

SMCLK

B6

SMDATA

B7

GND#B7

B8

3.3V

B9

JTAG1

B10

3.3VAUX

B11

WAKE_#

B12

RSVD#B12

B13

GND#B13

B14

HSOP0+

B15

HSOP0-

B16

GND#B16

B17

PRSNT2_#

B18

GND#B18

SLOT-PCI36_BLACK-2PITCH-RH-4

PRSNT1_#

12V#A2 12V#A3

GND#A4

JTAG2 JTAG3 JTAG4 JTAG5

3.3V#A9

3.3V#A10 PWRGD

GND#A12 REFCLK+

REFCLK-

GND#A15

HSIP0+

HSIP0-

GND#A18

X1

X2

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 X1

A12 A13 A14 A15 A16 A17 A18 X2

6

VCC3

PCIE_RST# PCIE_RST#

PE1_GPP_CLK1 16 PE1_GPP_CLK1# 16

GPP_RX1P 16 GPP_RX1N 16

5

VCC3

C472 X_C0.1u16Y0402C472 X_C0.1u16Y0402

+LAN_3VSB

4

C479

C470

C581

C0.1u16Y0402

C503

C471

C613

Place close to Pin A3,B3

C535

C572

X_C0.1u16Y0402

C532

C505

X_C0.1u16Y0402

C531

X_C0.1u16Y0402

3

C651

C619

X_C0.1u16Y0402

C612

C611

X_C0.1u16Y0402

MICRO-START INT'L CO.,LTD.

Title

PCIE X1 SLOTs

Size Document Number Rev

Custom

Date: Sheet

2

MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

of

32 36Tuesday, November 22, 2011

1

5

MINI_PCIE1

PE_WAKE#17,24,25,31,32

PE_MINI_CLK#16 PE_MINI_CLK16

D D

MINI_RXN16 MINI_RXP16

MINI_TXC_N16 MINI_TXC_P16

+3VAUX_WLAN

C C

SP3

Spacer

Support

E2B-1024030-RH

1

VCC3

+LAN_3VSB

B B

R85 0R0402R85 0R0402

SP4

Spacer

Support

E2B-1024030-RH

1

R696 X_0R0805R696 X_0R0805 R697 0R0805R697 0R0805

MINI_PCIE1

1

WAKE#

3

COEX1

5

COEX2

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

Reserved*(UIM_C8)

19

Reserved*(UIM_C4)

21

GND

23

PERn0

25

PERp0

27

GND

29

GND

31

PETn0

33

PETp0

35

GND

37

GND

39

+3.3Vaux

41

+3.3Vaux

43

GND

45

Reserved1

47

Reserved2

49

Reserved3

51

Reserved4

53

GND

SLOT-MINIPCI52P_WHITE-RH

+3VAUX_WLAN

C842

KEY

4

+3.3Vaux

GND

+1.5V

UIM_PWR

UIM_DATA

UIM_CLK

UIM_RESET

UIM_VPP

GND

W_DISABLE#

PERST#

+3.3Vaux

GND

+1.5V

SMB_CLK

SMB_DATA

GND

USB_D-

USB_D+

GND

LED_WWAN#

LED_WLAN#

LED_WPAN#

+1.5V

GND

+3.3Vaux

GND

MEC1 MEC2

3.3V@1.5 A

C839

C840

C841

+3VAUX_WLAN

2 4 6 8 10 12 14 16

18

MINI_DIS#

20 22 24 26 28

MINI_SCLK

30

MINI_SDATA

32 34 36 38 40 42 44 46 48 50 52

54

MEC1 MEC2

C844

C843

R689 0R0402R689 0R0402

R683 0R0402R683 0R0402 R688 0R0402R688 0R0402

LED_WlLAN#

+1_5VRUN_WLAN

R459 0RR459 0R R458 0RR458 0R

+3VAUX_WLAN

ATX_PWROK7,25,26,27,34

3

MINI_PWRON 17 PCIE_RST# 16,24,31,32

+3VAUX_WLAN +1_5VRUN_WLAN

USB6-SBD6USB6+SBD6+

+1_5VRUN_WLAN

VCC3

C851

PCIE_RST#

C849 X_C0.1u16Y0402C849 X_C0.1u16Y0402

SCLK1 17,31,32 SDATA1 17,31,32

+1_5VRUN_WLAN POWER

VCC5_SB

R694 X_10RR694 X_10R

R695 X_10KR0402R695 X_10KR0402

1

POK

2

EN

3

C850

X_C1U10Y0402

X_C10u10Y0805

Pd=( Vin - Vout] * Imax = (3.3 - 1.5) V * 0.5Amp = 0.9 W

VIN

5

NC

C854 X_C0.1u16Y0402C854 X_C0.1u16Y0402

U66

4

X_UP0105PSW8_PSOP8-HF

VOUT

CNTL

FB

0.8 V

GND8GND

9

PD=1.9 W

2

6

7

Vo=0.8*(R1+R2)/R1

L49

SBD6SBD6+

X_CMC-L12-9008104-RH

SBD6SBD6+ SBD6+

C853

X_C0.1u16Y0402

L49

2 3

U65

1

NC

2

NC

4

NC

5

NC

X_ESD-ESD3V3U4ULC-RH

3

8

1.5V@0.5 A

R692

X_976R1%0402

R2

R693

X_1.1KR1%0402

R1

1 4

SBD6-

10 9

7 6

+1_5VRUN_WLAN

C852

X_C22u6.3X1206

1

USB6- 17 USB6+ 17

+

12

EC83

EC83 X_CD100u16EL5-RH

X_CD100u16EL5-RH

C10u10Y0805

C0.1U16Y0402

LED_WlLAN#

VCC5

R146

4.7KR0402

G2 D1 G1

Q106

+3VAUX_WLAN

R143

4.7KR0402

A A

5

NN-2N7002D

S1

4

VCC5

D2

S2

C0.1U16Y0402

R147

4.7KR0402

F_LED_WlLAN#

C0.1U16Y0402

F_LED_WlLAN# 34

MICRO-START INT'L CO.,LTD.

Title

MINI PCIE SLOT

Size Document Number Rev

Custom

Date: Sheet

3

Date: Sheet

2

MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

of

33 36Tuesday, November 22, 2011

1

8

7

6

5

4

3

2

1

ATX CONNECTOR

C0.1u16Y0402

ATX_5VSB

VCC3

R335

R334

R334 0R0402

0R0402

R335

10KR0402

D D

ATX_PSON#25

D71

1N4148W

X_C1000P50X0402

-12V

C0.1u16Y0402

VCC5

C0.1u16Y0402

C C

For EMI

SLED#

C670

C670 X_C0.1u16Y0402

X_C0.1u16Y0402

5VDIMM

B B

LED_SB

C673

C673 X_C0.1u16Y0402

X_C0.1u16Y0402

R492,R473 Pmax=(5*5)/300=0.083W Pspec=0.1W

VCC5

R636 330RR636 330R

R638 330RR638 330R

Green

SLED#

PWRLED LED_SB PWRSW+ PWRSW-

C0.1u16Y0402 C363

C355

C388

C344

C363

25

3.3V

25

3.3V

GND

GND POK

5VSB

+12V +12V

1 2 3 4

5V

5 6

5V

7 8 9 10 11 12

13

3.3V

14

-12V

15

GND

16

P_ON

17

GND

18

GND

19

GND

20

-5V

21

5V

22

5V

23

5V GND243.3V

ATX_POWER

ATX_POWER PWRCONN24P_WHITE-1

PWRCONN24P_WHITE-1

LENOVO Front Panel Connector

F_PANEL

HDDSPK+

NC1 NC2

SPK-

RESET

GNDR

2 4 6

R802 330RR802 330R

8 10 12 14

R639

R639 300R

300R

1

HDD+

3

GNDL

5

SLED2

7

PLED1

9

PWSW+

11

PWSW-

NC13

H2X7[13]_black-2.6mm-RH

C307

C0.1u16Y0402

C387

C387 C0.1u16Y0402

C0.1u16Y0402

HDD-

F_LED_WlLAN# 33

SPK1

FP_RST#

C667

C667 C0.1u16Y0402

C0.1u16Y0402

VCC3

C386

C386 C0.1u16Y0402

C0.1u16Y0402

VCC5

C287

C287 C0.1u16Y0402

C0.1u16Y0402

ATX_5VSB +12V

C327

C327 C0.1u16Y0402

C0.1u16Y0402

VCC3

D55

S-BAT54A_SOT23

Z

X_C0.1u16Y0402

C657

C4.7u6.3X5

C671

VCC5

Y X

VCC5

R324

R324 10KR0402

10KR0402

ATX_PWROK 7,25,26,27,33

C336

C336 C1000P50X0402

C1000P50X0402

R637 X_4.7KR0402R637 X_4.7KR0402

SATA_LED#

Active by South Bridge

VCC3_SB

R640

4.7KR0402

VCC_DDR

VCC3_SB

VCC3

SATA_LED# 18

BAV99

D53

Y

Z

VCC5_SB

R558 X_1KR0402R558 X_1KR0402

R520 X_1KR0402R520 X_1KR0402

C570

X_C0.1u16Y0402

X

FP_RST# 17,27

VCC3

B

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

D

G

S

CE

Q61

Q61 X_N-SST3904_SOT23

X_N-SST3904_SOT23

RN9

RN9 X_8P4R-10R

X_8P4R-10R

RN12

RN12 X_8P4R-10R

X_8P4R-10R

Q65

Q65 X_N-2N7002_SOT23

X_N-2N7002_SOT23

VCCP

POWER LED

X_C0.1u16Y0402

power LED definition

VCC5_SB

R391 X_1KR0402R391 X_1KR0402

X_C0.1u16Y0402

PWRLED

CE

C650

R410 X_1KR0402R410 X_1KR0402

C444

5VDIMM

R593 300RR593 300R R602 4.7KR0402R602 4.7KR0402

B

Q73

Q73 N-SST3904_SOT23

N-SST3904_SOT23

VCC5

B

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

D

G

S

CE

Q56

Q56 X_N-SST3904_SOT23

X_N-SST3904_SOT23

PWR_LED

RN6

RN6 X_8P4R-10R

X_8P4R-10R

RN7

RN7 X_8P4R-10R

X_8P4R-10R

Q58

Q58 X_N-2N7002_SOT23

X_N-2N7002_SOT23

PWR_LED 25

VCC5

D47

D47 BAS32L_LL34

BAS32L_LL34

RN11

1

Q63

7

3 5 7

2 4 6 8

8P4R-150R

C606

C606 C0.1u16Y0402

C0.1u16Y0402

BUZZER

A A

R539 1KR0402R539 1KR0402

SPKR17

8

C

B

E

NPN-MMBT2222A-7

SPK1

VCC5

1 2

BZ1

BUZZER-RH

6

POWER BUTTON

ATX_5VSB ATX_5VSB

BAV99

D50

PWRSW+

5

Y

C668

C668 X_C0.1u16Y0402

X_C0.1u16Y0402

X

Z

R633 100R0402R633 100R0402

12

4

R625

8.2KR0402

PSIN# 25

C649

C649 C0.01U16X0402

C0.01U16X0402

MICRO-START INT'L CO.,LTD.

Title

ATX & FRONT PANEL

Size Document Number Rev

B

Date: Sheet

3

Date: Sheet

MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

2

of

34 36Tuesday, November 22, 2011

1

8

7

6

5

4

3

2

1

HEAT SINK

U14_X1

XX1

D D

XX2

FCH_HEATSINK

HDMI_Logo

HDMI Logo

Y01-RHDMI03-000

Rubber2

Rubber1

PCB

rubber1/2

MANUAL PART

C C

AVL: D06-0100161-F52 D06-0100101-K26

BAT1_X1

BAT-CR2032-RH

PCB1

P30-077020C-E36

GBM ( P30-077790B-G37 )

B B

USB_LAN

USB_LAN CONN

CONN

RJ45_USBX2

RJ45_USBX2 AUDIO

AUDIO

AUDIO JACK

AUDIO 2X3

6KV Giga 15u N58-22F1261-I60

2*3 N54-26F0091-K06

10/100M

1*3 N54-13F0331-K06 N54-13F0211-S42

MH1

7 6

5

981

X_MH001

4

981

MH2

2 3

7 6

5

X_MH001

4

2 3

MH3

7 6

5

981

X_MH001

4

2 3

Optics Orientation Holes

FM3

X_FM120

FM5

X_FM120

FM8

A A

X_FM120

FM4

X_FM120

8

FM2

X_FM120

FM6

X_FM120

FM1

X_FM120

FM7

X_FM120

Simulation

X_JS1

SIM2

X_JS1

SIM1

X_PIN1*2

X_JS2

X_PIN1*2

7

VCC5

6

MH4

7 6

MH8

7 6

5

981

X_MH001

4

981

X_MH001

4

5

2 3

MH5

7 6

MH7

7 6

5

981

X_MH001

4

981

X_MH001

4

2 3

4

MH6

7 6

5

981

X_MH001

4

2 3

MICRO-START INT'L CO.,LTD.

Title

Auto BOM Mnaual

Size Document Number Rev

B

Date: Sheet

3

Date: Sheet

MICRO-START INT'L CO.,LTD.

K415-Virgo 0B

2

of

35 36Tuesday, November 22, 2011

1

5

4

3

2

1

Release V.0a

(2011-10-18)

Release V.0b

(2011-11-09) Page07 Implement power solution, VRM driver "Vin" change to "+12Vin" Page21 Co_lay " HDMI_D19_4" footprint Page26 Add SIO_GP22 to control LAN 3VSB power schematic . Page25 Reserved SLP_S5# to control USB Power. Page25 Implement LPC SMI# solution, connect SIO GP21 to PCH(pin C26). Page17 Trig signal change to "FCH_gevnet4#" from "LPC_SMI#" for Mode switch header. Page18 Implement BIOS socket for debug, add U926 Page26 5VDIMM standby source power change to "VCC5_sb" from "ATX5V_SB". Page27 R237 change to 7.32k from 13.7k,for SA DDR OCP issue.

D D

Page23 SATA footprint change to "SATA_D7_16" for GEN3. page25 R272 stuff with 10K, R65 un-stuffed ,for SA 5VSB drop issue. (2011-11-11) Page21 HDMI CNT P/N change to N5Y-19M0061-L06. Page29 Implement the new "UP7536B" Page23 Fix SATA circuit error.

(2011-11-14) Page23 Fix " co-lay 3pin smart fan (Q91)" circuit error. Page23 Modify Lan_3vsb circuit for LAN power,and change to SIO_gp23 to control it. Page26 "Dual Power control"circuit change to reserved. Page26 Reserved MLCC cap at UP0104 pin2/EN (2011/11/17) Page25&26 Modify SIO GP57 to control +LAN_3VSB power; Page17&25 Modify SIO GP25 connector to FCH LPC_SMI#. Page17 Add R556,R584 for SA slp_s3#,Slp_s5 issue. Page21 Modfiy HDMI DDC bus levelshift circuit.

(2011-11-22) Page26 EC54 un-stuffed, for SA 3VSB step issue. Page17 R483 change to 1k from 0.909k, for USB3.0 issue. Page07 R53 change to 649R from 619R,for SA VCCP OCP issue. Page07&11 EC73,EC74,C794,C795,C796,C789,C790,C791,C792,C815,C816 un-stuffed for SA CPU_VDDNB inrush current issue. Page07 R62,r67 change to 130k ;C46,C50 change to 1000p for update isl6277 . Page21 HDMI CNT P/N change to N5Y-19M0231-L06. Page22 C276,C264,C258 un-stuffed;L20,L19,L16 change to 0R from 10nH;L21,L18,L17 change to 68nH from 0R;C274,C266,C256 change to 10p from 1p. Page35 PCB P/N change to P30-077790B-G37.

Page23 eSATA P/N change to P30-077790B-G37. Page25 Change L5,L3,L28,L34,L23,L22,L11,L10,L50,L51,L52,L53 0ohm to L12-9008104-I05. Page21 Change C271,C91,C8,C114,C293,C222,C6,C13 dummy to 0.1u.

(2011-11-23) Page26 R522 change to 10k from 0R un-stuffed for LAN_POWER. Page7 RT3&RT4 change to 100k from 10k, R57&R58 change to 18.2k from 27K,R68&R66 change to un-stuffed,R21 change to 3.83k,R120 change to 5.6k,C110&C141 change to 2200pF from intersil recommend. Page7 IC NCP1587 P/N change to I32-1579D03-O05.

C C

B B

A A

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

HISTORY

K415-Virgo 0B

1

36 36Thursday, November 24, 2011

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MSI MS-7779 Schematics rev0B

Specifications and Main Features

Frequently Asked Questions

User Manual