MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
6.0Introduction to Intelligent Power Modules (IPM)
Mitsubishi Intelligent Power Modules (IPMs) are advanced hybrid power devices that combine high speed, low loss IGBTs with optimized gate drive and protection circuitry. Highly effective over-current and short-circuit protection is realized through the use of advanced current sense IGBT chips that allow continuous monitoring of power device current. System reliability is further enhanced by the IPM’s integrated over temperature and under voltage lock out protection. Compact, automatically assembled Intelligent Power Modules are designed to reduce system size, cost, and time to market. Mitsubishi Electric introduced the first full line of Intelligent Power Modules in November, 1991. Continuous improvements in power chip, packaging, and control circuit technology have lead to the IPM lineup shown in Table 6.1.
6.0.1Third Generation Intelligent Power Modules
Mitsubishi third generation intelligent power module family shown in Table 6.1 represents the industries most complete line of IPMs. Since their original introduction in 1993 the series has been expanded to include 36 types with ratings ranging from 10A 600V to 800A 1200V. The power semiconductors used in these modules are based on the field proven H-Series IGBT and diode processes. In Table 6.1 the third generation family has been divided into two groups, the “Low Profile Series” and “High Power Series” based on the packaging technology that is used. The third
generation IPM has been optimized for minimum switching losses in order to meet industry demands for acoustically noiseless inverters with carrier frequencies up to 20kHz. The built in gate drive and protection has been carefully designed to minimize the components required for the user supplied interface circuit.
6.0.2 V-Series High Power IPMs
The V-Series IPM was developed in order to address newly emerging industry requirements for higher reliability, lower cost and reduced EMI. By utilizing the low inductance packaging technology developed
for the U-Series IGBT module (described in Section 4.1.5) combined with an advanced super soft freewheel diode and optimized gate drive and protection circuits the V- Series IPM family achieves improved performance at reduced cost. The detailed descriptions of IPM operation and interface requirements presented in Sections 6.1 through 6.8 apply to V-Series as well as third generation IPMs. The only exception being that V- Series IPMs have a unified short circuit protection function that takes the place of the separate short circuit and over current functions described in Sections 6.4.4 and 6.4.5. The unified protection was made
Table 6.1 Mitsubishi Intelligent Power Modules
Type Number |
Amps |
Power Circuit |
Third Generation Low Profile Series - 600V |
||
PM10CSJ060 |
10 |
Six IGBTs |
PM15CSJ060 |
15 |
Six IGBTs |
PM20CSJ060 |
20 |
Six IGBTs |
PM30CSJ060 |
30 |
Six IGBTs |
PM50RSK060 |
50 |
Six IGBTs + Brake ckt. |
PM75RSK060 |
75 |
Six IGBTs + Brake ckt. |
Third Generation Low Profile Series - 1200V |
||
PM10CZF120 |
10 |
Six IGBTs |
PM10RSH120 |
10 |
Six IGBTs + Brake ckt. |
PM15CZF120 |
15 |
Six IGBTs |
PM15RSH120 |
15 |
Six IGBTs + Brake ckt. |
PM25RSK120 |
25 |
Six IGBTs + Brake ckt. |
Third Generation High Power Series - 600V |
||
PM75RSA060 |
75 |
Six IGBTs + Brake ckt. |
PM100CSA060 |
100 |
Six IGBTs |
PM100RSA060 |
100 |
Six IGBTs + Brake ckt. |
PM150CSA060 |
150 |
Six IGBTs |
PM150RSA060 |
150 |
Six IGBTs + Brake ckt. |
PM200CSA060 |
200 |
Six IGBTs |
PM200RSA060 |
200 |
Six IGBTs + Brake ckt. |
PM200DSA060 |
200 |
Two IGBTs: Half Bridge |
PM300DSA060 |
300 |
Two IGBTs: Half Bridge |
PM400DAS060 |
400 |
Two IGBTs: Half Bridge |
PM600DSA060 |
600 |
Two IGBTs: Half Bridge |
PM800HSA060 |
800 |
One IGBT |
Type Number |
Amps Power Circuit |
|
Third Generation High Power Series - 1200V |
||
PM25RSB120 |
25 |
Six IGBTs + Brake ckt. |
PM50RSA120 |
50 |
Six IGBTs + Brake ckt. |
PM75CSA120 |
75 |
Six IGBTs |
PM75DSA120 |
75 |
Two IGBTs: Half Bridge |
PM100CSA120 |
100 |
Six IGBTs |
PM100DSA120 |
100 |
Two IGBTs: Half Bridge |
PM150DSA120 |
150 |
Two IGBTs: Half Bridge |
PM200DSA120 |
200 |
Two IGBTs: Half Bridge |
PM300DSA120 |
300 |
Two IGBTs: Half Bridge |
PM400HSA120 |
400 |
Two IGBTs: Half Bridge |
PM600HSA120 |
600 |
One IGBT |
PM800HSA120 |
800 |
One IGBT |
V-Series High Power |
- 600V |
|
PM75RVA060 |
75 |
Six IGBTs + Brake ckt. |
PM100CVA060 |
100 |
Six IGBTs |
PM150CVA060 |
150 |
Six IGBTs |
PM200CVA060 |
200 |
Six IGBTs |
PM300CVA060 |
300 |
Six IGBTs |
PM400DVA060 |
400 |
Two IGBTs: Half Bridge |
PM600DVA060 |
600 |
Two IGBTs: Half Bridge |
V-Series High Power |
- 1200V |
|
PM50RVA120 |
50 |
Six IGBTs + Brake ckt. |
PM75CVA120 |
75 |
Six IGBTs |
PM100CVA120 |
100 |
Six IGBTs |
PM150CVA120 |
150 |
Six IGBTs |
PM200DVA120 |
200 |
Two IGBTs: Half Bridge |
PM300DVA120 |
300 |
Two IGBTs: Half Bridge |
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
possible by an advanced RTC (Real Time Control) current clamping circuit that eliminates the need for the over current protection function. In V-Series IPMs a unified short circuit protection with a delay to avoid unwanted operation replaces the over current and short circuit modes of the third generation devices.
6.1Structure of Intelligent Power Modules
Mitsubishi Intelligent Power Modules utilize many of the same field proven module packaging technologies used in Mitsubishi IGBT modules. Cost effective implementation of the built in gate drive and protection circuits over a wide range of current ratings was achieved using two different packaging techniques. Low power devices use a multilayer epoxy isolation system while medium and high power devices use ceramic isolation. These packaging technologies are described in more detail in Sections 6.1.1 and 6.1.2. IPM are available in four power circuit configurations, single (H), dual (D), six pack (C), and seven pack (R). Table 6.1 indicates the power circuit of each IPM and Figure 6.1 shows the power circuit configurations.
6.1.1Multilayer Epoxy Construction
Low power IPM (10-50A, 600V and 10-15A, 1200V) use a multilayer epoxy based isolation system. In this system, alternate layers of copper and epoxy are used to create a shielded printed circuit directly on the aluminum base plate. Power
chips and gate control circuit components are soldered directly to the substrate eliminating the need for a separate printed circuit board and ceramic isolation materials. Modules constructed using this technique are easily identified by their
Figure 6.1 Power Circuit
Configuration
TYPE C
P
U V W
N |
|
|
|
TYPE R |
|
|
|
P |
|
|
|
B |
U |
V |
W |
N
TYPE D TYPE H
C1 |
C |
|
C2E1 |
E |
|
E2
extremely low profile packages. This package design is ideally suited for consumer and industrial applications where low cost and compact size are important. Figure 6.2 shows a cross section of this type of IPM package. Figure 6.3 is a PM20CSJ060 20A, 600V IPM.
Figure 6.2 Multi-Layer Epoxy
Construction
|
|
2 |
|
|
3 |
|
|
|
|
|
|
|
|||
|
|
|
|
4 |
|
|
|||||||||
1 |
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
5 |
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
6 |
|
|
11 |
7 |
8 |
9 |
10 |
|
1.Case
2.Epoxy Resin
3.Input Signal Terminal
4.SMT Resistor
5.Gate Control IC
6.SMT Capacitor
7.IGBT Chip
8.Free-wheel Diode Chip
9.Bond Wire
10.Copper Block
11.Baseplate with Epoxy Based Isolation
Figure 6.3 PM20CSJ060
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
6.1.2Ceramic Isolation Construction
Higher power IPMs are constructed using ceramic isolation material. A direct bond copper process in which copper patterns are bonded directly to the ceramic substrate without the use of solder is used in these modules. This substrate provides the improved thermal characteristics and greater current carrying capabilities that are needed in these higher power devices. Gate drive and control circuits are contained on a separate PCB mounted directly above the power devices. The PCB is a multilayer construction with special shield layers for EMI noise immunity. Figure 6.4 shows the structure of a ceramic isolated Intelligent Power Module. Figure 6.5 is a PM75RSA060 75 A, 600V IPM.
Figure 6.4 Ceramic Isolation Construction
INPUT SIGNAL
TERMINAL
MAIN |
EPOXY |
|
GUIDE |
|||
|
|
PIN |
||||
TERMINAL |
RESIN |
|
|
|||
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CASE
BASE
PLATE
SILICON GEL |
INTERCONNECT |
SILICON CHIP |
ELECTRODE TERMINAL |
DBC PLATE |
ALUMINUM WIRE |
|
CONTROL BOARD |
|
PCB |
|
RESISTOR |
|
SHIELD |
|
SHIELD |
LAYER |
|
SIGNAL |
||
LAYER |
||
TRACE |
||
|
Figure 6.5 PM75RSA060
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
6.1.3 V-Series IPM Construction
V-Series IPMs are similar to the ceramic isolated types described
in Section 6.1.2 except that an insert molded case similar to the U-Series IGBT is used. Like the U-Series IGBT described in Section 4.1.5, the V-Series IPM
has lower internal inductance and improved power cycle durability. Figure 6.6 is a cross section drawing showing the construction of the V-Series IPM. The insert molded case makes the V-Series IPM is easier to manufacture and lower in cost. Figure 6.7 shows a PM150CVA120 which is a 150A 1200V V-Series IPM.
6.1.4Advantages of Intelligent Power Module
IPM (Intelligent Power Module) products were designed and developed to provide advantages to Customers by reducing design, development, and manufacturing
costs as well as providing improvement in system performance and reliability over conventional IGBTs. Design and development effort is simplified and successful drive coordination is assured by the integration of the drive and protection circuitry directly into the IPM. Reduced time to market is only one of the additional benefits of using an IPM. Others include increased system reliability through automated IPM assembly and test and reduction in the number of components that must be purchased, stored, and assembled. Often the system size can be reduced through smaller heatsink requirements as a result of lower on-state and switching losses. All IPMs use the same standardized gate control interface with logic level control circuits allowing extension of the product line without additional drive circuit design. Finally, the ability of the IPM to self protect in fault situations reduce the chance of device destruction during development testing as well as in field stress situations.
6.2IPM Ratings and Characteristics
IPM datasheets are divided into three sections:
•Maximum Ratings
•Characteristics (electrical, thermal, mechanical)
•Recommended Operating Conditions
The limits given as maximum rating must not be exceeded under any circumstances, otherwise destruction of the IPM may result.
Key parameters needed for system design are indicated as electrical, thermal, and mechanical characteristics.
The given recommended operating conditions and application circuits should be considered as a preferable design guideline fitting most applications.
Figure 6.6 V-Series IPM Construction |
Figure 6.7 PM150CVA120 |
|
SILICONE GEL |
POWER TERMINALS
SIGNAL TERMINALS
|
COVER |
INSERT MOLD CASE |
|
|
|
PRINTED CIRCUIT |
ALUMINUM |
DBC AIN CERAMIC |
BOARD |
BOND WIRES |
SUBSTRATE |
BASE PLATE
SILICON CHIPS
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
6.2.1 Maximum Ratings
Symbol |
Parameter |
Definition |
Inverter Part |
|
|
|
|
|
VCC |
Supply Voltage |
Maximum DC bus voltage applied between P-N |
VCES |
Collector-Emitter Voltage |
Maximum off-state collector-emitter voltage at applied control input off signal |
±IC |
Collector-Current |
Maximum DC collector and FWDi current @ Tj ≤ 150°C |
±ICP |
Collector-Current (peak) |
Maximum peak collector and FWDi current @ Tj ≤ 150°C |
PC |
Collector Dissipation |
Maximum power dissipation per IGBT switch at Tj = 25°C |
Tj |
Junction Temperature |
Range of IGBT junction temperature during operation |
Brake Part |
|
|
|
|
|
VR(DC) |
FWDi Reverse Voltage |
Maximum reverse voltage of FWDi |
IF |
FWDi Forward Current |
Maximum FWDi DC current at Tj ≤ 150°C |
Control Part |
|
|
|
|
|
VD |
Supply Voltage |
Maximum control supply voltage |
VCIN |
Input Voltage |
Maximum voltage between input (I) and ground (C) pins |
VFO |
Fault Output Supply Voltage |
Maximum voltage between fault output (FO) and ground (C) pins |
IFO |
Fault Output Current |
Maximum sink current of fault output (FO) pin |
Total System |
|
|
|
|
|
VCC(prot) |
Supply Voltage Protected |
Maximum DC bus voltage applied between P-N with guaranteed OC and SC protection |
|
by OC & SC |
|
|
|
|
TC |
Module Case Operating |
Range of allowable case temperature at specified reference point during operation |
|
Temperature |
|
|
|
|
Tstg |
Storage Temperature |
Range of allowable ambient temperature without voltage or current |
Viso |
Isolation Voltage |
Maximum isolation voltage (AC 60Hz 1 min.) between baseplate and module terminals |
|
|
(all main and signal terminals externally shorted together) |
|
|
|
6.2.2 |
Thermal Resistance |
|
Symbol |
Parameter |
Definition |
|
|
|
Rth(j-c) |
Junction to Case |
Maximum value of thermal resistance between junction and case per switch |
|
Thermal Resistance |
|
|
|
|
Rth(c-f) |
Contact Thermal |
Maximum value of thermal resistance between case and fin (heatsink) per IGBT/FWDi pair |
|
Resistance |
with thermal grease applied according to mounting recommendations |
|
|
|
6.2.3 Electrical Characteristics
Symbol |
Parameter |
Definition |
Inverter |
and Brake Part |
|
|
|
|
VCE(sat) |
Collector-Emitter |
IGBT on-state voltage at rated collector current under specified conditions |
|
Saturation Voltage |
|
|
|
|
VEC |
FWDi Forward Voltage |
FWDi forward voltage at rated current under specified conditions |
ton |
Turn-On Time |
|
trr |
FWDi Recovery Time |
Inductive load switching times under rated conditions |
tc(on) |
Turn-On Crossover Time |
(See Figure 6.10) |
toff |
Turn-Off Time |
|
tc(off) |
Turn-Off Crossover Time |
|
ICES |
Collector-Emitter Cutoff |
Collector-Emitter current in off-state at VCE = VCES under specified conditions |
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
6.2.3 Electrical Characteristics (continued)
Symbol |
Parameter |
Definition |
Control Part |
|
|
|
|
|
VD |
Supply Voltage |
Range of allowable control supply voltage in switching operation |
ID |
Circuit Current |
Control supply current in stand-by mode |
VCIN(on) |
Input ON-Voltage |
A voltage applied between input (I) and ground (C) pins less than this value will turn on the IPM |
VCIN(off) |
Input OFF-Voltage |
A voltage applied between input (I) and ground (C) pins higher than this value will turn off the IPM |
fPWM |
PWM Input Frequency |
Range of PWM frequency for VVVF inverter operations |
tdead |
Arm Shoot Through |
Time delay required between high and low side input off/on signals to prevent an |
|
Blocking Time |
arm shoot through |
|
|
|
OC |
Over-Current Trip Level |
Collector that will activate the over-current protection |
|
|
|
SC |
Short-Circuit Trip Level |
Collector current that will activate the short-circuit protection |
|
|
|
toff(OC) |
Over-Current Delay Time |
Time delay after collector current exceeds OC trip level until OC protection is activated |
OT |
Over-Temperature Trip Level |
Baseplate temperature that will activate the over-temperature protection |
|
|
|
OTr |
Over-Temperature |
Temperature that the baseplate must fall below to reset an over-temperature fault |
|
Reset Level |
|
|
|
|
UV |
Control Supply |
Control supply voltage below this value will activate the undervoltage protection |
|
Undervoltage Trip Level |
|
|
|
|
UVr |
Control Supply |
Control supply voltage that must exceed to reset an undervoltage fault |
|
Undervoltage Reset Level |
|
|
|
|
IFO(H) |
Fault Output Inactive Current |
Fault output sink current when no fault has occurred |
IFO(L) |
Fault Output Active Current |
Fault Output sink current when a fault has occurred |
tFO |
Fault Output Pulsed Width |
Duration of the generated fault output pulse |
VSXR |
SXR Terminal Output Voltage |
Regulated power supply voltage on SXR terminal for driving the external optocoupler |
6.2.4 Recommended Operation Conditions
Symbol |
Parameter |
Definition |
VCC |
Main Supply Voltage |
Recommended DC bus voltage range |
VD |
Control Supply Voltage |
Recommended control supply voltage range |
VCIN(on) |
Input ON-Voltage |
Recommended input voltage range to turn on the IPM |
VCIN(off) |
Input OFF-Voltage |
Recommended input voltage range to turn off the IPM |
fPWM |
PWM Input Frequency |
Recommended range of PWM carrier frequency using the recommended application circuit |
tDEAD |
Arm Shoot Through |
Recommended time delay between high and low side off/on signals to the optocouplers |
|
Blocking Time |
using the recommended application circuit |
|
|
|
6.2.5 Test Circuits and Conditions |
|
|
The following test circuits are used |
Figure 6.8 VCE(sat) Test |
Figure 6.9 VEC Test |
to evaluate the IPM characteristics. |
|
|
|
C1(C2) |
C1(C2) |
|
|
1.VCE(sat) and VEC
To ensure specified junction
temperature, Tj, measurements of VCE(sat) and VEC must be performed as low duty factor pulsed tests. (See Figures 6.8 and 6.9)
|
VX1 |
|
|
|
VX1 |
|
|
|
VD |
SXR |
|
|
VD |
SXR |
|
|
|
CX1 |
V |
IC |
CX1 |
V |
IC |
|||
|
|
|||||||
|
|
|
|
|
|
|||
|
VXC |
|
|
|
VXC |
|
|
|
|
|
E1(E2) |
|
|
|
E1(E2) |
|
|
|
|
|
|
|
|
|
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
2. Half-Bridge Test Circuit and |
Figure 6.10 Half-Bridge Test Circuit and Switching Time Definitions |
|||||
Switching Time Definitions. |
|
|
|
|
|
|
Figure 6.10 shows the stan- |
+ |
|
INTEGRATED |
|
|
|
dard half-bridge test circuit and |
|
|
|
|||
|
OFF |
|
|
|||
VD |
GATE |
|
|
|||
switching waveforms. Switch- |
SIGNAL |
CONTROL |
|
|
||
|
|
|
||||
|
|
CIRCUIT |
|
|
||
ing times and FWDi recovery |
|
|
|
|
||
|
|
|
|
+ |
||
characteristics are defined as |
|
|
|
|
||
+ |
|
INTEGRATED |
VCE |
VCC |
||
shown in this figure. |
ON |
|||||
VD |
GATE |
|
IC |
|||
|
PULSE |
CONTROL |
|
|||
3. Overcurrent and |
|
|
CIRCUIT |
|
|
|
|
|
|
|
|
||
Short-Circuit Test |
|
|
|
|
|
Itrip levels and timing specifications in short circuit and overcurrent are defined as shown in Figure 6.11. By using a fixed load resistance the supply voltage, VCC, is gradually increased until OC and SC trip levels are reached.
Precautions:
trr
IC |
VCE |
Irr |
|
90%
90%
|
10% |
|
10% |
|
tc (on) |
tc (off) |
IC |
|
|
||
ICIN |
|
|
|
td (on) |
tr |
td (off) |
tf |
(ton = td (on) + tr) |
(toff = td (off) + tf) |
A.Before applying any main bus
voltage, VCC, the input terminals should be pulled up by resistors to their corresponding control supply (or SXR) pin, each input signal should be kept in OFF state, and the control supply should be provided. After this, the specified ON and OFF level for each input signal should be applied. The control supply should also be applied to the non-operating arm of the module under test and inputs of these arms should be kept to their OFF state.
B.When performing OC and SC
tests the applied voltage, VCC, must be less than VCC(prot) and the turn-off surge voltage spike must not be allowed to
rise above the VCES rating of the device. (These tests must not be attempted using a curve tracer.)
Figure 6.11 Over-Current and Short-Circuit Test Circuit
+ |
|
INTEGRATED |
|
|
ON |
||
VC |
GATE |
||
PULSE |
|||
CONTROL |
|||
|
|
CIRCUIT |
R*
VCC
IC
*R IS SIZED TO CAUSE SC AND OC CONDITIONS
ON |
|
|
|
INPUT |
|
|
|
SIGNAL |
|
PULSE |
|
|
|
|
|
|
|
|
SC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OC |
|
|
|
|
|
|
|
NORMAL |
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
IC |
|
|
|
|
|
|
|
OPERATION |
|
|
|
|
|
|
|
||
SC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OC |
|
|
|
|
|
|
|
OVER |
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
IC |
|
|
toff (OC) |
|
|
|
CURRENT |
|
|
|
|
|
|
||||
|
|
|
|
|
|
|||
SC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OC |
|
|
|
|
|
|
|
SHORT |
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
IC |
|
|
|
|
|
|
|
CIRCUIT |
|
|
|
|
|
|
|
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
6.3Area of Safe Operation for Intelligent Power Modules
The IPMs built-in gate drive and protection circuits protect it from many of the operating modes that would violate the Safe Operation Area (SOA) of non-intelligent IGBT modules. A conventional SOA definition that characterizes all possible combinations of voltage, current, and time that would cause power device failure is not required. In order to define the SOA for IPMs, the power device capability and control circuit operation must both be considered. The resulting easy to use short circuit and switching SOA definitions for Intelligent Power Modules are summarized
in this section.
6.3.1 Switching SOA
Switching or turn-off SOA is normally defined in terms of the maximum allowable simultaneous voltage and current during repetitive turn-off switching operations. In the case of the IPM the built-in gate drive eliminates many of the dangerous combinations of voltage and current that are caused by improper gate drive. In addition, the maximum operating current is limited by the over current protection circuit. Given these constraints the switching SOA can be defined using the waveform shown in Figure 6.12. This waveform shows that the IPM will operate safely as long as the DC bus voltage is below the
data sheet VCC(prot) specification, the turn-off transient voltage across
C-E terminals of each IPM switch is
maintained below the VCES specification, Tj is less than 125°C, and the control power supply voltage is between 13.5V and 16.5V. In this waveform IOC is the maximum current that the IPM will allow without causing an Over Current (OC) fault to occur. In other words, it is just below the OC trip level. This waveform defines the worst case for hard turn-off operations because the IPM will initiate a controlled slow shutdown for currents higher than the OC
trip level.
6.3.2 Short Circuit SOA
The waveform in Figure 6.13 depicts typical short circuit operation. The standard test condition uses a minimum impedance short circuit which causes the maximum short circuit current to flow in the device. In this test, the short circuit current (ISC) is limited only by the device characteristics. The IPM is guaranteed to survive non-repetitive short circuit and over current conditions as long as the initial DC bus volt-
age is less than the VCC(prot) specification, all transient voltages
across C-E terminals of each IPM switch are maintained less than the VCES specification, Tj is less than 125°C, and the control supply voltage is between 13.5V and 16.5V.
Figure 6.12 Turn-Off Waveform
IOC |
≤VCES |
≤VCC(PROT) |
The waveform shown depicts the controlled slow shutdown that is used by the IPM in order to help minimize transient voltages.
Note:
The condition VCE ≤ VCES has to be carefully checked for each IPM
switch. For easing the design another rating is given on the data
sheets, VCC(surge), i.e., the maximum allowable switching surge
voltage applied between the P and N terminals.
6.3.3 Active Region SOA
Like most IGBTs, the IGBTs used in the IPM are not suitable for linear or active region operation. Normally device capabilities in this mode of operation are described in terms of FBSOA (Forward Biased Safe Operating Area). The IPM’s internal gate drive forces the IGBT to operate with a gate voltage of either zero for the off state or the control supply voltage (VD) for the on state. The IPMs under-voltage lock out prevents any possibility of active or linear operation by automatically turning the power device off if VD drops to a level
that could cause desaturation of the IGBT.
Figure 6.13 Short-Circuit
Operation
≤VCES |
≤VCC(PROT) |
ISC |
≤VCES |
toff(OC)
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
6.4. IPM Self Protection
6.4.1 Self Protection Features
IPM (Intelligent Power Modules) have sophisticated built-in protection circuits that prevent the power devices from being damaged should the system malfunction or be over stressed. Our design and applications engineers have developed fault detection and shut down schemes that allow maximum utilization of power device capability without compromising reliability. Control supply under-voltage, overtemperature, over-current, and short-circuit protection are all provided by the IPM's internal gate control circuits. A fault output signal is provided to alert the system controller if any of the protection circuits are activated. Figure 6.14 is a block diagram showing the IPMs internally integrated functions. This diagram also shows the isolated interface circuits and control power supply that must be provided by the user. The internal gate control circuit requires only a simple +15V DC supply. Specially designed gate drive circuits eliminate the need for a negative supply to off bias the IGBT. The IPM control input is designed to interface with optocoupled transistors with a minimum of external components. The
operation and timing of each protection feature is described in Sections 6.4.2 through 6.4.5.
6.4.2Control Supply Under-Voltage Lock-Out
The Intelligent Power Module's internal control circuits operate from an isolated 15V DC supply. If, for any reason, the voltage of this supply drops below the specified un- der-voltage trip level (UVt), the power devices will be turned off and a fault signal will be generated. Small glitches less than the specified tdUV in length will not affect the operation of the control circuitry and will be ignored by the undervoltage protection circuit. In order for normal operation to resume, the supply voltage must exceed the un- der-voltage reset level (UVr). Operation of the under-voltage protection circuit will also occur during power up and power down of the control supply. This operation is normal and the system controller's program should take the fault output delay (tfo) into account. Figure 6.15 is a timing diagram showing the operation of the under-voltage lock-out protection circuit. In this diagram an active low input signal is applied to the input pin of the IPM by the system controller. The effects of control supply power up,
Figure |
6.14 IPM Functional Diagram |
|
|
|
|
INTELLIGENT POWER MODULE |
|
|
|
|
COLLECTOR |
|
ISOLATED |
|
CURRENT |
|
POWER |
GATE |
SENSE |
|
SUPPLY |
IGBT |
|
|
CONTROL |
||
INPUT |
|
CIRCUIT |
SENSE |
SIGNAL |
ISOLATING |
|
|
GATE DRIVE |
CURRENT |
||
|
INTERFACE |
OVER TEMP |
|
|
CIRCUIT |
|
|
|
UV LOCK-OUT |
|
|
|
|
|
|
FAULT |
|
OVER CURRENT |
EMITTER |
OUTPUT |
ISOLATING |
SHORT CIRCUIT |
|
|
INTERFACE |
|
TEMPERATURE |
|
CIRCUIT |
|
|
|
|
SENSOR |
|
|
|
|
power down and failure on the power device gate drive and fault output are shown.
Caution:
1.Application of the main bus
voltage at a rate greater than 20V/μs before the control power supply is on and stabilized may cause destruction of the power devices.
2.Voltage ripple on the control
power supply with dv/dt in excess of 5V/μs may cause a false trip of the UV lock-out.
6.4.3Over-Temperature Protection
The Intelligent Power Module has a temperature sensor mounted on the isolating base plate near the IGBT chips. If the temperature of the base plate exceeds the overtemperature trip level (OT) the IPMs internal control circuit will protect the power devices by disabling the gate drive and ignoring the control input signal until the over temperature condition has subsided. In six and seven pack modules all three low side devices will be turned off and a low side fault signal will be generated. High side switches are unaffected and can still be turned on and off by the system controller. Similarly, in dual type modules only the low side device is disabled. The fault output will remain as long as the overtemperature condition exists. When the temperature falls below the over-temperature reset level (OTr), and the control input is high (offstate) the power device will be enabled and normal operation will resume at the next low (on) input signal. Figure 6.16 is a timing diagram showing the operation of the over-
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
temperature protection circuit.
The over temperature function provides effective protection against overloads and cooling system failures in most applications. However, it does not guarantee that the maximum junction temperature rating of the IGBT chip will never be exceeded. In cases of abnormally high losses such as failure of the system controller to properly regulate current or excessively high switching frequency it is possible
for IGBT chip to exceed Tj(max) before the base plate reaches the OT
trip level.
Caution:
Tripping of the over-temperature protection is an indication of stressful operation. Repetitive tripping should be avoided.
6.4.4 Over-Current Protection
The IPM uses current sense IGBT chips to continuously monitor power device current. If the current though the Intelligent Power Module exceeds the specified overcurrent trip level (OC) for a pe-
riod longer than toff(OC) the IPMs internal control circuit will protect
the power device by disabling the gate drive and generating a fault output signal. The timing of the over-current protection is shown in
Figure 6.17. The toff(OC) delay is implemented in order to avoid trip-
ping of the OC protection on short pulses of current above the OC level that are not dangerous for the power device. When an over-cur-
rent is detected a controlled shutdown is initiated and a fault output is generated. The controlled shutdown lowers the turn-off di/dt which helps to control transient voltages that can occur during
shut down from high fault currents. Most Intelligent Modules use the two step shutdown depicted in Figure 6.17. In the two step shutdown, the gate voltage is reduced to an
intermediate voltage causing the current through the device to drop slowly to a low level. Then, about 5μs later, the gate voltage is reduced to zero completing the shut down. Some of the large six and seven pack IPMs use an active ramp of gate voltage to achieve the desired reduction in turn off di/dt under high fault currents. The oscillographs in Figure 6.18 illustrate
Figure 6.15 Operation of Under-Voltage Lockout
INPUT
SIGNAL
UVr
UVt
CONTROL
SUPPLY
VOLTAGE
FAULT |
|
|
|
|
|
|
|
|
|
OUTPUT |
|
tdUV |
|
|
|
|
|
|
tdUV |
|
|
|
|
|
|
|
|
||
CURRENT |
tFO |
|
tFO |
||||||
(IFO) |
|
|
|
|
|
|
|
|
|
INTERNAL
GATE
VOLTAGE
VGE
|
|
|
|
|
|
|
CONTROL SUPPLY ON |
SHORT |
|
POWER SUPPLY |
CONTROL SUPPLY OFF |
||
|
|
GLITCH |
|
FAULT AND |
|
|
|
|
|
|
|||
|
|
IGNORED |
|
RECOVERY |
|
Figure 6.16 Operation of Over-Temperature
INPUT
SIGNAL
OT
OTr
BASE PLATE TEMPERATURE (Tb)
FAULT OUTPUT CURRENT (IFO)
INTERNAL
GATE
VOLTAGE
VGE
Sep.1998