Mitsubishi M2S56D20AKT-75, M2S56D20AKT-10L, M2S56D20AKT-10, M2S56D20ATP-75L, M2S56D20ATP-75AL Datasheet

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0 (0)

DDR SDRAM

MITSUBISHI LSIs

M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10

(Rev.1.44)

M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10

 

Mar. '02

 

256M Double Data Rate Synchronous DRAM

 

 

 

 

 

 

 

 

 

 

 

 

Contents are subject to change without notice.

 

 

 

 

 

DESCRIPTION

M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit,

M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit,

M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit,

double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK.Input data is registered on both edges of data strobes, and output data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40ATP achieve very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.

FEATURES

-VDD=VDDQ=2.5V+0.2V

-Double data rate architecture; two data transfers per clock cycle

-Bidirectional, data strobe (DQS) is transmitted/received with data

-Differential clock inputs (CLK and /CLK)

-DLL aligns DQ and DQS transitions

-Commands are entered on each positive CLK edge

-Data and data mask are referenced to both edges of DQS

-4-bank operations are controlled by BA0, BA1 (Bank Address)

-/CAS latency- 2.0/2.5 (programmable)

-Burst length- 2/4/8 (programmable)

-Burst typesequential / interleave (programmable)

-Auto precharge / All bank precharge is controlled by A10

-8192 refresh cycles /64ms (4 banks concurrent refresh)

-Auto refresh and Self refresh

-Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)

-SSTL_2 Interface

-Both 66-pin TSOP Package and 64-pin Small TSOP Package M2S56D*0ATP: 0.8mm lead pitch 66-pin TSOP Package M2S56D*0AKT: 0.4mm lead pitch 64-pin Small TSOP Package

-JEDEC standard

- Low Power for the Self Refresh Current ICC6 : 2mA (-75AL , -75L , -10L)

Operating Frequencies

 

Max. Frequency

Max. Frequency

Standard

 

@CL=2.0 *

@CL=2.5 *

 

 

M2S56D20/30/40ATP/AKT-75AL/-75A

133MHz

133MHz

DDR266A

 

 

 

 

M2S56D20/30/40ATP/AKT-75L/-75

100MHz

133MHz

DDR266B

 

 

 

 

M2S56D20/30/40ATP/AKT-10L/-10

100MHz

125MHz

DDR200

 

 

 

 

* CL = CAS(Read) Latency

MITSUBISHI ELECTRIC

1

 

DDR SDRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MITSUBISHI LSIs

 

M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10

(Rev.1.44)

 

 

 

M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10

Mar. '02

 

 

 

 

 

 

 

 

 

 

 

 

256M Double Data Rate Synchronous DRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN CONFIGURATION(TOP VIEW)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD

VDD

VDD

 

1

 

 

 

 

 

 

 

66

VSS

VSS

VSS

NC

DQ0

DQ0

 

2

 

 

 

 

 

 

 

65

DQ15

DQ7

NC

VDDQ

VDDQ

VDDQ

 

3

 

 

 

 

 

 

 

64

VSSQ

VSSQ

VSSQ

NC

NC

DQ1

 

4

 

 

 

 

 

 

 

63

DQ14

NC

NC

DQ0

DQ1

DQ2

 

5

 

 

 

 

 

 

 

62

DQ13

DQ6

DQ3

VSSQ

VSSQ

VSSQ

 

6

66pin TSOP(II)

61

VDDQ

VDDQ

VDDQ

NC

NC

DQ3

 

7

60

DQ12

NC

NC

NC

DQ2

DQ4

 

8

 

 

 

 

 

 

 

59

DQ11

DQ5

NC

VDDQ

VDDQ

VDDQ

 

9

 

 

 

 

 

 

 

58

VSSQ

VSSQ

VSSQ

NC

NC

DQ5

 

10

 

 

 

 

 

 

 

57

DQ10

NC

NC

DQ1

DQ3

DQ6

 

11

 

 

 

 

 

 

 

56

DQ9

DQ4

DQ2

VSSQ

VSSQ

VSSQ

 

12

400mil width

55

VDDQ

VDDQ

VDDQ

NC

NC

DQ7

 

13

54

DQ8

NC

NC

NC

NC

NC

 

14

 

 

 

x

53

NC

NC

NC

VDDQ

VDDQ

VDDQ

 

15

 

 

 

52

VSSQ

VSSQ

VSSQ

 

875mil length

NC

NC

LDQS

 

16

51

UDQS

DQS

DQS

NC

NC

NC

 

17

 

 

 

 

 

 

 

50

NC

NC

NC

VDD

VDD

VDD

 

18

 

 

 

 

 

 

 

49

VREF

VREF

VREF

NC

NC

NC

 

19

0.65mm

48

VSS

VSS

VSS

NC

NC

LDM

 

20

47

UDM

DM

DM

 

Lead Pitch

/WE

/WE

/WE

 

21

46

/CLK

/CLK

/CLK

/CAS

/CAS

/CAS

 

22

 

 

 

 

 

 

 

45

CLK

CLK

CLK

/RAS

/RAS

/RAS

 

23

 

 

 

 

 

 

 

44

CKE

CKE

CKE

/CS

/CS

/CS

 

24

ROW

43

NC

NC

NC

NC

NC

NC

 

25

42

A12

A12

A12

BA0

BA0

BA0

 

26

A0-12

41

A11

A11

A11

BA1

BA1

BA1

 

27

40

A9

A9

A9

 

Column

A10/AP

A10/AP

A10/AP

 

28

39

A8

A8

A8

A0

A0

A0

 

29

A0-9,11(x4)

38

A7

A7

A7

A1

A1

A1

 

30

37

A6

A6

A6

 

A0-9 (x8)

A2

A2

A2

 

31

36

A5

A5

A5

A3

A3

A3

 

32

A0-8 (x16)

35

A4

A4

A4

VDD

VDD

VDD

 

33

34

VSS

VSS

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK,/CLK

: Master Clock

DM

: Write Mask

CKE

: Clock Enable

LDM,UDM

 

/CS

: Chip Select

VREF

: Reference Voltage

/RAS

: Row Address Strobe

A0-12

: Address Input

/CAS

: Column Address Strobe

BA0,1

: Bank Address Input

/WE

: Write Enable

VDD

: Power Supply

DQ0-15

: Data I/O

VDDQ

: Power Supply for Output

DQS

: Data Strobe

VSS

: Ground

LDQS,UDQS

 

VSSQ

: Ground for Output

MITSUBISHI ELECTRIC

2

 

DDR SDRAM

 

 

 

 

 

 

 

 

 

MITSUBISHI LSIs

M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10

(Rev.1.44)

M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10

Mar. '02

 

 

 

256M Double Data Rate Synchronous DRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN CONFIGURATION(TOP VIEW)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X 8

 

 

 

 

 

 

 

 

 

 

X 16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD

VDD

VDD

NC

DQ0

DQ0

VDDQ

VDDQ

VDDQ

NC

NC

DQ1

DQ0

DQ1

DQ2

VSSQ

VSSQ

VSSQ

NC

NC

DQ3

NC

DQ2

DQ4

VDDQ

VDDQ

VDDQ

NC

NC

DQ5

DQ1

DQ3

DQ6

VSSQ

VSSQ

VSSQ

NC

NC

DQ7

VDDQ

VDDQ

VDDQ

NC

NC

LDQS

NC

NC

NC

VDD

VDD

VDD

NC

NC

NC

NC

NC

LDM

/WE

/WE

/WE

/CAS

/CAS

/CAS

/RAS

/RAS

/RAS

/CS

/CS

/CS

NC

NC

NC

BA0

BA0

BA0

BA1

BA1

BA1

A10/AP

A10/AP

A10/AP

A0

A0

A0

A1

A1

A1

A2

A2

A2

A3

A3

A3

VDD

VDD

VDD

 

1

 

 

64

 

 

2

 

 

63

 

 

3

 

 

62

 

 

4

 

 

61

 

 

5

 

 

60

 

 

6

 

 

59

 

 

7

 

 

58

 

 

8

 

 

57

 

 

9

 

 

56

 

 

10

64pin sTSOP

 

55

 

 

11

PIN PITCH 0.4 mm

54

 

 

12

53

 

 

13

52

 

 

 

 

14

51

 

 

 

 

15

50

 

 

16

49

 

 

17

48

 

 

18

47

 

 

19

46

 

 

20

45

 

 

 

 

21

44

 

 

22

43

 

 

 

 

 

 

23

 

 

42

 

 

24

 

 

41

 

 

25

 

 

40

 

 

26

 

 

39

 

 

27

 

 

38

 

 

28

 

 

37

 

 

29

 

 

36

 

 

30

 

 

35

 

 

31

 

 

34

 

 

32

 

 

33

 

 

 

 

 

 

 

VSS

VSS

VSS

DQ15

DQ7

NC

VSSQ

VSSQ

VSSQ

DQ14

NC

NC

DQ13

DQ6

DQ3

VDDQ

VDDQ

VDDQ

DQ12

NC

NC

DQ11

DQ5

NC

VSSQ

VSSQ

VSSQ

DQ10

NC

NC

DQ9

DQ4

DQ2

VDDQ

VDDQ

VDDQ

DQ8

NC

NC

VSSQ

VSSQ

VSSQ

UDQS

DQS

DQS

NC

NC

NC

VREF

VREF

VREF

VSS

VSS

VSS

UDM

DM

DM

/CLK

/CLK

/CLK

CLK

CLK

CLK

CKE

CKE

CKE

NC

NC

NC

A12

A12

A12

A11

A11

A11

A9

A9

A9

A8

A8

A8

A7

A7

A7

A6

A6

A6

A5

A5

A5

A4

A4

A4

VSS

VSS

VSS

CLK,/CLK

: Master Clock

DM

: Write Mask

CKE

: Clock Enable

LDM,UDM

 

/CS

: Chip Select

VREF

: Reference Voltage

/RAS

: Row Address Strobe

A0-12

: Address Input

/CAS

: Column Address Strobe

BA0,1

: Bank Address Input

/WE

: Write Enable

VDD

: Power Supply

DQ0-15

: Data I/O

VDDQ

: Power Supply for Output

DQS

: Data Strobe

VSS

: Ground

LDQS,UDQS

 

VSSQ

: Ground for Output

MITSUBISHI ELECTRIC

3

 

Mitsubishi M2S56D20AKT-75, M2S56D20AKT-10L, M2S56D20AKT-10, M2S56D20ATP-75L, M2S56D20ATP-75AL Datasheet

DDR SDRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MITSUBISHI LSIs

 

 

 

 

 

 

 

 

 

 

 

M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10

(Rev.1.44)

 

 

 

 

 

 

 

 

 

 

 

M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10

Mar. '02

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

256M Double Data Rate Synchronous DRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Package Outline of sTSOP

 

 

 

 

 

 

 

 

+

 

 

 

 

 

 

 

 

0.05

 

 

 

 

 

 

 

 

0.125-

 

 

 

 

 

 

 

 

0.02

64

33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

10.65+0.2

9.05+0.1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

32

*1

1.2 MAX

13.1+0.1

B

0.4 NOM

*3

+0.1

0.08

M

 

0.1

0.16-0.05

0 - 10

 

0.25

 

0.8

0.6+0.15

0.5+0.1

(1)

0.35

0.125+0.075

0.55 MAX

Note)

1.DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2.DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.

Detail A (NTS)

Detail B (NTS)

MITSUBISHI ELECTRIC

4

 

 

DDR SDRAM

 

MITSUBISHI LSIs

 

M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10

 

(Rev.1.44)

M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10

 

Mar. '02

 

 

256M Double Data Rate Synchronous DRAM

 

 

 

 

 

 

 

 

PIN FUNCTION

 

 

 

 

 

 

 

 

SYMBOL

TYPE

DESCRIPTION

 

 

 

 

 

 

 

 

 

Clock: CLK and /CLK are differential clock inputs. All address and control

 

 

CLK, /CLK

Input

input signals are sampled on the crossing of the positive edge of CLK and

 

 

negative edge of /CLK. Output (read) data is referenced to the crossings of

 

 

 

 

CLK and /CLK (both directions of crossing).

 

 

 

 

 

 

 

 

 

Clock Enable: CKE controls internal clock. When CKE is low, internal clock

 

 

CKE

Input

for the following cycle is ceased. CKE is also used to select auto / self

 

 

refresh.After self refresh mode is started, CKE becomes asynchronous

 

 

 

 

 

 

 

 

input. Self refresh is maintained as long as CKE is low.

 

 

 

 

 

 

 

/CS

Input

Chip Select: When /CS is high, any command means No Operation.

 

 

 

 

 

 

 

/RAS, /CAS, /WE

Input

Combination of /RAS, /CAS, /WE defines basic commands.

 

 

 

 

 

 

 

 

 

A0-12 specify the Row / Column Address in conjunction with BA0,1. The

 

 

 

 

Row Address is specified by A0-12. The Column Address is specified by

 

 

A0-12

Input

A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge

 

 

option. When A10 is high at a read / write command, an auto precharge is

 

 

 

 

 

 

 

 

performed. When A10 is high at a precharge command, all banks are

 

 

 

 

precharged.

 

 

 

 

 

 

 

BA0,1

Input

Bank Address: BA0,1 specifies one of four banks to which a command is

 

 

applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.

 

 

 

 

 

 

 

 

 

 

 

DQ0-15(x16),

 

 

 

 

DQ0-7(x8),

Input / Output

Data Input/Output: Data bus

 

 

DQ0-3(x4),

 

 

 

 

 

 

 

 

 

 

 

Data Strobe: Output pin during Read operation, input pin during Write

 

 

DQS

Input / Output

operation. Edge-aligned with read data, placed at the centered of write data

 

 

to capture the write data. For the x16, LDQS corresponds to the data on

 

 

 

 

 

 

 

 

DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15.

 

 

 

 

 

 

 

 

 

Input Data Mask: DM is an input mask signal for write data. Input data

 

 

 

 

is masked when DM is sampled HIGH along with the input data

 

 

DM

Input

during a WRITE operations. DM is sampled on both edges of DQS.

 

 

 

 

Although DM pins are input only, the DM loading matches the DQ

 

 

 

 

and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;

 

 

 

 

UDM corresponds to the data on DQ8-DQ15.

 

 

 

 

 

 

 

VDD, VSS

Power Supply

Power Supply for the memory array and peripheral circuitry.

 

 

 

 

 

 

 

VDDQ, VSSQ

Power Supply

VDDQ and VSSQ are supplied to the Output Buffers only.

 

 

 

 

 

 

 

VREF

Input

SSTL_2 reference voltage.

 

 

 

 

 

 

MITSUBISHI ELECTRIC

5

 

DDR SDRAM

MITSUBISHI LSIs

M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10

(Rev.1.44)

M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10

Mar. '02

256M Double Data Rate Synchronous DRAM

 

 

 

BLOCK DIAGRAM

DQ0 - 15

UDQS,LDQS

 

 

 

 

 

DLL

 

I/O Buffer

QS Buffer

 

Memory

Memory

Memory

Memory

 

Array

 

Array

Array

Array

 

Bank #0

Bank #1

Bank #2

Bank #3

 

Mode Register

 

 

 

 

 

 

Control Circuitry

 

 

Address Buffer

 

Control Signal Buffer

 

 

Clock Buffer

 

 

A0-12

BA0,1

 

/CS

/RAS /CAS /WE

UDM,

 

 

CLK

/CLK CKE

 

LDM

Type Designation Code

This rule is applied to only Synchronous DRAM family.

 

M 2 S 56 D 3 0 A KT –75A L

 

 

 

 

 

 

 

 

 

 

Power Grade L: Low power, Blank: standard

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Speed Grade10: 125MHz@CL=2.5,100MHz@CL=2.0

(DDR200)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

75: 133MHz@CL=2.5,100MHz@CL=2.0

(DDR266B)

 

 

 

 

 

 

 

 

 

75A: 133MHz@CL=2.5,133MHz@CL=2.0

(DDR266A)

 

 

 

 

 

 

 

 

 

Package Type TP: TSOP(II), KT: sTSOP(Small TSOP)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Process Generation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Function Reserved for Future Use

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Organization 2 n 2: x4, 3: x8, 4: x16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR Synchronous DRAM

 

 

 

 

 

 

 

 

 

 

Density 56: 256M bits

Interface V:LVTTL, S:SSTL_3, _2

Memory Style (DRAM)

Mitsubishi Main Designation

MITSUBISHI ELECTRIC

6

 

DDR SDRAM

MITSUBISHI LSIs

M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10

(Rev.1.44)

M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10

Mar. '02

256M Double Data Rate Synchronous DRAM

 

 

 

BASIC FUNCTIONS

The M2S56D20/30/40A* provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. Refer to the command truth table for the detailed definition of commands.

/CLK CLK

/CS

 

 

 

Chip Select : L=select, H=deselect

 

 

 

 

Command

 

/RAS

 

 

 

 

 

 

 

 

Command

 

/CAS

 

 

 

define basic commands

 

 

 

 

 

 

/WE

 

 

 

Command

 

 

 

 

 

Refresh Option @refresh command

CKE

 

 

 

 

 

 

 

Precharge Option @precharge or read/write command

A10

 

 

 

Activate (ACT) [/RAS =L, /CAS =/WE =H]

ACT command activates one row in an idle bank indicated by BA.

Read (READ) [/RAS =H, /CAS =L, /WE =H]

READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H in this command, the bank is deactivated after the burst read (auto - precharge, READA)

Write (WRITE) [/RAS =H, /CAS =/WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is defined by burst length. When A10 =H in this command, the bank is deactivated after the burst write (auto-precharge, WRITEA)

Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H in this command, all banks are deactivated (precharge all, PREA ).

Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]

REFA command starts auto-refresh cycle. Refresh addresses including bank address are generated internally. After this command, the banks are precharged automatically.

MITSUBISHI ELECTRIC

7

 

 

DDR SDRAM

 

 

 

 

 

 

 

 

 

MITSUBISHI LSIs

 

M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10

 

(Rev.1.44)

M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10

 

Mar. '02

 

 

 

 

 

256M Double Data Rate Synchronous DRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COMMAND TRUTH TABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COMMAND

MNEMONIC

 

CKE

CKE

/CS

/RAS

/CAS

/WE

BA0,1

A10

A0-9,

note

 

 

 

 

 

n-1

n

 

 

 

 

 

/AP

11-12

 

 

 

Deselect

DESEL

 

H

X

H

X

X

X

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

No Operation

NOP

 

H

X

L

H

H

H

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Row Address Entry &

ACT

 

H

H

L

L

H

H

V

V

V

 

 

 

Bank Activate

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Single Bank Precharge

PRE

 

H

H

L

L

H

L

V

L

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Precharge All Banks

PREA

 

H

H

L

L

H

L

X

H

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Column Address Entry

WRITE

 

H

H

L

H

L

L

V

L

V

 

 

 

& Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Column Address Entry

WRITEA

 

H

H

L

H

L

L

V

H

V

 

 

 

& Write with

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Auto-Precharge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Column Address Entry

READ

 

H

H

L

H

L

H

V

L

V

 

 

 

& Read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Column Address Entry

 

 

 

 

 

 

 

 

 

 

 

 

 

 

& Read with

READA

 

H

H

L

H

L

H

V

H

V

 

 

 

Auto-Precharge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Auto-Refresh

REFA

 

H

H

L

L

L

H

X

X

X

 

 

 

Self-Refresh Entry

REFS

 

H

L

L

L

L

H

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Self-Refresh Exit

REFSX

 

L

H

H

X

X

X

X

X

X

 

 

 

 

L

H

L

H

H

H

X

X

X

 

 

 

 

 

 

 

 

 

Burst Terminate

TERM

 

H

H

L

H

H

L

X

X

X

1

 

 

Mode Register Set

MRS

 

H

H

L

L

L

L

L

L

V

2

 

H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number

NOTE:

1.Applies only to read bursts while autoprecharge is disabled; this command is undefined (and should not be used) during read bursts while autoprecharge is enabled, as well as during write bursts.

2.BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register;BA0=1 ,BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-codes to be written to the selected Mode Register.

MITSUBISHI ELECTRIC

8

 

 

DDR SDRAM

 

 

 

 

 

MITSUBISHI LSIs

 

 

 

M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10

 

(Rev.1.44)

 

 

 

M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10

 

Mar. '02

 

 

 

 

 

 

 

 

 

256M Double Data Rate Synchronous DRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTION TRUTH TABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Current State

/CS

/RAS

/CAS

/WE

Address

Command

Action

Notes

 

 

IDLE

H

X

X

X

X

DESEL

NOP

 

 

 

 

L

H

H

H

X

NOP

NOP

 

 

 

 

L

H

H

L

BA

TERM

ILLEGAL

2

 

 

 

L

H

L

X

BA, CA, A10

READ / WRITE

ILLEGAL

2

 

 

 

L

L

H

H

BA, RA

ACT

Bank Active, Latch RA

 

 

 

 

L

L

H

L

BA, A10

PRE / PREA

NOP

4

 

 

 

L

L

L

H

X

REFA

Auto-Refresh

5

 

 

 

L

L

L

L

Op-Code,

MRS

Mode Register Set

5

 

 

 

Mode-Add

 

 

 

 

 

 

 

 

 

 

 

 

ROW ACTIVE

H

X

X

X

X

DESEL

NOP

 

 

 

 

L

H

H

H

X

NOP

NOP

 

 

 

 

L

H

H

L

BA

TERM

NOP

 

 

 

 

L

H

L

H

BA, CA, A10

READ / READA

Begin Read, Latch CA,

 

 

 

 

Determine Auto-Precharge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

L

L

BA, CA, A10

WRITE / WRITEA

Begin Write, Latch CA,

 

 

 

 

Determine Auto-Precharge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

L

H

H

BA, RA

ACT

Bank Active / ILLEGAL

2

 

 

 

L

L

H

L

BA, A10

PRE / PREA

Precharge / Precharge All

 

 

 

 

L

L

L

H

X

REFA

ILLEGAL

 

 

 

 

L

L

L

L

Op-Code,

MRS

ILLEGAL

 

 

 

 

Mode-Add

 

 

 

 

 

 

 

 

 

 

 

 

 

READ(Auto-

H

X

X

X

X

DESEL

NOP (Continue Burst to END)

 

 

 

Precharge

L

H

H

H

X

NOP

NOP (Continue Burst to END)

 

 

 

Disabled)

L

H

H

L

BA

TERM

Terminate Burst

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Terminate Burst, Latch CA, Begin

 

 

 

 

L

H

L

H

BA, CA, A10

READ / READA

New Read, Determine Auto-

3

 

 

 

 

 

 

 

 

 

Precharge

 

 

 

 

L

H

L

L

BA, CA, A10

WRITE / WRITEA

ILLEGAL

 

 

 

 

L

L

H

H

BA, RA

ACT

Bank Active / ILLEGAL

2

 

 

 

L

L

H

L

BA, A10

PRE / PREA

Terminate Burst, Precharge

 

 

 

 

L

L

L

H

X

REFA

ILLEGAL

 

 

 

 

L

L

L

L

Op-Code,

MRS

ILLEGAL

 

 

 

 

Mode-Add

 

 

 

 

 

 

 

 

 

 

 

 

MITSUBISHI ELECTRIC

9

 

 

DDR SDRAM

 

 

 

 

 

MITSUBISHI LSIs

 

 

 

M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10

 

(Rev.1.44)

 

 

 

M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10

 

Mar. '02

 

 

 

 

 

 

 

 

 

256M Double Data Rate Synchronous DRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTION TRUTH TABLE (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Current State

/CS

/RAS

/CAS

/WE

Address

Command

Action

Notes

 

 

WRITE(Auto-

H

X

X

X

X

DESEL

NOP (Continue Burst to END)

 

 

 

Precharge

L

H

H

H

X

NOP

NOP (Continue Burst to END)

 

 

 

Disabled)

L

H

H

L

BA

TERM

ILLEGAL

 

 

 

 

 

 

 

 

L

H

L

H

BA, CA, A10

READ / READA

Terminate Burst, Latch CA, Begin

3

 

 

 

Read, Determine Auto-Precharge

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

L

L

BA, CA, A10

WRITE / WRITEA

Terminate Burst, Latch CA, Begin

3

 

 

 

Write, Determine Auto-Precharge

 

 

 

 

 

 

 

 

 

 

 

 

 

L

L

H

H

BA, RA

ACT

Bank Active / ILLEGAL

2

 

 

 

L

L

H

L

BA, A10

PRE / PREA

Terminate Burst, Precharge

 

 

 

 

L

L

L

H

X

REFA

ILLEGAL

 

 

 

 

L

L

L

L

Op-Code,

MRS

ILLEGAL

 

 

 

 

Mode-Add

 

 

 

 

 

 

 

 

 

 

 

 

 

READ with

H

X

X

X

X

DESEL

NOP (Continue Burst to END)

 

 

 

Auto-

L

H

H

H

X

NOP

NOP (Continue Burst to END)

 

 

 

Precharge

L

H

H

L

BA

TERM

ILLEGAL

 

 

 

 

 

 

 

 

L

H

L

H

BA, CA, A10

READ / READA

ILLEGAL for Same Bank

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

L

L

BA, CA, A10

WRITE / WRITEA

ILLEGAL for Same Bank

6

 

 

 

L

L

H

H

BA, RA

ACT

Bank Active / ILLEGAL

2

 

 

 

L

L

H

L

BA, A10

PRE / PREA

Precharge / ILLEGAL

2

 

 

 

L

L

L

H

X

REFA

ILLEGAL

 

 

 

 

L

L

L

L

Op-Code,

MRS

ILLEGAL

 

 

 

 

Mode-Add

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE with

H

X

X

X

X

DESEL

NOP (Continue Burst to END)

 

 

 

Auto-

L

H

H

H

X

NOP

NOP (Continue Burst to END)

 

 

 

Precharge

L

H

H

L

BA

TERM

ILLEGAL

 

 

 

 

 

 

 

 

L

H

L

H

BA, CA, A10

READ / READA

ILLEGAL for Same Bank

7

 

 

 

L

H

L

L

BA, CA, A10

WRITE / WRITEA

ILLEGAL for Same Bank

7

 

 

 

L

L

H

H

BA, RA

ACT

Bank Active / ILLEGAL

2

 

 

 

L

L

H

L

BA, A10

PRE / PREA

Precharge / ILLEGAL

2

 

 

 

L

L

L

H

X

REFA

ILLEGAL

 

 

 

 

L

L

L

L

Op-Code,

MRS

ILLEGAL

 

 

 

 

Mode-Add

 

 

 

 

 

 

 

 

 

 

 

 

MITSUBISHI ELECTRIC

10

 

DDR SDRAM

 

 

 

 

 

MITSUBISHI LSIs

 

 

M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10

(Rev.1.44)

 

 

 

M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10

Mar. '02

 

 

 

 

 

 

 

 

256M Double Data Rate Synchronous DRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTION TRUTH TABLE (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

Current State

/CS

/RAS

/CAS

/WE

Address

Command

Action

Notes

 

PRE-

H

X

X

X

X

DESEL

NOP (Idle after tRP)

 

 

CHARGING

L

H

H

H

X

NOP

NOP (Idle after tRP)

 

 

 

L

H

H

L

BA

TERM

ILLEGAL

2

 

 

L

H

L

X

BA, CA, A10

READ / WRITE

ILLEGAL

2

 

 

L

L

H

H

BA, RA

ACT

ILLEGAL

2

 

 

L

L

H

L

BA, A10

PRE / PREA

NOP (Idle after tRP)

4

 

 

L

L

L

H

X

REFA

ILLEGAL

 

 

 

L

L

L

L

Op-Code,

MRS

ILLEGAL

 

 

 

Mode-Add

 

 

 

 

 

 

 

 

 

 

 

ROW

H

X

X

X

X

DESEL

NOP (Row Active after tRCD)

 

 

L

H

H

H

X

NOP

NOP (Row Active after tRCD)

 

 

ACTIVATING

 

 

L

H

H

L

BA

TERM

ILLEGAL

2

 

 

 

 

L

H

L

X

BA, CA, A10

READ / WRITE

ILLEGAL

2

 

 

L

L

H

H

BA, RA

ACT

ILLEGAL

2

 

 

L

L

H

L

BA, A10

PRE / PREA

ILLEGAL

2

 

 

L

L

L

H

X

REFA

ILLEGAL

 

 

 

L

L

L

L

Op-Code,

MRS

ILLEGAL

 

 

 

Mode-Add

 

 

 

 

 

 

 

 

 

 

 

WRITE RE-

H

X

X

X

X

DESEL

NOP

 

 

L

H

H

H

X

NOP

NOP

 

 

COVERING

 

 

L

H

H

L

BA

TERM

ILLEGAL

2

 

 

 

 

L

H

L

X

BA, CA, A10

READ / WRITE

ILLEGAL

2

 

 

L

L

H

H

BA, RA

ACT

ILLEGAL

2

 

 

L

L

H

L

BA, A10

PRE / PREA

ILLEGAL

2

 

 

L

L

L

H

X

REFA

ILLEGAL

 

 

 

L

L

L

L

Op-Code,

MRS

ILLEGAL

 

 

 

Mode-Add

 

 

 

 

 

 

 

 

 

 

 

MITSUBISHI ELECTRIC

11

 

 

DDR SDRAM

 

 

 

 

 

MITSUBISHI LSIs

 

 

 

M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10

 

(Rev.1.44)

 

 

 

M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10

 

Mar. '02

 

 

 

 

 

 

 

 

 

256M Double Data Rate Synchronous DRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTION TRUTH TABLE (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Current State

/CS

/RAS

/CAS

/WE

Address

Command

Action

Notes

 

 

REFRESHING

H

X

X

X

X

DESEL

NOP (Idle after tRFC)

 

 

 

 

L

H

H

H

X

NOP

NOP (Idle after tRFC)

 

 

 

 

L

H

H

L

BA

TERM

ILLEGAL

 

 

 

 

L

H

L

X

BA, CA, A10

READ / WRITE

ILLEGAL

 

 

 

 

L

L

H

H

BA, RA

ACT

ILLEGAL

 

 

 

 

L

L

H

L

BA, A10

PRE / PREA

ILLEGAL

 

 

 

 

L

L

L

H

X

REFA

ILLEGAL

 

 

 

 

L

L

L

L

Op-Code,

MRS

ILLEGAL

 

 

 

 

Mode-Add

 

 

 

 

 

 

 

 

 

 

 

 

 

MODE

H

X

X

X

X

DESEL

NOP (Idle after tMRD)

 

 

 

REGISTER

L

H

H

H

X

NOP

NOP (Idle after tMRD)

 

 

 

SETTING

L

H

H

L

BA

TERM

ILLEGAL

 

 

 

 

 

 

 

 

L

H

L

X

BA, CA, A10

READ / WRITE

ILLEGAL

 

 

 

 

L

L

H

H

BA, RA

ACT

ILLEGAL

 

 

 

 

L

L

H

L

BA, A10

PRE / PREA

ILLEGAL

 

 

 

 

L

L

L

H

X

REFA

ILLEGAL

 

 

 

 

L

L

L

L

Op-Code,

MRS

ILLEGAL

 

 

 

 

Mode-Add

 

 

 

 

 

 

 

 

 

 

 

 

ABBREVIATIONS:

H=High Level, L=Low Level, X=Don't Care

BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation

NOTES:

1.All entries are valid only when CKE was High during the preceding clock cycle and the current clock cycle.

2.ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of specific bank.

3.Must satisfy bus contention, bus turn around, write recovery requirements.

4.NOP to bank precharging or in idle state. May precharge bank indicated by BA.

5.ILLEGAL if any bank is not idle.

6.Refer to Read with Auto-Precharge in page 27.

7.Refer to Write with Auto-Precharge in page 29.

ILLEGAL = Device operation and/or data-integrity are not guaranteed.

MITSUBISHI ELECTRIC

12

 

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