Microchip Technology Inc 24LC00-I-P, 24LC00-ST, 24LC00-SN, 24LC00-P, 24LC00-OT Datasheet

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M24AA00/24LC00/24C00

128 Bit I2C™ Bus Serial EEPROM

DEVICE SELECTION TABLE

Device

VCC Range

Temp Range

 

 

 

 

 

 

24AA00

1.8 - 6.0

C,I

 

 

 

24LC00

2.5 - 6.0

C,I

 

 

 

24C00

4.5 - 5.5

C,I,E

 

 

 

FEATURES

Low power CMOS technology

-500 A typical active current

-500 nA typical standby current

Organized as 16 bytes x 8 bits

2-wire serial interface bus, I2C™ compatible

100kHz (1.8V) and 400kHz (5V) compatibility

Self-timed write cycle (including auto-erase)

4 ms maximum byte write cycle time

1,000,000 erase/write cycles guaranteed

ESD protection > 4kV

Data retention > 200 years

8L DIP, SOIC, TSSOP and 5L SOT-23 packages

Temperature ranges available:

-

Commercial (C):

0°C

to

+70°C

-

Industrial (I):

-40°C to

+85°C

-

Automotive (E)

-40°C

to

+125°C

DESCRIPTION

The Microchip Technology Inc. 24AA00/24LC00/24C00 (24xx00*) is a 128-bit Electrically Erasable PROM memory organized as 16 x 8 with a 2-wire serial interface. Low voltage design permits operation down to 1.8 volts for the 24xx00 version, and every version maintains a maximum standby current of only 1 A and typical active current of only 500 A. This device was designed where a small amount of EEPROM is needed for the storage of calibration values, ID numbers or manufacturing information, etc. The 24xx00 is available in 8ld PDIP, 8ld SOIC (150 mil), 8ld TSSOP and the 5ld SOT-23 packages.

PACKAGE TYPES

8-PIN PDIP/SOIC

NC

 

1

24xx00

8

 

VCC

 

 

NC

 

2

7

 

NC

 

 

NC

 

3

 

6

 

SCL

 

 

 

VSS

 

4

 

5

 

SDA

 

 

 

 

 

 

 

 

 

 

8-PIN TSSOP

NC

 

 

 

 

1

24xx00

8

 

 

 

 

Vcc

 

 

 

 

 

 

 

 

NC

 

 

 

 

2

7

 

 

 

 

NC

 

 

 

 

 

 

 

NC

 

 

3

 

6

 

 

 

 

SCL

 

 

 

 

 

 

 

 

 

 

 

 

 

Vss

 

 

4

 

5

 

 

 

 

SDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5-PIN SOT-23

SCL

 

1

5

 

VCC

 

 

VSS

 

2

24xx00

 

 

 

 

 

 

SDA

 

3

4

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BLOCK DIAGRAM

 

 

 

 

HV GENERATOR

 

I/O

MEMORY

 

 

CONTROL

CONTROL

XDEC

EEPROM

LOGIC

LOGIC

ARRAY

 

 

 

 

SDA

SCL

 

 

 

 

 

 

 

YDEC

VCC

 

 

 

SENSE AMP

 

 

 

 

VSS

 

 

 

R/W CONTROL

*24xx00 is used in this document as a generic part number for the 24AA00/24LC00/24C00 devices. I2C is a trademark of Philips Corporation.

1996 Microchip Technology Inc.

Preliminary

DS21178A-page 1

Microchip Technology Inc 24LC00-I-P, 24LC00-ST, 24LC00-SN, 24LC00-P, 24LC00-OT Datasheet

24xx00

1.0ELECTRICAL CHARACTERISTICS

1.1Maximum Ratings*

Vcc ...................................................................................

 

7.0V

All inputs and outputs w.r.t. Vss.................

-0.6V to Vcc +1.0V

Storage temperature .....................................

 

-65˚C to +150˚C

Ambient temp. with power applied.................

 

-65˚C to +125˚C

Soldering temperature of leads (10 seconds)

............. +300˚C

ESD protection on all pins................................................

 

4 kV

*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1

PIN FUNCTION TABLE

 

 

Name

Function

 

 

 

 

VSS

Ground

SDA

Serial Data

SCL

Serial Clock

VCC

+1.8V to 6.0V (24AA00)

 

+2.5V to 6.0V (24LC00)

 

+4.5V to 5.5V (24C00)

NC

No Internal Connection

 

 

 

TABLE 1-2

DC CHARACTERISTICS

 

 

 

 

 

 

 

 

 

 

 

 

All Parameters apply across the recom-

Commercial (C): Tamb =

0˚C to +70˚C, Vcc = 1.8V to 6.0V

mended operating ranges unless other-

Industrial (I):

Tamb = -40˚C to +85˚C, Vcc = 1.8V to 6.0V

wise noted

 

Automotive (E) Tamb = -40˚C to +125˚C, Vcc = 4.5V to 5.5V

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

Symbol

 

Min.

 

Max.

Units

Conditions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCL and SDA pins:

 

 

 

 

 

 

 

High level input voltage

VIH

 

.7 VCC

 

 

V

(Note)

Low level input voltage

VIL

 

 

.3 VCC

V

(Note)

Hysteresis of Schmitt trigger inputs

VHYS

 

.05 VCC

 

V

(Note)

Low level output voltage

VOL

 

 

 

.40

V

IOL = 3.0 mA, VCC = VccMIN

 

 

 

 

 

 

 

 

Input leakage current

ILI

 

-10

 

10

A

VIN = 0.1V to 5.5V

 

 

 

 

 

 

 

 

Output leakage current

ILO

 

-10

 

10

A

VOUT = 0.1V to 5.5V

 

 

 

 

 

 

 

 

Pin capacitance (all inputs/outputs)

CIN,

 

 

10

pF

V CC = 5.0V (Note)

 

 

 

COUT

 

 

 

 

 

Tamb = 25˚C, f = 1 MHz

 

 

 

 

 

 

 

 

Operating current

ICC Write

 

 

2

mA

V CC = 5.5V, SCL = 400 kHz

 

 

 

ICC Read

 

 

1

mA

V CC = 5.5V, SCL = 400 kHz

 

 

 

 

 

 

 

 

Standby current

ICCS

 

 

1

A

VCC = 5.5V, SDA = SCL = VCC

 

 

 

 

 

 

 

Note:

This parameter is periodically sampled and not 100% tested.

 

 

FIGURE 1-1: BUS TIMING DATA

 

TF

THIGH

 

TR

 

 

 

 

 

 

 

SCL

TSU:STA

 

 

 

 

 

 

 

 

TLOW

THD:DAT

TSU:DAT

TSU:STO

SDA

THD:STA

 

 

 

IN

 

 

 

TSP

 

 

 

 

 

 

TAA

TBUF

 

 

 

 

SDA

 

 

 

 

OUT

 

 

 

 

DS21178A-page 2

Preliminary

1996 Microchip Technology Inc.

 

 

 

 

 

 

 

 

 

24xx00

 

 

 

 

 

 

 

 

 

 

TABLE 1-3

AC CHARACTERISTICS

 

 

 

 

 

 

 

 

 

 

 

 

All Parameters apply across all

Commercial (C):

Tamb = 0˚C to +70˚C, Vcc = 1.8V to 6.0V

recommended operating ranges

Industrial (I):

 

Tamb = -40˚C to +85˚C, Vcc = 1.8V to 6.0V

unless otherwise noted

Automotive (E):

Tamb = -40˚C to +125˚C, Vcc = 4.5V to 5.5V

 

 

 

 

 

 

 

 

 

Parameter

Symbol

 

 

Min

Max

Units

 

Conditions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock frequency

 

FCLK

 

 

100

kHz

4.5V Vcc 5.5V (E Temp range)

 

 

 

 

 

100

 

1.8V

Vcc 4.5V

 

 

 

 

 

400

 

4.5V

Vcc 6.0V

 

 

 

 

 

 

 

 

 

Clock high time

 

THIGH

 

 

4000

ns

4.5V Vcc 5.5V (E Temp range)

 

 

 

 

 

4000

 

1.8V

Vcc 4.5V

 

 

 

 

 

600

 

4.5V

Vcc 6.0V

 

 

 

 

 

 

 

 

 

Clock low time

 

TLOW

 

 

4700

ns

4.5V Vcc 5.5V (E Temp range)

 

 

 

 

 

4700

 

1.8V

Vcc 4.5V

 

 

 

 

 

1300

 

4.5V

Vcc 6.0V

 

 

 

 

 

 

 

 

SDA and SCL rise time

TR

 

 

1000

ns

4.5V Vcc 5.5V (E Temp range)

(Note 1)

 

 

 

 

1000

 

1.8V

Vcc 4.5V

 

 

 

 

 

300

 

4.5V

Vcc 6.0V

 

 

 

 

 

 

 

 

SDA and SCL fall time

TF

 

 

300

ns

(Note 1)

 

 

 

 

 

 

 

START condition hold time

THD:STA

 

 

4000

ns

4.5V Vcc 5.5V (E Temp range)

 

 

 

 

 

4000

 

1.8V

Vcc 4.5V

 

 

 

 

 

600

 

4.5V

Vcc 6.0V

 

 

 

 

 

 

 

START condition setup time

TSU:STA

 

 

4700

ns

4.5V Vcc 5.5V (E Temp range)

 

 

 

 

 

4700

 

1.8V

Vcc 4.5V

 

 

 

 

 

600

 

4.5V

Vcc 6.0V

 

 

 

 

 

 

 

 

Data input hold time

THD:DAT

 

 

0

ns

(Note 2)

 

 

 

 

 

 

 

 

Data input setup time

TSU:DAT

 

 

250

ns

4.5V Vcc 5.5V (E Temp range)

 

 

 

 

 

250

 

1.8V

Vcc 4.5V

 

 

 

 

 

100

 

4.5V

Vcc 6.0V

 

 

 

 

 

 

 

STOP condition setup time

TSU:STO

 

 

4000

ns

4.5V Vcc 5.5V (E Temp range)

 

 

 

 

 

4000

 

1.8V

Vcc 4.5V

 

 

 

 

 

600

 

4.5V

Vcc 6.0V

 

 

 

 

 

 

 

 

Output valid from clock

TAA

 

 

3500

ns

4.5V Vcc 5.5V (E Temp range)

(Note 2)

 

 

 

 

3500

 

1.8V

Vcc 4.5V

 

 

 

 

 

900

 

4.5V

Vcc 6.0V

 

 

 

 

 

 

 

 

Bus free time: Time the bus must

TBUF

 

 

4700

ns

4.5V Vcc 5.5V (E Temp range)

be free before a new transmission

 

 

 

4700

 

1.8V Vcc 4.5V

can start

 

 

 

 

1300

 

4.5V Vcc 6.0V

 

 

 

 

 

 

 

Output fall time from VIH

TOF

 

20+0.1

250

ns

(Note 1), CB 100 pF

minimum to VIL maximum

 

 

 

CB

 

 

 

 

 

 

 

 

 

 

 

 

Input filter spike suppression

TSP

 

 

50

ns

(Notes 1, 3)

(SDA and SCL pins)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write cycle time

 

TWC

 

 

4

ms

 

 

 

 

 

 

 

 

 

 

 

Endurance

 

 

 

 

1M

cycles

25 °C, VCC = 5.0V, Block Mode (Note 4)

 

 

 

 

 

 

 

 

 

 

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3:The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation.

4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.

1996 Microchip Technology Inc.

Preliminary

DS21178A-page 3

24xx00

2.0PIN DESCRIPTIONS

2.1SDA Serial Data

This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10kΩ for 100 kHz, 1kΩ for 400 kHz).

For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.

2.2SCL Serial Clock

This input is used to synchronize the data transfer from and to the device.

2.3Noise Protection

The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.

3.0FUNCTIONAL DESCRIPTION

The 24xx00 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24xx00 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.

4.0BUS CHARACTERISTICS

The following bus protocol has been defined:

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined (Figure 4-1).

4.1Bus not Busy (A)

Both data and clock lines remain HIGH.

4.2Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

0.1Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

4.3Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited.

4.4Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.

Note: The 24xx00 does not generate any acknowledge bits if an internal programming cycle is in progress.

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition (Figure 4-2).

DS21178A-page 4

Preliminary

1996 Microchip Technology Inc.

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