M24AA00/24LC00/24C00
128 Bit I2C™ Bus Serial EEPROM
DEVICE SELECTION TABLE
Device |
VCC Range |
Temp Range |
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24AA00 |
1.8 - 6.0 |
C,I |
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24LC00 |
2.5 - 6.0 |
C,I |
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24C00 |
4.5 - 5.5 |
C,I,E |
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FEATURES
•Low power CMOS technology
-500 A typical active current
-500 nA typical standby current
•Organized as 16 bytes x 8 bits
•2-wire serial interface bus, I2C™ compatible
•100kHz (1.8V) and 400kHz (5V) compatibility
•Self-timed write cycle (including auto-erase)
•4 ms maximum byte write cycle time
•1,000,000 erase/write cycles guaranteed
•ESD protection > 4kV
•Data retention > 200 years
•8L DIP, SOIC, TSSOP and 5L SOT-23 packages
•Temperature ranges available:
- |
Commercial (C): |
0°C |
to |
+70°C |
- |
Industrial (I): |
-40°C to |
+85°C |
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- |
Automotive (E) |
-40°C |
to |
+125°C |
DESCRIPTION
The Microchip Technology Inc. 24AA00/24LC00/24C00 (24xx00*) is a 128-bit Electrically Erasable PROM memory organized as 16 x 8 with a 2-wire serial interface. Low voltage design permits operation down to 1.8 volts for the 24xx00 version, and every version maintains a maximum standby current of only 1 A and typical active current of only 500 A. This device was designed where a small amount of EEPROM is needed for the storage of calibration values, ID numbers or manufacturing information, etc. The 24xx00 is available in 8ld PDIP, 8ld SOIC (150 mil), 8ld TSSOP and the 5ld SOT-23 packages.
PACKAGE TYPES
8-PIN PDIP/SOIC
NC |
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1 |
24xx00 |
8 |
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VCC |
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NC |
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2 |
7 |
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NC |
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NC |
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3 |
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6 |
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SCL |
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VSS |
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4 |
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5 |
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SDA |
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8-PIN TSSOP
NC |
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1 |
24xx00 |
8 |
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Vcc |
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NC |
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2 |
7 |
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NC |
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NC |
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3 |
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6 |
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SCL |
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Vss |
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4 |
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5 |
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SDA |
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5-PIN SOT-23
SCL |
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1 |
5 |
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VCC |
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VSS |
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2 |
24xx00 |
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SDA |
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3 |
4 |
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NC |
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BLOCK DIAGRAM
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HV GENERATOR |
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I/O |
MEMORY |
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CONTROL |
CONTROL |
XDEC |
EEPROM |
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LOGIC |
LOGIC |
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ARRAY |
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SDA |
SCL |
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YDEC |
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VCC |
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SENSE AMP |
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VSS |
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R/W CONTROL |
*24xx00 is used in this document as a generic part number for the 24AA00/24LC00/24C00 devices. I2C is a trademark of Philips Corporation.
1996 Microchip Technology Inc. |
Preliminary |
DS21178A-page 1
24xx00
1.0ELECTRICAL CHARACTERISTICS
Vcc ................................................................................... |
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7.0V |
All inputs and outputs w.r.t. Vss................. |
-0.6V to Vcc +1.0V |
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Storage temperature ..................................... |
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-65˚C to +150˚C |
Ambient temp. with power applied................. |
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-65˚C to +125˚C |
Soldering temperature of leads (10 seconds) |
............. +300˚C |
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ESD protection on all pins................................................ |
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4 kV |
*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-1 |
PIN FUNCTION TABLE |
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Name |
Function |
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VSS |
Ground |
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SDA |
Serial Data |
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SCL |
Serial Clock |
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VCC |
+1.8V to 6.0V (24AA00) |
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+2.5V to 6.0V (24LC00) |
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+4.5V to 5.5V (24C00) |
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NC |
No Internal Connection |
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TABLE 1-2 |
DC CHARACTERISTICS |
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All Parameters apply across the recom- |
Commercial (C): Tamb = |
0˚C to +70˚C, Vcc = 1.8V to 6.0V |
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mended operating ranges unless other- |
Industrial (I): |
Tamb = -40˚C to +85˚C, Vcc = 1.8V to 6.0V |
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wise noted |
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Automotive (E) Tamb = -40˚C to +125˚C, Vcc = 4.5V to 5.5V |
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Parameter |
Symbol |
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Min. |
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Max. |
Units |
Conditions |
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SCL and SDA pins: |
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High level input voltage |
VIH |
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.7 VCC |
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V |
(Note) |
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Low level input voltage |
VIL |
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.3 VCC |
V |
(Note) |
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Hysteresis of Schmitt trigger inputs |
VHYS |
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.05 VCC |
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— |
V |
(Note) |
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Low level output voltage |
VOL |
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.40 |
V |
IOL = 3.0 mA, VCC = VccMIN |
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Input leakage current |
ILI |
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-10 |
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10 |
A |
VIN = 0.1V to 5.5V |
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Output leakage current |
ILO |
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-10 |
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10 |
A |
VOUT = 0.1V to 5.5V |
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Pin capacitance (all inputs/outputs) |
CIN, |
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— |
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10 |
pF |
V CC = 5.0V (Note) |
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COUT |
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Tamb = 25˚C, f = 1 MHz |
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Operating current |
ICC Write |
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— |
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2 |
mA |
V CC = 5.5V, SCL = 400 kHz |
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ICC Read |
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— |
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1 |
mA |
V CC = 5.5V, SCL = 400 kHz |
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Standby current |
ICCS |
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— |
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1 |
A |
VCC = 5.5V, SDA = SCL = VCC |
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Note: |
This parameter is periodically sampled and not 100% tested. |
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FIGURE 1-1: BUS TIMING DATA
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TF |
THIGH |
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TR |
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SCL |
TSU:STA |
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TLOW |
THD:DAT |
TSU:DAT |
TSU:STO |
SDA |
THD:STA |
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IN |
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TSP |
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TAA |
TBUF |
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SDA |
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OUT |
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DS21178A-page 2 |
Preliminary |
1996 Microchip Technology Inc. |
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24xx00 |
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TABLE 1-3 |
AC CHARACTERISTICS |
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All Parameters apply across all |
Commercial (C): |
Tamb = 0˚C to +70˚C, Vcc = 1.8V to 6.0V |
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recommended operating ranges |
Industrial (I): |
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Tamb = -40˚C to +85˚C, Vcc = 1.8V to 6.0V |
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unless otherwise noted |
Automotive (E): |
Tamb = -40˚C to +125˚C, Vcc = 4.5V to 5.5V |
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Parameter |
Symbol |
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Min |
Max |
Units |
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Conditions |
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Clock frequency |
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FCLK |
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— |
100 |
kHz |
4.5V ≤ Vcc ≤ 5.5V (E Temp range) |
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— |
100 |
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1.8V |
≤ Vcc ≤ 4.5V |
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— |
400 |
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4.5V |
≤ Vcc ≤ 6.0V |
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Clock high time |
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THIGH |
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4000 |
— |
ns |
4.5V ≤ Vcc ≤ 5.5V (E Temp range) |
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4000 |
— |
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1.8V |
≤ Vcc ≤ 4.5V |
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600 |
— |
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4.5V |
≤ Vcc ≤ 6.0V |
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Clock low time |
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TLOW |
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4700 |
— |
ns |
4.5V ≤ Vcc ≤ 5.5V (E Temp range) |
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4700 |
— |
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1.8V |
≤ Vcc ≤ 4.5V |
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1300 |
— |
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4.5V |
≤ Vcc ≤ 6.0V |
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SDA and SCL rise time |
TR |
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— |
1000 |
ns |
4.5V ≤ Vcc ≤ 5.5V (E Temp range) |
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(Note 1) |
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— |
1000 |
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1.8V |
≤ Vcc ≤ 4.5V |
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— |
300 |
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4.5V |
≤ Vcc ≤ 6.0V |
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SDA and SCL fall time |
TF |
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— |
300 |
ns |
(Note 1) |
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START condition hold time |
THD:STA |
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4000 |
— |
ns |
4.5V ≤ Vcc ≤ 5.5V (E Temp range) |
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4000 |
— |
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1.8V |
≤ Vcc ≤ 4.5V |
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600 |
— |
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4.5V |
≤ Vcc ≤ 6.0V |
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START condition setup time |
TSU:STA |
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4700 |
— |
ns |
4.5V ≤ Vcc ≤ 5.5V (E Temp range) |
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4700 |
— |
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1.8V |
≤ Vcc ≤ 4.5V |
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600 |
— |
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4.5V |
≤ Vcc ≤ 6.0V |
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Data input hold time |
THD:DAT |
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0 |
— |
ns |
(Note 2) |
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Data input setup time |
TSU:DAT |
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250 |
— |
ns |
4.5V ≤ Vcc ≤ 5.5V (E Temp range) |
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250 |
— |
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1.8V |
≤ Vcc ≤ 4.5V |
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100 |
— |
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4.5V |
≤ Vcc ≤ 6.0V |
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STOP condition setup time |
TSU:STO |
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4000 |
— |
ns |
4.5V ≤ Vcc ≤ 5.5V (E Temp range) |
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4000 |
— |
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1.8V |
≤ Vcc ≤ 4.5V |
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600 |
— |
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4.5V |
≤ Vcc ≤ 6.0V |
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Output valid from clock |
TAA |
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— |
3500 |
ns |
4.5V ≤ Vcc ≤ 5.5V (E Temp range) |
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(Note 2) |
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— |
3500 |
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1.8V |
≤ Vcc ≤ 4.5V |
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— |
900 |
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4.5V |
≤ Vcc ≤ 6.0V |
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Bus free time: Time the bus must |
TBUF |
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4700 |
— |
ns |
4.5V ≤ Vcc ≤ 5.5V (E Temp range) |
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be free before a new transmission |
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4700 |
— |
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1.8V ≤ Vcc ≤ 4.5V |
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can start |
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1300 |
— |
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4.5V ≤ Vcc ≤ 6.0V |
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Output fall time from VIH |
TOF |
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20+0.1 |
250 |
ns |
(Note 1), CB ≤ 100 pF |
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minimum to VIL maximum |
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CB |
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Input filter spike suppression |
TSP |
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— |
50 |
ns |
(Notes 1, 3) |
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(SDA and SCL pins) |
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Write cycle time |
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TWC |
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— |
4 |
ms |
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Endurance |
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1M |
— |
cycles |
25 °C, VCC = 5.0V, Block Mode (Note 4) |
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Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3:The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation.
4:This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.
1996 Microchip Technology Inc. |
Preliminary |
DS21178A-page 3
24xx00
This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10kΩ for 100 kHz, 1kΩ for 400 kHz).
For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.
This input is used to synchronize the data transfer from and to the device.
The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.
The 24xx00 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24xx00 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.
The following bus protocol has been defined:
•Data transfer may be initiated only when the bus is not busy.
•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been defined (Figure 4-1).
Both data and clock lines remain HIGH.
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited.
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.
Note: The 24xx00 does not generate any acknowledge bits if an internal programming cycle is in progress.
The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition (Figure 4-2).
DS21178A-page 4 |
Preliminary |
1996 Microchip Technology Inc. |