MXIC MX29LV400BHI-70, MX29LV400BHI-90, MX29LV400BMC-55R, MX29LV400BMC-70, MX29LV400BMC-90 Datasheet

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MX29LV400T/B

4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE 3VONLYFLASHMEMORY

FEATURES

Extended single - supply voltage range 2.7V to 3.6V

524,288 x 8/262,144 x 16 switchable

Single power supply operation

-3.0V only operation for read, erase and program operation

Fast access time: 55R/70/90ns

Low power consumption

-20mA maximum active current

-0.2uA typical standby current

Command register architecture

-Byte/word Programming (9us/11us typical)

-Sector Erase (Sector structure 16K-Byte x 1,

8K-Byte x 2, 32K-Byte x1, and 64K-Byte x7)

Auto Erase (chip & sector) and Auto Program

-Automatically erase any combination of sectors with Erase Suspend capability.

-Automatically program and verify data at specified address

Erase suspend/Erase Resume

-Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase.

GENERAL DESCRIPTION

Status Reply

-Data polling & Toggle bit for detection of program and erase operation completion.

Ready/Busy pin (RY/BY)

-Provides a hardware method of detecting program or erase operation completion.

Sector protection

-Hardware method to disable any combination of sectors from program or erase operations

-Tempoary sector unprotect allows code changes in previously locked sectors.

100,000 minimum erase/program cycles

Latch-up protected to 100mA from -1V to VCC+1V

Boot Sector Architecture

-T = Top Boot Sector

-B = Bottom Boot Sector

Low VCC write inhibit is equal to or less than 2.3V

Package type:

-44-pin SOP

-48-pin TSOP

-48-ball CSP

Compatibility with JEDEC standard

-Pinout and software compatible with single-power supply Flash

The MX29LV400T/B is a 4-mega bit Flash memory organized as 512K bytes of 8 bits or 256K words of 16 bits. MXIC's Flash memories offer the most cost-effec- tive and reliable read/write non-volatile random access memory. The MX29LV400T/B is packaged in 44-pin SOP, 48-pin TSOP and 48-ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.

The standard MX29LV400T/B offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29LV400T/B has separate chip enable (CE) and output enable (OE) controls.

MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV400T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.

MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The MX29LV400T/B uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.

The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.

P/N:PM0710

REV. 1.4, NOV. 23, 2001

1

MX29LV400T/B

PIN CONFIGURATIONS

PIN DESCRIPTION

44 SOP(500 mil)

NC

RY/BY 2

A17 3

A7 4

A6 5

A5 6

A4 7

A3 8

A2 9

A1 10

A0 11

CE 12

GND 13

OE 14

Q0 15

Q8 16

Q1 17

Q9 18

Q2 19

Q10 20

Q3 21

Q11 22

MX29LV400T/B

44

 

 

 

 

RESET

 

 

 

 

 

43

 

 

 

 

 

 

 

 

 

WE

 

42

 

 

 

 

A8

41

 

 

 

 

A9

40

 

 

 

 

A10

39

 

 

 

 

A11

38

 

 

 

 

A12

37

 

 

 

 

A13

36

 

 

 

 

A14

35

 

 

 

 

A15

34

 

 

 

 

A16

33

 

 

 

 

 

 

 

 

 

 

 

BYTE

32

 

 

 

 

GND

31

 

 

 

 

Q15/A-1

 

 

30

 

 

 

 

Q7

 

 

29

 

 

 

 

Q14

 

 

28

 

 

 

 

Q6

 

 

 

27

 

 

 

 

Q13

 

 

 

26

 

 

 

 

Q5

 

 

 

25

 

 

 

 

Q12

 

 

 

24

 

 

 

 

Q4

 

 

 

23

 

 

 

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYMBOL

PIN NAME

 

 

 

 

 

 

 

 

 

 

 

 

A0~A17

Address Input

 

 

 

 

 

 

 

 

 

 

 

 

Q0~Q14

Data Input/Output

 

 

 

 

 

 

 

 

 

 

 

Q15/A-1 Q15(Word mode)/LSB addr(Byte mode)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip Enable Input

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

Write Enable Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Word/Byte Selction input

 

 

BYTE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

Hardware Reset Pin/Sector Protect Unlock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

Output Enable Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ready/Busy Output

 

 

RY/BY

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

Power Supply Pin (2.7V~3.6V)

 

 

 

 

 

 

 

 

 

 

 

 

GND

Ground Pin

 

 

 

 

 

 

 

 

 

 

48 TSOP (Standard Type) (12mm x 20mm)

A15

 

1

 

48

 

 

A16

 

 

 

 

47

 

 

 

 

A14

 

2

 

 

 

BYTE

A13

 

3

 

46

 

 

GND

A12

 

4

 

45

 

 

Q15/A-1

A11

 

5

 

44

 

 

Q7

A10

 

6

 

43

 

 

Q14

 

 

A9

 

7

 

42

 

 

Q6

 

 

A8

 

8

 

41

 

 

Q13

 

NC

 

9

 

40

 

 

Q5

 

NC

 

10

 

39

 

 

Q12

 

 

 

 

 

 

 

11

 

38

 

 

Q4

 

WE

 

 

 

 

 

 

 

 

12

 

37

 

 

VCC

RSEET

 

 

 

MX29LV400T/B

 

 

 

 

 

NC

 

13

 

36

 

 

Q11

 

 

 

 

NC

 

14

 

35

 

 

Q3

 

 

 

 

 

 

 

15

 

34

 

 

Q10

RY/BY

 

 

 

 

 

 

 

 

NC

 

16

 

33

 

 

Q2

 

 

 

A17

 

17

 

32

 

 

Q9

 

 

 

 

 

 

A7

 

18

 

31

 

 

Q1

 

 

 

 

 

 

 

A6

 

19

 

30

 

 

Q8

 

 

 

 

 

 

 

A5

 

20

 

29

 

 

Q0

 

 

 

 

 

 

 

A4

 

21

 

28

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

A3

 

22

 

27

 

 

GND

 

 

 

 

 

 

 

 

A2

 

23

 

26

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

24

 

25

 

 

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

48-Ball CSP(6mm x 8mm,ball pitch=0.8mm),Top View, Balls Facing Down for MX29LV400TXB/BXB/TXE/BXE

 

A

 

B

C

D

E

 

F

 

G

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

A13

 

A12

A14

A15

A16

 

BYTE

 

Q15/A-1

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

A9

 

A8

A10

A11

Q7

 

Q14

 

Q13

Q6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

WE

 

RESET

NC

NC

Q5

 

Q12

 

Vcc

Q4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

 

 

NC

NC

NC

Q2

 

Q10

 

Q11

Q3

 

RY/BY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

A7

 

A17

A6

A5

Q0

 

Q8

 

Q9

Q1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

A3

 

A4

A2

A1

A0

 

CE

 

 

OE

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P/N:PM0710

 

 

 

 

 

 

 

 

 

 

 

 

 

REV. 1.4, NOV. 23, 2001

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

MX29LV400T/B

BLOCK STRUCTURE

Table 1: MX29LV400T SECTOR ARCHITECTURE

Sector

Sector Size

Address range

 

 

Sector Address

 

 

Byte Mode

Word Mode

Byte Mode (x8)

Word Mode (x16)

A17

A16

A15

A14

A13

A12

 

 

 

 

 

 

 

 

 

 

 

SA0

64Kbytes

32Kwords

00000-0FFFF

00000-07FFF

0

0

0

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA1

64Kbytes

32Kwords

10000-1FFFF

08000-0FFFF

0

0

1

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA2

64Kbytes

32Kwords

20000-2FFFF

10000-17FFF

0

1

0

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA3

64Kbytes

32Kwords

30000-3FFFF

18000-1FFFF

0

1

1

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA4

64Kbytes

32Kwords

40000-4FFFF

20000-27FFF

1

0

0

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA5

64Kbytes

32Kwords

50000-5FFFF

28000-2FFFF

1

0

1

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA6

64Kbytes

32Kwords

60000-6FFFF

30000-37FFF

1

1

0

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA7

32Kbytes

16Kwords

70000-77FFF

38000-3BFFF

1

1

1

0

X

X

 

 

 

 

 

 

 

 

 

 

 

SA8

8Kbytes

4Kwords

78000-79FFF

3C000-3CFFF

1

1

1

1

0

0

 

 

 

 

 

 

 

 

 

 

 

SA9

8Kbytes

4Kwords

7A000-7BFFF

3D000-3DFFF

1

1

1

1

0

1

 

 

 

 

 

 

 

 

 

 

 

SA10

16Kbytes

8Kwords

7C000-7FFFF

3E000-3FFFF

1

1

1

1

1

X

 

 

 

 

 

 

 

 

 

 

 

Note: Byte mode:address range A17:A-1, word mode:address range A17:A0.

Table 2: MX29LV400B SECTOR ARCHITECTURE

Sector

Sector Size

Address range

 

 

Sector Address

 

 

Byte Mode

Word Mode

Byte Mode (x8)

Word Mode (x16)

A17

A16

A15

A14

A13

A12

 

 

 

 

 

 

 

 

 

 

 

SA0

16Kbytes

8Kwords

00000-03FFF

00000-01FFF

0

0

0

0

0

X

 

 

 

 

 

 

 

 

 

 

 

SA1

8Kbytes

4Kwords

04000-05FFF

02000-02FFF

0

0

0

0

1

0

 

 

 

 

 

 

 

 

 

 

 

SA2

8Kbytes

4Kwords

06000-07FFF

03000-03FFF

0

0

0

0

1

1

 

 

 

 

 

 

 

 

 

 

 

SA3

32Kbytes

16Kwords

08000-0FFFF

04000-07FFF

0

0

0

1

X

X

 

 

 

 

 

 

 

 

 

 

 

SA4

64Kbytes

32Kwords

10000-1FFFF

08000-0FFFF

0

0

1

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA5

64Kbytes

32Kwords

20000-2FFFF

10000-17FFF

0

1

0

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA6

64Kbytes

32Kwords

30000-3FFFF

18000-1FFFF

0

1

1

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA7

64Kbytes

32Kwords

40000-4FFFF

20000-27FFF

1

0

0

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA8

64Kbytes

32Kwords

50000-5FFFF

28000-2FFFF

1

0

1

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA9

64Kbytes

32Kwords

60000-6FFFF

30000-37FFF

1

1

0

X

X

X

 

 

 

 

 

 

 

 

 

 

 

SA10

64Kbytes

32Kwords

70000-7FFFF

38000-3FFFF

1

1

1

X

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: Byte mode:address range A17:A-1, word mode:address range A17:A0.

P/N:PM0710

REV. 1.4, NOV. 23, 2001

3

MXIC MX29LV400BHI-70, MX29LV400BHI-90, MX29LV400BMC-55R, MX29LV400BMC-70, MX29LV400BMC-90 Datasheet

MX29LV400T/B

BLOCK DIAGRAM

CE

CONTROL

PROGRAM/ERASE

WRITE

STATE

OE

INPUT

HIGH VOLTAGE

 

WE

LOGIC

 

MACHINE

 

 

 

 

RESET

 

 

 

 

(WSM)

 

 

 

 

 

 

 

 

 

 

 

 

STATE

 

 

 

MX29LV400T/B

 

REGISTER

 

ADDRESS

 

 

 

 

 

 

LATCH

 

FLASH

ARRAY

 

A0-A17

 

 

ARRAY

SOURCE

 

AND

X-DECODER-Y

 

COMMAND

 

 

HV

 

BUFFER

DECODER

 

 

 

DATA

 

Y-PASS GATE

 

DECODER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SENSE

PGM

 

COMMAND

 

 

 

DATA

 

 

 

AMPLIFIER

 

 

 

HV

 

DATA LATCH

 

 

 

 

 

 

 

 

 

 

PROGRAM

 

 

 

 

 

 

DATA LATCH

 

 

 

Q0-Q15/A-1

 

I/O BUFFER

 

 

P/N:PM0710

 

 

 

 

 

REV. 1.4, NOV. 23, 2001

 

 

 

4

 

 

 

MX29LV400T/B

AUTOMATIC PROGRAMMING

The MX29LV400T/B is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV400T/B is less than 10 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 25 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29LV400T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. An erase operation can erase one sector, multiple sectors, or the entire device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the program verification, and counts the number of sequences. The device provides an unlock bypass mode with faster programming. Only two write cycles are needed to program a word or byte, instead of four. A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. Refer to write operation status, table7, for more information on these status bits.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the status of the erasing operation.

Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE or CE, whichever happens first.

MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reliability, and cost effectiveness.The MX29LV400T/B electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection.

During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command register to respond to its full command set.

AUTOMATIC SELECT

The automatic select mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on Q7~Q0.This mode is mainly adapted for programming equipment on the device to be programmed with its programming algorithm. When programming by high voltage method, automatic select mode requires VID (11.5V to 12.5V) on address pin A9 and other address pin A6, A1 as referring to Table 3. In addition, to access the automatic select codes insystem, the host can issue the automatic select com-

P/N:PM0710

REV. 1.4, NOV. 23, 2001

5

MX29LV400T/B

mand through the command register without requiring VID, as shown in table4.

To verify whether or not sector being protected, the sector address must appear on the appropriate highest order address bit (see Table 1 and Table 2). The rest of address bits, as shown in table3, are don't care. Once all necessary bits have been set as required, the programming equipment may read the corresponding identifier code on Q7~Q0.

TABLE 3. MX29LV400T/B AUTOSELECT MODE OPERATION

 

 

 

 

 

 

 

 

 

 

A17 A11 A9

A8

A6

A5

A1

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Description

Mode

CE

 

OE

 

WE RESET

|

|

 

|

 

|

 

 

Q15~Q0

 

 

 

 

 

 

 

 

 

 

A12 A10

 

A7

 

A2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Silicon ID

 

L

 

L

 

H

 

H

X

X

VID

X

L

X

L

L

C2H

Manfacturer Code

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Silicon ID

Word

L

 

L

 

H

 

H

X

X

VID

X

L

X

L

H

22B9H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(Top Boot Block)

Byte

L

 

L

 

H

 

H

X

X

VID

X

L

X

L

H

XXB9H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device ID

Word

L

 

L

 

H

 

H

X

X

VID

X

L

X

L

H

22BAH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(Bottom Boot Block)

Byte

L

 

L

 

H

 

H

X

X

VID

X

L

X

L

H

XXBAH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XX01H

Sector Protection

 

L

 

L

 

H

 

H

SA

X

VID

X

L

X

H

L

(protected)

Verification

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XX00H

(unprotected)

NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High

P/N:PM0710

REV. 1.4, NOV. 23, 2001

6

MX29LV400T/B

TABLE 4. MX29LV400T/B COMMAND DEFINITIONS

 

 

 

First Bus

Second Bus

Third Bus

Fourth Bus

Fifth Bus

Sixth Bus

Command

 

Bus

Cycle

 

Cycle

 

Cycle

 

Cycle

 

Cycle

 

Cycle

 

 

 

Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

1

XXXH

F0H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

 

1

RA

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Silicon ID

Word

4

555H

AAH

2AAH

55H

555H

90H

ADI

DDI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte

4

AAAH

AAH

555H

55H

AAAH

90H

ADI

DDI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sector Protect

Word

4

555H

AAH

2AAH

55H

555H

90H

(SA)

XX00H

 

 

 

 

Verify

 

 

 

 

 

 

 

 

x02H

XX01H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte

4

AAAH

AAH

555H

55H

AAAH

90H

(SA)

00H

 

 

 

 

 

 

 

 

 

 

 

 

 

x04H

01H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Porgram

Word

4

555H

AAH

2AAH

55H

555H

A0H

PA

PD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte

4

AAAH

AAH

555H

55H

AAAH

A0H

PA

PD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip Erase

Word

6

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

555H

10H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte

6

AAAH

AAH

555H

55H

AAAH

80H

AAAH

AAH

555H

55H

AAAH

10H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sector Erase

Word

6

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH

55H

SA

30H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte

6

AAAH

AAH

555H

55H

AAAH

80H

AAAH

AAH

555H

55H

SA

30H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sector Erase Suspend

1

XXXH

B0H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sector Erase Resume

1

XXXH

30H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

1.ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A17=do not care. (Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, B9H/BAH (x8) and 22B9H/22BAH (x16) for device code. X = X can be VIL or VIH

RA=Address of memory location to be read. RD=Data to be read at location RA.

2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA.

SA = Address of the sector to be erased.

3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or 555H to Address A10~A-1 in byte mode.

Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A17 in either state.

4.For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00H, it means the sector is still not being protected.

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MX29LV400T/B

COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 4 defines the valid register command

TABLE 5. MX29LV400T/B BUS OPERATION

sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDRESS

 

 

 

 

 

Q8~Q15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DESCRIPTION

 

CE

OE

 

WE

RESET

A17

A10

A9

A8

A6

A5

A1

A0

Q0~Q7

BYTE

BYTE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A11

 

 

A7

 

A2

 

 

 

=VIH

=VIL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

 

L

 

L

 

H

H

 

 

 

 

AIN

 

 

 

 

 

Dout

Dout

Q8~Q14=High Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q15=A-1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write

 

L

 

H

 

L

H

 

 

 

 

AIN

 

 

 

 

 

DIN(3)

DIN

Q8~Q14=High Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q15=A-1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

X

 

X

 

X

L

 

 

 

 

X

 

 

 

 

 

High Z

High Z

High Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Temproary sector unlock

 

X

 

X

 

X

VID

 

 

 

 

AIN

 

 

 

 

 

DIN

DIN

High Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Disable

 

L

 

H

 

H

H

 

 

 

 

X

 

 

 

 

 

High Z

High Z

High Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Standby

Vcc±

 

X

 

X

Vcc±

 

 

 

 

X

 

 

 

 

 

High Z

High Z

High Z

 

0.3V

 

 

 

 

 

 

0.3V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sector Protect

 

L

 

H

 

L

VID

SA

X

X

X

L

X

H

L

DIN

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip Unprotect

 

L

 

H

 

L

VID

X

X

X

X

H

X

H

L

DIN

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sector Protection Verify

 

L

 

L

 

H

H

SA

X

VID

X

L

X

H

L

CODE(5)

X

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTES:

1.Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.

2.VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3.Refer to Table 4 for valid Data-In during a write operation.

4.X can be VIL or VIH.

5.Code=00H/XX00H means unprotected. Code=01H/XX01H means protected.

6.A17~A12=Sector address for sector protect.

7.The sector protect and chip unprotect functions may also be implemented via programming equipment.

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8

MX29LV400T/B

REQUIREMENTS FOR READING ARRAY DATA

To read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory contect occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs.The device remains enabled for read access until the command register contents are altered.

WRITE COMMANDS/COMMAND

SEQUENCES

To program data to the device or erase sectors of memory , the sysytem must drive WE and CE to VIL, and OE to VIH.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The "byte Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors , or the entire device.Table indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences.Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data."section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal reqister (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode.

Refer to the Autoselect Mode and Autoselect Command Sequence section for more information.

ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations.

STANDBY MODE

When using both pins of CE and RESET, the device enter CMOS Standby with both pins held at Vcc ± 0.3V. IF CE and RESET are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby currect will be larger. During Auto Algorithm operation, Vcc active current (Icc2) is required even CE = "H" until the operation is complated. The device can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data.

OUTPUT DISABLE

With the OE input at a logic high level (VIH), output from the devices are disabled.This will cause the output pins to be in a high impedance state.

RESET OPERATION

The RESET pin provides a hardware method of resetting the device to reading array data.When the RESET pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET pluse. The device also resets the internal state machine to reading array data.The operation that was interrupted should be reinitated once the device is ready to accept another command sequence, to ensure data integrity

Current is reduced for the duration of the RESET pulse. When RESET is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS±0.3V, the standby current will be greater.

The RESET pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firm-ware from

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9

MX29LV400T/B

the Flash memory.

If RESET is asserted during a program or erase operation, the RY/BY pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The sysytem can thus monitor RY/BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase operation is commpleted within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET pin returns to VIH.

Refer to the AC Characteristics tables for RESET parameters and to Figure 24 for the timing diagram.

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered.

If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state.

SILICON-ID READ COMMAND

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage(VID). However, multiplexing high voltage onto address lines is not generally desired system design practice.

The MX29LV400T/B contains a Silicon-ID-Read operation to supple traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of B9H/22B9H for MX29LV400T, BAH/22BAH for MX29LV400B.

SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS

Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H or sector erase command 30H.

The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.

When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verification command is required).

If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 7), indicating the erase operation exceed internal timing limit.

The automatic erase begins on the rising edge of the last WE or CE pulse, whichever happens first in the command sequence and terminates when the data on Q7 is "1" at which time the device returns to the Read mode, or the data on Q6 stops toggling for two consecutive read cycles at which time the device returns to the Read mode.

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MX29LV400T/B

TABLE 6. EXPANDED SILICON ID CODE

Pins

 

A0

A1

Q15~Q8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Code(Hex)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Manufacture code

Word

VIL

VIL

00H

1

1

0

0

0

0

1

0

00C2H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte

VIL

VIL

X

1

1

0

0

0

0

1

0

C2H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device code

Word

VIH

VIL

22H

1

0

1

1

1

0

0

1

22B9H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

for MX29LV400T

Byte

VIH

VIL

X

1

0

1

1

1

0

0

1

B9H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device code

Word

VIH

VIL

22H

1

0

1

1

1

0

1

0

22BAH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

for MX29LV400B

Byte

VIH

VIL

X

1

0

1

1

1

0

1

0

BAH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sector Protection

 

X

VIH

X

0

0

0

0

0

0

0

1

01H

(Protected)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Verification

 

X

VIH

X

0

0

0

0

0

0

0

0

00H

(Unprotected)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READING ARRAY DATA

The device is automatically set to reading array data after device power-up. No commands are required to retrieve data.The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See rase Suspend/Erase Resume Commands” for more infor-mation on this mode. The system must issue the reset command to re-en- able the device for reading array data if Q5 goes high, or while in the autoselect mode. See the "Reset Command" section, next.

RESET COMMAND

Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command sequence be-fore programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins,however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an SILICON ID READ command sequence. Once in the SILICON ID READ mode, the reset command must be written to return to reading array data (also applies to SILICON ID READ during Erase Suspend).

If Q5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

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11

MX29LV400T/B

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Sector Erase Set-up command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations.

When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when either the data on Q7 is "1" at which time the device returns to the Read mode, or the data on Q6 stops toggling for two consecutive read cycles at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.

When using the Automatic sector Erase algorithm, note that the erase automatically terminates when adequate

Table 7.Write Operation Status

erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the setup command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE or CE, whichever happens later, while the command(data) is latched on the rising edge of WE or CE, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE or CE, whichever happens later. Each successive sector load cycle started by the falling edge of WE or CE, whichever happens later must begin within 50us from the rising edge of the preceding WE or CE, whichever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Status

 

 

Q7

Q6

Q5

Q3

Q2

RY/BY

 

 

 

(Note1)

 

(Note2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte Program in Auto Program Algorithm

 

 

 

Toggle

0

N/A

No

0

 

 

 

Q7

 

 

 

 

 

 

 

 

 

 

 

 

 

Toggle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Auto Erase Algorithm

 

0

 

 

Toggle

0

1

Toggle

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Erase Suspend Read

1

 

 

No

0

N/A

Toggle

1

 

In Progress

 

(Erase Suspended Sector)

 

 

 

 

Toggle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Erase Suspended Mode

Erase Suspend Read

Data

Data

Data

Data

Data

1

 

 

 

 

 

(Non-Erase Suspended Sector)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Erase Suspend Program

 

 

Toggle

0

N/A

N/A

0

 

 

 

 

Q7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte Program in Auto Program Algorithm

 

 

Toggle

1

N/A

No

0

 

 

 

Q7

 

 

Exceeded

 

 

 

 

 

 

 

 

 

Toggle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Time Limits

Auto Erase Algorithm

 

0

 

 

Toggle

1

1

Toggle

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Erase Suspend Program

 

 

 

Toggle

1

N/A

N/A

0

 

 

 

 

Q7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

1.Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2.Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information.

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12

MX29LV400T/B

ERASE SUSPEND

This command only has meaning while the state machine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20us to suspend the erase operations.However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands.

The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing.

AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Program mode, A three-cycle command sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Program command A0H.

Once the Automatic Program command is initiated, the next WE pulse causes a transition to an active programming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE or CE, whichever happens first. The rising edge of WE or CE, whichever happens first, also begins the programming operation. The system is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin.

The device provides Q2, Q3, Q5, Q6, Q7, and RY/BY to determine the status of a write operation. If the program operation was unsuccessful, the data on Q5 is "1"(see Table 7), indicating the program operation exceed internal timing limit.The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode(no program verify command is required).

WORD/BYTE PROGRAM COMMAND SEQUENCE

The device programs one byte of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 1 shows the address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Q7, Q6, or RY/BY. See "Write Operation Status" for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operat ion.The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the

operation and set Q5 to "1" ,” or cause the Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".

WRITE OPERSTION STATUS

The device provides several bits to determine the sta- tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/ BY.Table 10 and the following subsections describe the

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functions of these bits. Q7, RY/BY, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.

Q7: Data Polling

The Data Polling bit, Q7, indicates to the host sys-tem whether an Automatic Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data Polling is valid after the rising edge of the final WE pulse in the program or erase command sequence.

During the Automatic Program algorithm, the device outputs on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to programming during Er ase Suspend.When the Automatic Program algorithm is complete, the device outputs the datum programmed to Q7. The system must provide the program address to read valid status information on Q7. If a program address falls within a protected sector, Data Polling on Q7 is active for approximately 1 us, then the device returns to reading array data.

During the Automatic Erase algorithm, Data Polling produces a "0" on Q7. When the Automatic Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data Polling produces a "1" on Q7. This is analogous to the complement/true datum out-put described for the Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement,” or "0".” The system must provide an address within any of the sectors selected for erasure to read valid status information on Q7.

After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on Q7 is active for approximately 100 us, then the device returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchr onously with Q0-Q6 while Output Enable (OE) is asserted low.

RY/BY:Ready/Busy

The RY/BY is a dedicated, open-drain output pin that indicates whether an Automatic Erase/Program algorithm is in progress or complete. The RY/BY status is valid after the rising edge of the final WE or CE, whichever happens first, in the command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to Vcc.

If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

Table 7 shows the outputs for RY/BY during write operation.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, whichever happens first, in the command sequence(prior to the program or erase operation), and during the sector timeout.

During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles.When the operation is complete, Q6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.

The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase suspended.When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-sus- pended. Alternatively, the system can use Q7.

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If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program command sequence is written, then returns to reading array data.

Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete.

Table 7 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively eraseing (that is, the Automatic Erase alorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE or CE, whichever happens first, in the command sequence.

Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 7 to compare outputs for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device has successfuly completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.

Q5

Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition.

If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device.

If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad.

If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector maynot be reused, (other sectors are still functional and can be reused).

The time-out condition will not appear if a user tries to program a non blank location without erasing. Please note that this is not a device failure condition since the device was incorrectly used.

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Q3

Sector Erase Timer

After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence.

If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted.

DATA PROTECTION

The MX29LV400T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting fromVCC power-up and power-down transition or system noise.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND.

POWER-UP SEQUENCE

The MX29LV400T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences.

TEMPORARY SECTOR UNPROTECT

This feature allows temporary unprotection of previously protected sector to change data in-system.The Tempo- rary Sector Unprotect mode is activated by setting the RESET pin to VID(11.5V-12.5V). During this mode, formerly protected sectors can be programmed or erased as un-protected sector. Once VID is remove from the RESET pin,all the previously protected sectors are protected again.

SECTOR PROTECTION

The MX29LV400T/B features hardware sector protection. This feature will disable both program and erase operations for these sectors protected. To activate this mode, the programming equipment must force VID on address pin A9 and OE (suggest VID = 12V). Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform.

To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses,except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes.(Read Silicon ID)

It is also possible to determine if the sector is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector.

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CHIP UNPROTECT

The MX29LV400T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode.

To activate this mode, the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE pulse and is terminated on the rising edge.

It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector.

It is noted that all sectors are unprotected after the chip unprotect algorithm is completed.

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ABSOLUTE MAXIMUM RATINGS

Storage Temperature

 

Plastic Packages . . . . . . . . . . . . .

..... -65oC to +150oC

Ambient Temperature

 

with Power Applied. . . . . . . . . . . . .

.... -65oC to +125oC

Voltage with Respect to Ground

 

 

VCC (Note 1) . . . . . . . . . . . . . . . . .

-0.5 V to +4.0 V

 

 

 

 

 

 

 

A9, OE, and

 

 

 

 

 

 

RESET (Note 2) . . . . . . . . . . . ....

- 0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1.Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns.

2.Minimum DC input voltage on pins A9, OE, and RESET is -0.5 V. During voltage transitions, A9, OE, and RESET may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.

3.No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

Stresses above those listed under "Absolute Maximum Rat-ings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

OPERATING RATINGS

Commercial (C) Devices

Ambient Temperature (TA ). . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA ). . . . . . . . . . -40°C to +85°C

VCC Supply Voltages

VCC for regulated voltage range . . . . . +3.0 V to 3.6 V VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

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