MXIC MX27L512PC-12, MX27L512PC-15, MX27L512PC-20, MX27L512PC-25, MX27L512PI-12 Datasheet

MX27L512

FEATURES

•64K x 8 organization

•Wide voltage range, 2.7V to 3.6V

•+12.5V programming voltage

•Fast access time: 120/150/200/250ns

•Totally static operation

•Completely TTL compatible

GENERAL DESCRIPTION

The MX27L512 is a 3V only, 512K-bit, ultraviolet Erasable Programmable Read Only Memory. It is organized as 64K words by 8 bits per word, operates from a single +3volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requiring a single pulse. For programming outside from the system, existing EPROM

512K-BIT [64K x 8] CMOS EPROM

•Operating current: 10mA@ 3.6V, 5MHz

•Standby current: 10uA

•Package type:

-28 pin plastic DIP

-32 pin PLCC

-28 pin 8 x 13.4 mm TSOP(I)

programmers may be used. The MX27L512 supports intelligent fast programming algorithm which can result in programming time of less than fifteen seconds.

This EPROM is packaged in industry standard 28 pin dual-in-line packages , 32 lead PLCC, and 28 lead TSOP(I) packages.

PIN CONFIGURATIONS

BLOCK DIAGRAM

PDIP

A15 1

A12 2

A7 3

A6 4

A5 5

A4 6

A3 7

A2 8

A1 9

A0 10

Q0 11

Q1 12

Q2 13 GND 14

MX27L512

PLCC

A7

A12

A15

NC

VCC

A14

A13

CONTROL

OUTPUT

28

VCC

CE

Q0~Q7

OE/VPP

LOGIC

BUFFERS

27

A14

4

1

32

30

A8

26

A13

A6

5

29

25

A8

A5

A9

24

A9

A4

A11

.

Y-DECODER

.

Y-SELECT

23

A11

A3

NC

.

.

22

OE/VPP

.

.

21

A10

A2

9

MX27L512

25

OE/VPP

A0~A15

.

.

20

CE

A10

ADDRESS

512K BIT

A1

.

.

19

Q7

X-DECODER

CELL

INPUTS

.

A0

CE

.

18

Q6

MAXTRIX

.

.

17

Q5

NC

Q7

.

.

16

Q4

Q0

13

21

Q6

15

Q3

14

17

20

VCC

Q1

Q2

GND

NC

Q3

Q4

Q5

GND

8 x 13.4mm 28TSOP(I)

				22		21			A10
OE/VPP
	A11			23		20
										CE
	A9			24		19			Q7
	A8			25		18			Q6
	A13			26		17			Q5
	A14			27		16			Q4
	VCC			28	MX27L512	15			Q3
	A15			1		14			GND
	A12			2		13			Q2
	A7			3		12			Q1
	A6			4		11			Q0
	A5			5		10			A0
	A4			6		9			A1
	A3			7		8			A2

PIN DESCRIPTION

SYMBOL			PIN NAME
A0~A15			Address Input
Q0~Q7			Data Input/Output
			Chip Enable Input
	CE
			Output Enable Input/Program Supply Voltage
	OE/VPP
NC			No Internal Connection
VCC			Power Supply Pin
GND			Ground Pin

P/N: PM0256

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REV. 2.3, SEP. 19, 2001

MX27L512

FUNCTIONAL DESCRIPTION

THE PROGRAMMING OF THE MX27L512

When the MX27L512 is delivered, or it is erased, the chip has all 512K bits in the "ONE", or HIGH state. "ZEROs" are loaded into the MX27L512 through the procedure of programming.

For programming, the data to be programmed is applied with 8 bits in parallel to the data pins.

Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. When programming an MXIC EPROM, a 0.1uF capacitor is required across Vpp and ground to suppress spurious voltage transients which may damage the device.

FAST PROGRAMMING

The device is set up in the fast programming mode when the programming voltage OE/VPP = 12.75V is applied, with VCC = 6.25 V, (Algorithm is shown in Figure 1). The programming is achieved by applying a single TTL low level 100us pulse to the CE input after addresses and data line are stable. If the data is not verified, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = 5V

± 10%.

PROGRAM INHIBIT MODE

Programming of multiple MX27L512s in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX27L512 may be common. A TTL low-level program pulse applied to an MX27L512 CE input with OE/VPP = 12.5 ± 0.5V will program that MX27L512. A high-level CE input inhibits the other MX27L512s from being programmed.

PROGRAM VERIFY MODE

Verification should be performed on the programmed bits to determine that they were correctly programmed. The verification should be performed with OE/VPP and CE, at VIL. Data should be verified tDV after the falling edge of CE.

AUTO IDENTIFY MODE

The auto identify mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the MX27L512.

To activate this mode, the programming equipment must force 12.0 ± 0.5(VH) on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode.

Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX27L512, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (Q7) defined as the parity bit.

READ MODE

The MX27L512 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC - tOE.

STANDBY MODE

The MX27L512 has a CMOS standby mode which reduces the maximum VCC current to 10 uA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The MX27L512 also has a TTL-standby mode which reduces the maximum VCC current to 0.25 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input.

P/N:PM0256

REV. 2.3, SEP. 19, 2001

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MX27L512

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a twoline control function is provided to allow for:

1.Low memory power dissipation,

2.Assurance that output bus contention will not occur.

It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 uF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.

MODE SELECT TABLE

PINS

MODE			CE	OE/VPP	A0	A9	OUTPUTS
Read			VIL	VIL	X	X	DOUT
Output Disable			VIL	VIH	X	X	High Z
Standby (TTL)			VIH	X	X	X	High Z
Standby (CMOS)			VCC±0.3V	X	X	X	High Z
Program			VIL	VPP	X	X	DIN
Program Verify			VIL	VIL	X	X	DOUT
Program Inhibit			VIH	VPP	X	X	High Z
Manufacturer Code(3)			VIL	VIL	VIL	VH	C2H
Device Code(3)			VIL	VIL	VIH	VH	91H
NOTES: 1.	VH	= 12.0 V ± 0.5 V			3. A1 - A8 = A10 - A15 =		VIL(For auto select)
2.	X =	Either VIH or VIL			4. See DC Programming Characteristics for VPP voltage during
					programming.

P/N:PM0256

REV. 2.3, SEP. 19, 2001

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MX27L512

Figure1. FAST PROGRAMMING FLOW CHART

		START
		ADDRESS = FIRST LOCATION
		VCC = 6.25V
		OE/VPP = 12.75V
		PROGRAM ONE 100us PULSE
	NO	LAST
INCREMENT ADDRESS		ADDRESS ?
		YES
		ADDRESS = FIRST LOCATION
INCREMENT ADDRESS		X = 0
NO
LAST	PASS	FAIL		INCREMENT X
ADDRESS ?		VERIFY BYTE
YES
			NO	X = 25 ?
		PROGRAM ONE 100us PULSE
		VCC = 5.25V		YES
		OE/VPP = VIL
		COMPARE	FAIL	DEVICE FAILED
		ALL BYTES
		TO ORIGINAL
		DATA
		PASS
		DEVICE PASSED

P/N:PM0256

REV. 2.3, SEP. 19, 2001

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MX27L512

SWITCHING TEST CIRCUITS

	DEVICE	1.8K ohm
	UNDER	+5V
	TEST
	CL	DIODES = IN3064
		OR EQUIVALENT
	6.2K ohm

CL = 100 pF including jig capacitance

SWITCHING TEST WAVEFORMS

2.0V	2.0V
AC driving levels	TEST POINTS
0.8V	0.8V
INPUT	OUTPUT

AC TESTING: AC driving levels are 2.4V/0.4V for both commercial grade and industrial grade.

Input pulse rise and fall times are < 10ns.

P/N:PM0256		REV. 2.3, SEP. 19, 2001

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