MX27L256
256K-BIT [32Kx8] LOW VOLTAGE OPERATION
CMOS EPROM
FEATURES
•32K x 8 organization
•Wide Voltage range, 2.7V to 3.6V DC
•+12.5V programming voltage
•Fast access time: 120/150/200/250 ns
•Totally static operation
GENERAL DESCRIPTION
The MX27L256 is a 256K-bit, ultraviolet Erasable Programmable Read Only Memory. It is organized as 32K by 8 bits, operates from a single + 3volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requiring a single pulse. For programming from outside the system, existing EPROM programmers
•Completely TTL compatible
•Operating current: 10mA @ 3.6V, 5MHz
•Standby current: 10uA
•Package type:
-28 pin plastic DIP
-32 pin PLCC
-28 pin 8 x 13.4mm TSOP(I)
may be used. The MX27L256 supports intelligent fast programming algorithm which can result in programming time of less than ten seconds.
This EPROM is packaged in industry standard 28 pin dual-in-line packages, 32 lead PLCC, and 28 lead TSOP(I) packages.
PIN CONFIGURATIONS |
BLOCK DIAGRAM |
PDIP
VPP 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9
A0 10
Q0 11
Q1 12
Q2 13 GND 14
MX27L256
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PLCC |
A12 |
VPP |
NC |
VCC |
A14 |
A13 |
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CONTROL |
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A7 |
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CE |
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Q0~Q7 |
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OE |
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LOGIC |
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BUFFERS |
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A5 |
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A9 |
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A8 |
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Y-DECODER |
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Y-SELECT |
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A9 |
A4 |
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A11 |
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A11 |
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NC |
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A3 |
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OE |
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A0~A14 |
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A2 |
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MX27L256 |
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25 |
OE |
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256K BIT |
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A10 |
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ADDRESS |
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A10 |
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X-DECODER |
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CELL |
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20 |
CE |
A1 |
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INPUTS |
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Q7 |
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MAXTRIX |
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A0 |
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CE |
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Q6 |
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NC |
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Q7 |
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Q5 |
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16 |
Q4 |
Q0 |
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Q6 |
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15 |
Q3 |
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17 |
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20 |
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VCC |
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VPP |
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GND |
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Q1 |
Q2 |
GND |
NC |
Q3 |
Q4 |
Q5 |
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8 x 13.4mm 28 -TSOP(I) |
PIN DESCRIPTION |
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22 |
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21 |
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A10 |
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OE |
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A11 |
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23 |
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20 |
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CE |
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A9 |
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Q7 |
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A8 |
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Q6 |
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A13 |
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Q5 |
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A14 |
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27 |
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16 |
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Q4 |
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VCC |
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28 |
MX27L256 |
15 |
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Q3 |
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VPP |
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1 |
14 |
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GND |
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A12 |
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13 |
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Q2 |
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A7 |
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3 |
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Q1 |
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A6 |
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Q0 |
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A5 |
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10 |
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A0 |
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A4 |
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9 |
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A1 |
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A3 |
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8 |
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A2 |
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SYMBOL |
PIN NAME |
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A0~A14 |
Address Input |
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Q0~Q7 |
Data Input/Output |
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Chip Enable Input |
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CE |
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OE |
Output Enable Input |
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VPP |
Program Supply Voltage |
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NC |
No Internal Connection |
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VCC |
Power Supply Pin |
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GND |
Ground Pin |
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P/N: PM0248 |
REV. 3.3, SEP. 19, 2001 |
1
MX27L256
FUNCTIONAL DESCRIPTION
THE PROGRAMMING OF THE MX27L256
When the MX27L256 is delivered, or it is erased, the chip has all 256K bits in the "ONE" or HIGH state. "ZEROs" are loaded into the MX27L256 through the procedure of programming.
For programming, the data to be programmed is applied with 8 bits in parallel to the data pins.
VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. When programming an MXIC EPROM, a 0.1uF capacitor is required across VPP and ground to suppress spurious voltage transients which may damage the device.
FAST PROGRAMMING
The device is set up in the fast programming mode when the programming voltage VPP = 12.75V is applied, with VCC = 6.25 V and OE = VIH (Algorithm is shown in Figure 1). The programming is achieved by applying a single TTL low level 100us pulse to the CE input after addresses and data line are stable. If the data is not verified, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = VPP = 5V ± 10%.
PROGRAM INHIBIT MODE
Programming of multiple MX27L256s in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX27L256 may be common. A TTL low-level program pulse applied to an MX27L256 CE input with VPP = 12.5 ± 0.5 V and OE HIGH will program that MX27L256. A high-level CE input inhibits the other MX27L256s from being programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed bits to determine that they were correctly programmed. The verification should be performed with CE and OE at VIL, and VPP at its programming voltage.
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the MX27L256.
To activate this mode, the programming equipment must force 12.0 ± 0.5 (VH) on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode.
Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX27L256, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (Q7) defined as the parity bit.
READ MODE
The MX27L256 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC - tOE.
STANDBY MODE
The MX27L256 has a CMOS standby mode which reduces the maximum Vcc current to 10 uA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The MX27L 256 also has a TTL-standby mode which reduces the maximum VCC current to 0.25 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input.
P/N:PM0248 |
REV.3.3, SEP. 19, 2001 |
2
MX27L256
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a twoline control function is provided to allow for:
1.Low memory power dissipation,
2.Assurance that output bus contention will not occur.
It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 uF bulk electrolytic capacitor should be used between Vcc and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
MODE SELECT TABLE
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PINS |
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MODE |
CE |
OE |
A0 |
A9 |
VPP |
OUTPUTS |
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Read |
VIL |
VIL |
X |
X |
VCC |
DOUT |
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Output Disable |
VIL |
VIH |
X |
X |
VCC |
High Z |
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Standby (TTL) |
VIH |
X |
X |
X |
VCC |
High Z |
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Standby (CMOS) |
VCC±0.3V |
X |
X |
X |
VCC |
High Z |
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Program |
VIL |
VIH |
X |
X |
VPP |
DIN |
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Program Verify |
VIH |
VIL |
X |
X |
VPP |
DOUT |
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Program Inhibit |
VIH |
VIH |
X |
X |
VPP |
High Z |
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Manufacturer Code(3) |
VIL |
VIL |
VIL |
VH |
VCC |
C2H |
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Device Code(3) |
VIL |
VIL |
VIH |
VH |
VCC |
10H |
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NOTES: 1. |
VH = 12.0 V ± 0.5 V |
4. See DC Programming characteristics for VPP voltage during |
2. |
X = Either VIH or VIL |
programming. |
3. |
A1 - A8 = A10 - A14 = VIL(For auto select) |
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P/N:PM0248 |
REV.3.3, SEP. 19, 2001 |
3
MX27L256
FIGURE 1. FAST PROGRAMMING FLOW CHART
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START |
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ADDRESS = FIRST LOCATION |
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VCC = 6.25V |
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VPP = 12.75V |
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X = 0 |
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PROGRAM ONE 100us PULSE |
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INTERACTIVE |
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INCREMENT X |
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SECTION |
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YES |
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X = 25? |
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NO |
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FAIL |
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VERIFY BYTE |
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? |
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PASS |
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NO |
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INCREMENT ADDRESS |
LAST ADDRESS |
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FAIL |
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YES |
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VCC = VPP = 5.25V |
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VERIFY SECTION |
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FAIL |
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DEVICE FAILED |
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VERIFY ALL BYTES |
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? |
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PASS |
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DEVICE PASSED |
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P/N:PM0248 |
REV.3.3, SEP. 19, 2001 |
4
MX27L256
SWITCHING TEST CIRCUITS
DEVICE |
1.8K ohm |
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UNDER |
+5V |
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TEST |
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|
CL |
DIODES = IN3064 |
|
OR EQUIVALENT |
||
6.2K ohm |
CL = 100 pF including jig capacitance
SWITCHING TEST WAVEFORMS
2.0V |
2.0V |
AC driving levels |
TEST POINTS |
0.8V |
0.8V |
INPUT |
OUTPUT |
AC TESTING: AC driving levels are 2.4V/0.4V for both commercial grade and industrial grade.
Input pulse rise and fall times are < 20ns.
P/N:PM0248 |
REV.3.3, SEP. 19, 2001 |
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