ADVANCE INFORMATION
MX26C2000B
FEATURES
•256Kx 8 organization
•Single +5V power supply
•+12V programming voltage
•Fast access time:90/100/120/150 ns
•Totally static operation
•Completely TTL compatible
•Operating current:30mA
•Standby current: 100uA
GENERAL DESCRIPTION
2M-BIT[256Kx8]CMOS MULTIPLE-TIME-PROGRAMMABLE-EPROM
•Chip erase time: 1 (typ.)
•Chip program time: 12.5 (typ.)
•50 minimum erase/program cycles
•Typical fast programming cycle duration 10us/byte
•Package type:
-32 pin plastic DIP
-32 pin PLCC
-32 pin TSOP
-32 pin SOP
The MX26C2000B is a 5V only, 2M-bit, MTP EPROMTM (Multiple Time Programmable Read Only Memory). It is organized as 256K words by 8 bits per word, operates from a single + 5 volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requiring a single pulse. It is design to be programmed and erased by an
EPROM programmer or on-board. The MX26C2000B supports a intelligent fast programming algorithm which can result in programming time of less than one minute.
This MTP EPROMTM is packaged in industry standard 32 pin dual-in-line packages, 32 lead PLCC, 32 lead SOP and 32 lead TSOP packages.
PIN CONFIGURATIONS 32 PDIP/SOP
VPP |
1 |
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A16 |
2 |
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A15 |
3 |
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A12 |
4 |
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A7 |
5 |
MX26C2000B |
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A6 |
6 |
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A5 |
7 |
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A4 |
8 |
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A3 |
9 |
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A2 |
10 |
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A1 |
11 |
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A0 |
12 |
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Q0 |
13 |
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Q1 |
14 |
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Q2 |
15 |
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GND |
16 |
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32 VCC
31 WE
30 A17
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 Q7
20 Q6
19 Q5
18 Q4
17 Q3
32 PLCC
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A12 |
A15 |
A16 |
VPP |
VCC |
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WE |
A17 |
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4 |
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1 |
32 |
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30 |
A14 |
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A7 |
5 |
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29 |
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A6 |
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A13 |
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A5 |
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A8 |
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A4 |
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A9 |
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A3 |
9 |
MX26C2000B |
25 |
A11 |
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A2 |
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OE |
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A1 |
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A10 |
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A0 |
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CE |
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Q0 |
13 |
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17 |
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21 |
Q7 |
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14 |
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20 |
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Q1 |
Q2 |
GND |
Q3 |
Q4 |
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Q5 |
Q6 |
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32 TSOP
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32 |
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A11 |
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1 |
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OE |
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A9 |
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2 |
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31 |
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A10 |
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30 |
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A8 |
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3 |
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CE |
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A13 |
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4 |
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29 |
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Q7 |
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A14 |
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5 |
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28 |
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Q6 |
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A17 |
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6 |
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27 |
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Q5 |
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7 |
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26 |
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Q4 |
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WE |
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VCC |
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8 |
MX26C2000B |
25 |
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Q3 |
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VPP |
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9 |
24 |
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GND |
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A16 |
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10 |
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23 |
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Q2 |
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A15 |
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11 |
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22 |
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Q1 |
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A12 |
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12 |
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21 |
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Q0 |
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A7 |
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13 |
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20 |
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A0 |
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A6 |
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14 |
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19 |
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A1 |
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A5 |
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15 |
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18 |
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A2 |
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A4 |
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16 |
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17 |
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A3 |
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PIN DESCRIPTION
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SYMBOL |
PIN NAME |
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A0~A17 |
Address Input |
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Q0~Q7 |
Data Input/Output |
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Chip Enable Input |
CE |
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Output Enable Input |
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OE |
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Write Enable Input |
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WE |
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VPP |
Program Supply Voltage |
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NC |
No Internal Connection |
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VCC |
Power Supply Pin (+5V) |
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GND |
Ground Pin |
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P/N: PM0765 |
1 |
REV. 0.7, OCT. 04, 2001 |
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MX26C2000B
BLOCK DIAGRAM
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WRITE |
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CE |
CONTROL |
PROGRAM/ERASE |
STATE |
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INPUT |
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OE |
HIGH VOLTAGE |
MACHINE |
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WE |
LOGIC |
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(WSM) |
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X-DECODER |
MX26C2000B |
STATE |
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ADDRESS |
FLASH |
REGISTER |
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LATCH |
ARRAY |
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A0-A17 |
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ARRAY |
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AND |
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-Y |
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SOURCE |
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DECODER |
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BUFFER |
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HV |
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Y-PASS GATE |
COMMAND |
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DATA |
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DECODER |
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SENSE |
PGM |
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AMPLIFIER |
DATA |
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HV |
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COMMAND |
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DATA LATCH |
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PROGRAM |
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DATA LATCH |
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Q0-Q7 |
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I/O BUFFER |
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P/N: PM0765 |
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2 |
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REV. 0.7, OCT. 04, 2001 |
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MX26C2000B
FUNCTIONAL DESCRIPTION
When the MX26C2000B is delivered, or it is erased, the chip has all 2000K bits in the "ONE", or HIGH state. "ZEROs" are loaded into the MX26C2000B through the procedure of programming.
ERASE ALGORITHM
The MX26C2000B do not required preprogramming before an erase operation. The erase algorithm is a close loop flow to simultaneously erase all bits in the entire array. Erase operation starts with the initial erase operation. Erase verification begins at address 0000H by reading data FFH from each byte. If any byte fails to erase. the entire chip is reerased. to a maximum for 30 pulse counts of 100ms duration for each pulse. The maximum cumulative erase time is 3s. However. the device is usually erased in no more than 3 pulses. Erase verification time can be reduced by storing the address of the last byte that failed. Following the next erase operation verification may start at the stored address location. JEDEC standard erase algorithm can also be used. But erase time will increase by performing the unnecessary preprogramming.
PROGRAM ALGORITHM
The device is programmed byte by byte. A maximum of 25 pulses. each of 10us duration is allowed for each byte being programmed. The byte may be programmed sequentially or by random. After each program pulse, a program verify is done to determine if the byte has been successfully programmed.
Programming then proceeds to the next desired byte location. JEDEC standard program algorithms can be used.
RESET
The Reset command initializes the MTP EPROMTM device to the Read mode. In addition, it also provides the user with a safe method to abort any device operation (including program or erase). The Reset command must be written two consecutive times after the set-up Program command (40H). This will safely abort any previous operation and initialize the device to the Read mode.
Theset-upProgramcommand(40H)istheonlycommand that requires a two sequence reset cycle. The first Reset command is interpreted as program data. How ever, FFH dataisconsiderednulldataduringprogrammingoperations (memory cells are only programmed from logica "1" to "0". The second Reset command safely aborts the programming operation and resets the device to the Read mode.
This detailed information is for your reference. It may prove esier to always issue the Reset command two consecutive times. This eliminates the need to determine if you are in the set-up Program state or not.
SET-UP PROGRAM/PROGRAM
A three-step sequence of commands is required to perform a complete program operation: Set Up Program- Program-Program Verify. The device is bulk erased and byte by byte programming. The command 40H is written to the command register to initiate Set Up Program operation. Address and data to be programmed into the byte are provided on the second WE pulse. Addresses are latched on the falling edge of the WE pulse, data are latched on the rising edge of the WE pulse. Program operation begins on the rising edge of the second WE pulse, and terminate of the next rising edge of the WE pulse. Refer to AC Characteristics and Waveforms for specific timing parameters.
COMMAND REGISTER
When high voltage is applied to VPP the command register is enabled. Read, write, standby, output disable modes are available. The read, erase, erase verify, program, program verify and Device ID are accessed via the command register. Standard microprocessor write timings are used to input a command to the register. This register serves as the input to an internal state machine which controls the operation mode of the device. An internal latch is used for write cycles, addresses and data for programming and erase operations.
NO INTEGRATED STOP TIMER FOR ERASE
Leading industry flash technology requires a stop timer built into the flash chip to prevent the memory cells from going into depletion due to over erase. The 2 Mbit MTP
P/N: PM0765 |
3 |
REV. 0.7, OCT. 04, 2001 |
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MX26C2000B
EPROMTM is built on an innovative cell concept in which over erasing the memory cell is impossible.
DATA WRITE PROTECTION
The design of the device protects against accidental erasure or programming. The internal state machine is automatically reset to the read mode on power-up. Using control register architecture, alteration of memory can only occur after completion of proper command sequences. The command register is only active when V PP is at high voltage. when V PP = V PPL , the device defaults to the Read Mode. Robust design features prevent inadvertent write cycles resulting from VCC power-up and power-downtransitionsorsystemnoise.Toavoidinitiation of write cycle during VCC power-up, a write cycle is locked out for VCC less than 4V. The twocommand program and erase write sequence to the command register provide additional software protection against spurious data changes.
PROGRAM VERIFY MODE
Verification should be performed on the programmed bits to determine that they were correctly programmed. Verification should be performed with OE and CE, at VIL, WE at VIH, and VPP at its programming voltage.
ERASE VERIFY MODE
Verification should be performed on the erased chip to determine that the whole chip(all bits) was correctly erased. Verification should be performed with OE and CE at VIL, WE at VIH, and VCC = 5V, VPP = 12.5V
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary code from MTP EPROM that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ±5°C ambient temperature range that is required when programming the MX26C2000B.
To activate this mode, the programming equipment must
force 12.0 ± 0.5 V on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode.
Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX26C2000B, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit.
READ MODE
The MX26C2000B has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC - tOE.
STANDBY MODE
The MX26C2000B has a CMOS standby mode which reduces the maximum VCC current to 100 uA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The MX26C2000B also has a TTL-standby mode which reduces the maximum VCC current to 1.5 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive
P/N: PM0765 |
4 |
REV. 0.7, OCT. 04, 2001 |
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MX26C2000B
effects of the printed circuit board traces on EPROM arrays, a 4.7 uF bulk electrolytic capacitor should be used between VCC and GND for each of the eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
OUTPUT DISABLE
Output is disabled when OE is at logre high. When in output disabled all circuitry is enabled. Except the output pins are in a high impedance state(TRI-ATATE).
Table 1: BUS OPERATIONS
Mode |
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VPP(1) |
A0 |
A9 |
CE |
OE |
WE |
Q0~Q7 |
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Read |
VPPL |
A0 |
A9 |
VIL |
VIL |
VIH |
Data Out |
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READ-ONLY |
Output Disable |
VPPL |
X |
X |
VIL |
VIH |
VIH |
Tri-State |
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MODE |
Standby |
VPPL |
X |
X |
VIH |
X |
X |
Tri-State |
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Manufacturer Identification |
VPPL |
VIL |
VID(2) |
VIL |
VIL |
VIH |
Data=C2H |
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Device Identification |
VPPL |
VIH |
VID(2) |
VIL |
VIL |
VIH |
Data=C3H |
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Read |
VPPH |
A0 |
A9 |
VIL |
VIL |
VIH |
Data Out(3) |
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COMMAND |
Output Disable |
VPPH |
X |
X |
VIL |
VIH |
VIH |
Tri-State |
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MODE |
Standby(4) |
VPPH |
X |
X(5) |
VIH |
X |
X |
Tri-State |
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Program |
VPPH |
A0 |
A9 |
VIL |
VIH |
VIL |
Data Inb |
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Note:
1.Refer to DC Characteristics. When VPP=VPPL memory contents can be read but not written or erased.
2.VID is the intelligent identifier high voltage. Refer to DC Characteristics.
3.Read operations with VPP=VPPH may access array data or the intelligent identifier codes.
4.With VPP at high voltage the standby current equals ICC+IPP(standby).
5.Refer to Table 2 for vaild data-in during a write operation.
6.X can be VIL or VIH.
P/N: PM0765 |
5 |
REV. 0.7, OCT. 04, 2001 |
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MX26C2000B
COMMAND MODE
The 2 Mbit MTP EPROMTM is in Command mode when high voltage VPPH is applied to the VPP pin. In this state the available functions are Read, Program, Program Verify, Eraseand Erase Verify. Reset are selected by writing commands to the input register. Data from the register are input to the state machine. The output from the state machine determines the function of the device. The command register serves as a latch to store data for executing commands. It does not occupy addressable memory location. Standard microprocessor write timing is used. Table 2 defines the register commands. The command register is written by bringing WE to a logic-low Level (V IL), while CE is low. Addresses are latched on the falling edge of WE, while data is latched on the rising edge of the WE pulse.
Standby and Output disable functions are the same as in Read Mode, controlled by CE and OE. If the device is deselectedduringerasure,programming,orerase/program verification, the device draws active current until the operations terminate.
READ COMMAND
To read memory content, write 00H into the command register while high voltage is applied to V PP pin (VPP = VPPH ). Microprocessor read cycle retrieves the data . The device remains enable for read until the data in the command register are altered. The device is default in read mode when power up. This is to ensure no accidental alteration of the memory occurs during power transition.RefertoACReadCharacteristicsandWaveforms for specific timing parameters.
SET UP ERASE/ERASE
Preprogram operation is not required prior to the erase operation.Asequenceofcommandsisrequiredtoperform a complete erase operation: set up erase, erase, and erase verify. High voltage is applied to the V PP pin
(VPP=VPPH). The command 20H is written to the command register to initiate the set-up erase mode.
ERASE OPERATION
The same command, 20H, is again written to the command register. This second command starts bulk
erase operation. The two-step command prevents accidental alteration to memory array. Erase operation starts with the rising edge of the WE pulse and terminates with the rising edge of the next WE pulse, which in this case is the erase verify command.
ERASE VERIFY
Each erase operation is followed by an erase verify. The command A0H is written into the command register. The address of the bytes to be verified is supplied with the command. The address is latched on the falling edge of the WE pulse. A reading FFH is returned to confirm all bits in the byte are erased. This sequence of Set Up EraseErase continues for each address until FFH is returned. This indicates the entire memory array is erased and completes the operation. Erase verify operation starts at address 0000H and ends at the last address. Maximum erase pulse duration for the 2Mbit MTP EPROMTM is 100ms with a maximum 30 pulses. Refer to AC Characteristics and Waveforms for specific timing parameters.
P/N: PM0765 |
6 |
REV. 0.7, OCT. 04, 2001 |
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MX26C2000B
PROGRAMMING ALGORITHM FLOW CHART
Start
Programming
Apply VPPH
PLSCNT=0
Write Set-up Program CMD
Write Program Cmd(A/D)
Time Out 10us
Write Program Verify Cmd
Time out 6us
Read Data From Device
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NO |
Verify Data ? |
NO |
Inc PLSNT=25 ? |
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YES |
YES |
NO
Increment Address |
Last Address ? |
YES
Write Read CMD
Apply VPPL |
Apply VPPL |
Programming |
Programming |
Completed |
Error |
P/N: PM0765 |
7 |
REV. 0.7, OCT. 04, 2001 |
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