19-0401; Rev 0; 6/95
Multi-Range (±4V, ±2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface
_______________General Description
The MAX199 multi-range, 12-bit data-acquisition system (DAS) requires only a single +5V supply for operation, and converts analog signals up to ±4V at its inputs. This system provides eight analog input channels that are independently software programmable for a variety of ranges: ±VREF, ±VREF/2, 0V to VREF, or 0V to VREF/2. This increases effective dynamic range to 14 bits, and provides the user flexibility to interface 4mA-to-20mA, ±12V, and ±15V powered sensors to a single +5V system. In addition, the converter is fault-protected to ±16.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, 100ksps throughput rate, internal/external clock, internal/external acquisition control, 8+4 parallel interface, and operation with an internal 4.096V or external reference.
A hardware SHDN pin and two programmable powerdown modes (STBYPD, FULLPD) provide low-current shutdown between conversions. In STBYPD mode, the reference buffer remains active, eliminating start-up delays.
The MAX199 employs a standard microprocessor (µP) interface. Its three-state data I/O interface is configured to operate with 8-bit data buses, and data-access and bus-release timing specifications are compatible with most popular µPs. All logic inputs and outputs are TTL/CMOS compatible.
The MAX199 is available in 28-pin DIP, wide SO, SSOP, and ceramic SB packages.
For a different combination of input ranges (±10V, ±5V, 0V to 10V, 0V to 5V), see the MAX197 data sheet. For 12bit bus interfaces, see the MAX196/MAX198 data sheet.
________________________Applications
Industrial-Control Systems
Robotics
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
Telecommunications
____________________________Features
♦12-Bit Resolution, 1/2LSB Linearity
♦Single +5V Operation
♦Software-Selectable Input Ranges:
±V REF, ±V REF/2, 0V to VREF, 0V to VREF/2
♦Internal 4.096V or External Reference
♦Fault-Protected Input Multiplexer (±16.5V)
♦8 Analog Input Channels
♦6µs Conversion Time, 100ksps Sampling Rate
♦Internal or External Acquisition Control
♦Two Power-Down Modes
♦Internal or External Clock
______________Ordering Information
PART |
TEMP. RANGE |
PIN-PACKAGE |
MAX199ACNI |
0°C to +70°C |
28 Narrow Plastic DIP |
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MAX199BCNI |
0°C to +70°C |
28 Narrow Plastic DIP |
MAX199ACWI |
0°C to +70°C |
28 Wide SO |
MAX199BCWI |
0°C to +70°C |
28 Wide SO |
MAX199ACAI |
0°C to +70°C |
28 SSOP |
MAX199BCAI |
0°C to +70°C |
28 SSOP |
MAX199BC/D |
0°C to +70°C |
Dice* |
Ordering Information continued at end of data sheet.
*Dice are specified at TA = +25°C, DC parameters only.
__________________Pin Configuration
TOP VIEW
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CLK |
1 |
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28 |
DGND |
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CS |
2 |
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27 |
VDD |
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REF |
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WR |
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3 |
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26 |
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REFADJ |
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4 |
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25 |
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RD |
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HBEN |
5 |
MAX199 |
24 |
INT |
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SHDN |
6 |
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23 |
CH7 |
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D7 |
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7 |
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22 |
CH6 |
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D6 |
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8 |
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21 |
CH5 |
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D5 |
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9 |
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20 |
CH4 |
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D4 |
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CH3 |
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10 |
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19 |
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CH2 |
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D3/D11 |
11 |
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18 |
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CH1 |
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D2/D10 |
12 |
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17 |
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CH0 |
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D1/D9 |
13 |
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16 |
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AGND |
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D0/D8 |
14 |
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15 |
Functional Diagram appears at end of data sheet. |
DIP/SO/SSOP/Ceramic SB |
________________________________________________________________ Maxim Integrated Products 1
MAX199
Call toll free 1-800-722-8266 for free samples or literature.
MAX199
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
ABSOLUTE MAXIMUM RATINGS
VDD to AGND............................................................ |
-0.3V to +7V |
AGND to DGND..................................................... |
-0.3V to +0.3V |
REF to AGND.............................................. |
-0.3V to (VDD + 0.3V) |
REFADJ to AGND....................................... |
-0.3V to (VDD + 0.3V) |
Digital Inputs to DGND............................... |
-0.3V to (VDD + 0.3V) |
Digital Outputs to DGND............................ |
-0.3V to (VDD + 0.3V) |
CH0–CH7 to AGND .......................................................... |
±16.5V |
Continuous Power Dissipation (TA = +70°C)
Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW
Wide SO (derate 12.50mW/°C above +70°C).............. |
1000mW |
SSOP (derate 9.52mW/°C above +70°C) ...................... |
762mW |
Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW
Operating Temperature Ranges |
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MAX199_C_ _ ....................................................... |
0°C to +70°C |
MAX199_E_ _..................................................... |
-40°C to +85°C |
MAX199_M_ _.................................................. |
-55°C to +125°C |
Storage Temperature Range ............................. |
-65°C to +150°C |
Lead Temperature (soldering, 10sec) ............................. |
+300°C |
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER |
SYMBOL |
CONDITIONS |
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MIN |
TYP |
MAX |
UNITS |
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ACCURACY (Note 1) |
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Resolution |
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12 |
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Bits |
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Integral Nonlinearity |
INL |
MAX199A |
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±1/2 |
LSB |
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MAX199B |
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±1 |
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Differential Nonlinearity |
DNL |
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±1 |
LSB |
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Unipolar |
MAX199A |
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±3 |
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Offset Error |
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MAX199B |
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±5 |
LSB |
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Bipolar |
MAX199A |
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±5 |
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MAX199B |
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±10 |
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Channel-to-Channel Offset |
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Unipolar |
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±0.1 |
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LSB |
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Error Matching |
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Bipolar |
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±0.5 |
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Unipolar |
MAX199A |
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±7 |
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Gain Error |
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MAX199B |
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±10 |
LSB |
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(Note 2) |
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Bipolar |
MAX199A |
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±7 |
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MAX199B |
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±10 |
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Gain Temperature Coefficient |
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Unipolar |
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3 |
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ppm/°C |
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(Note 2) |
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Bipolar |
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5 |
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DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±4.096Vp-p, fSAMPLE = 100ksps) |
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Signal-to-Noise + Distortion Ratio |
SINAD |
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MAX199A |
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70 |
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dB |
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MAX199B |
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69 |
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Total Harmonic Distortion |
THD |
Up to the 5th harmonic |
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-85 |
-78 |
dB |
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Spurious-Free Dynamic Range |
SFDR |
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80 |
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dB |
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Channel-to-Channel Crosstalk |
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50kHz, VIN = ±4V (Note 3) |
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-86 |
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dB |
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Aperture Delay |
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External CLK mode/external acquisition control |
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15 |
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ns |
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External CLK mode/external acquisition |
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<50 |
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ps |
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control |
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Aperture Jitter |
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Internal CLK mode/internal acquisition |
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10 |
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ns |
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control (Note 4) |
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2 _______________________________________________________________________________________
Multi-Range (±4V, ±2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER |
SYMBOL |
CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
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ANALOG INPUT |
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Track/Hold Acquisition Time |
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fCLK = 2.0MHz |
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3 |
µs |
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±VREF range |
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5 |
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Small-Signal Bandwidth |
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-3dB rolloff |
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±VREF/2 range |
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2.5 |
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MHz |
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0V to VREF range |
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2.5 |
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0V to VREF/2 range |
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1.25 |
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Unipolar (see Table 2) |
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0 |
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VREF |
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Input Voltage Range |
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0 |
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VREF/2 |
V |
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Bipolar (see Table 2) |
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-VREF |
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VREF |
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-VREF/2 |
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VREF/2 |
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Unipolar range |
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0.1 |
10 |
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Input Current |
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Bipolar |
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±VREF range |
-1200 |
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10 |
µA |
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±VREF/2 range |
-600 |
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10 |
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Input Dynamic Resistance |
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Unipolar |
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40 |
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MΩ |
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Bipolar |
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10 |
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kΩ |
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Input Capacitance |
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(Note 5) |
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40 |
pF |
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INTERNAL REFERENCE |
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REF Output Voltage |
VREF |
TA = +25°C |
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4.076 |
4.096 |
4.116 |
V |
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REF Output Tempco |
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MAX199_C |
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±15 |
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(Contact Maxim Applications |
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TC VREF |
MAX199_E |
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±30 |
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ppm/°C |
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for guaranteed temperature |
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drift specifications) |
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MAX199_M |
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±40 |
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Output Short-Circuit Current |
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30 |
mA |
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Load Regulation |
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0mA to 0.5mA output current (Note 6) |
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7.5 |
mV |
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0mA to 0.1mA output current (Note 6) |
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0.8 |
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Capacitive Bypass at REF |
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4.7 |
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µF |
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REFADJ Output Voltage |
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2.465 |
2.500 |
2.535 |
V |
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REFADJ Adjustment Range |
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With recommended circuit (Figure 1) |
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±1.5 |
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% |
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Buffer Voltage Gain |
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1.6384 |
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V/V |
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REFERENCE INPUT (Buffer disabled, reference input applied to REF pin) |
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Input Voltage Range |
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2.4 |
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4.18 |
V |
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Normal, or STANDBY |
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400 |
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power-down mode |
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Input Current |
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VREF = 4.18V |
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µA |
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FULL power-down |
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1 |
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mode |
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Input Resistance |
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Normal, or STANDBY power-down mode |
10 |
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kΩ |
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FULL power-down mode |
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5 |
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MΩ |
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REFADJ Threshold for |
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VDD - 50mV |
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V |
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Buffer Disable |
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MAX199
_______________________________________________________________________________________ 3
MAX199
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER |
SYMBOL |
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CONDITIONS |
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MIN |
TYP |
MAX |
UNITS |
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POWER REQUIREMENTS |
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Supply Voltage |
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VDD |
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4.75 |
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5.25 |
V |
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Normal mode, bipolar ranges |
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18 |
mA |
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Supply Current |
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IDD |
Normal mode, unipolar ranges |
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6 |
10 |
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Standby power-down (STBYPD) |
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700 |
850 |
µA |
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Full power-down mode (FULLPD) (Note 7) |
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60 |
120 |
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Power-Supply Rejection Ratio |
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External reference = 4.096V |
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±1/ |
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PSRR |
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2 |
LSB |
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(Note 8) |
Internal reference |
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±1/2 |
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TIMING |
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Internal Clock Frequency |
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fCLK |
CCLK = 100pF |
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1.25 |
1.56 |
2.00 |
MHz |
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External Clock Frequency Range |
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fCLK |
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0.1 |
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2.0 |
MHz |
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tACQI |
Internal acquisition |
External CLK |
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3.0 |
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Acquisition Time |
Internal CLK |
3.0 |
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5.0 |
µs |
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tACQE |
External acquisition (Note 9) |
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3.0 |
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After FULLPD or STBYPD |
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5 |
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Conversion Time |
tCONV |
External CLK |
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6.0 |
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Internal CLK, CCLK = 100pF |
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6.0 |
7.7 |
10.0 |
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Throughput Rate |
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External CLK |
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100 |
ksps |
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Internal CLK, CCLK = 100pF |
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62 |
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Bandgap Reference |
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Power-up (Note 10) |
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Start-Up Time |
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Reference Buffer Settling |
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To 0.1mV, REF |
CREF = 4.7µF |
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8 |
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bypass capacitor |
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CREF = 33µF |
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60 |
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fully discharged |
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DIGITAL INPUTS (D7–D0, CLK, |
RD, |
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WR, |
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CS, |
HBEN, |
SHDN) |
(Note 11) |
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Input High Voltage |
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VINH |
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2.4 |
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V |
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Input Low Voltage |
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VINL |
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0.8 |
V |
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Input Leakage Current |
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IIN |
VIN = 0V or VDD |
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±10 |
µA |
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Input Capacitance |
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CIN |
(Note 5) |
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15 |
pF |
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DIGITAL OUTPUTS (D7–D4, D3/D11, D2/D10, D1/D9, D0/D8, |
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INT) |
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Output Low Voltage |
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VOL |
VDD = 4.75V, ISINK = 1.6mA |
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0.4 |
V |
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Output High Voltage |
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VOH |
VDD = 4.75V, ISOURCE = 1mA |
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VDD - 1 |
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V |
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Three-State Output Capacitance |
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COUT |
(Note 5) |
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15 |
pF |
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4 _______________________________________________________________________________________
Multi-Range (±4V, ±2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface
TIMING CHARACTERISTICS
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.)
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PARAMETER |
SYMBOL |
CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
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Pulse Width |
tCS |
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80 |
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CS |
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Pulse Width |
tWR |
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80 |
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WR |
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to |
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Setup Time |
tCSWS |
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0 |
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ns |
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CS |
WR |
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CS |
to |
WR |
Hold Time |
tCSWH |
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0 |
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to |
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Setup Time |
tCSRS |
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0 |
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CS |
RD |
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to |
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Hold Time |
tCSRH |
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0 |
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ns |
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CS |
RD |
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CLK to |
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Setup Time |
tCWS |
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100 |
ns |
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WR |
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CLK to |
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Hold Time |
tCWH |
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50 |
ns |
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WR |
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Data Valid to |
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Setup |
tDS |
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60 |
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WR |
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Data Valid to |
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Hold |
tDH |
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0 |
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WR |
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Low to Output Data Valid |
tDO |
Figure 2, CL = 100pF (Note 12) |
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120 |
ns |
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RD |
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HBEN High or HBEN Low to |
tDO1 |
Figure 2, CL = 100pF (Note 12) |
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120 |
ns |
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Output Valid |
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RD |
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High to Output Disable |
tTR |
(Note 13) |
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70 |
ns |
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Low to |
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High Delay |
tINT1 |
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120 |
ns |
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RD |
INT |
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Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply Rejection test. Tested for the ±4.096V input range.
External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB. Ground “on” channel; sine wave applied to all “off” channels.
Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz. Guaranteed by design. Not tested.
Use static loads only.
Tested using internal reference.
PSRR measured at full-scale. VDD = 4.75V to 5.25V.
External acquisition timing: starts at rising edge of WR with control bit ACQMOD = low; ends at rising edge of WR with ACQMOD = high.
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with tR = tF = 5ns from a voltage level of 0.8V to 2.4V.
Note 12: tDO and tDO1 are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 13: tTR is defined as the time required for the data lines to change by 0.5V.
MAX199
_______________________________________________________________________________________ 5