Maxim MAX192BMJP, MAX192BCWP, MAX192BCPP, MAX192BCAP, MAX192AMJP Datasheet

...
0 (0)

19-0247; Rev. 1; 4/97

________________General Description

The MAX192 is a low-cost, 10-bit data-acquisition system that combines an 8-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and ultra-low power consumption. The device operates with a single +5V supply. The analog inputs are software configurable for single-ended and differential (unipolar/bipolar) operation.

The 4-wire serial interface connects directly to SPI™, QSPI™, and Microwire™ devices, without using external logic. A serial strobe output allows direct connection to TMS320 family digital signal processors. The MAX192 uses either the internal clock or an external serialinterface clock to perform successive approximation A/D conversions. The serial interface can operate beyond 4MHz when the internal clock is used. The MAX192 has an internal 4.096V reference with a drift of ±30ppm typical. A reference-buffer amplifier simplifies gain trim and two sub-LSBs reduce quantization errors.

The MAX192 provides a hardwired SHDN pin and two software-selectable power-down modes. Accessing the serial interface automatically powers up the device, and the quick turn-on time allows the MAX192 to be shut down between conversions. By powering down between conversions, supply current can be cut to under 10µA at reduced sampling rates.

The MAX192 is available in 20-pin DIP and SO packages, and in a shrink-small-outline package (SSOP) that occupies 30% less area than an 8-pin DIP. The data format provides hardware and software compatibility with the MAX186/MAX188. For anti-aliasing filters, consult the data sheets for the MAX291–MAX297.

________________________Applications

Automotive Pen-Entry Systems Consumer Electronics

Portable Data Logging Robotics

Battery-Powered Instruments, Battery Management

Medical Instruments

____________________________Features

See last page for Typical Operating Circuit.

SPI and QSPI are trademarks of Motorola Corp. Microwire is a trademark of National Semiconductor Corp.

Low-Power, 8-Channel,

Serial 10-Bit ADC

8-Channel Single-Ended or 4-Channel Differential Inputs

Single +5V Operation

Low Power: 1.5mA (operating)

2µA (power-down)

Internal Track/Hold, 133kHz Sampling Rate

Internal 4.096V Reference

4-Wire Serial Interface is Compatible with SPI, QSPI, Microwire, and TMS320

20-Pin DIP, SO, SSOP Packages

Pin-Compatible 12-Bit Upgrade (MAX186/MAX188)

_______________Ordering Information

PART

TEMP. RANGE

PIN-PACKAGE INL (LSB)

 

 

 

 

MAX192ACPP

0°C to +70°C

20 Plastic DIP

±1/2

 

 

 

 

MAX192BCPP

0°C to +70°C

20 Plastic DIP

±1

 

 

 

 

MAX192ACWP

0°C to +70°C

20 Wide SO

±1/2

MAX192BCWP

0°C to +70°C

20 Wide SO

±1

MAX192ACAP

0°C to +70°C

20 SSOP

±1/2

 

 

 

 

MAX192BCAP

0°C to +70°C

20 SSOP

±1

 

 

 

 

MAX192AEPP

-40°C to +85°C

20 Plastic DIP

±1/2

MAX192BEPP

-40°C to +85°C

20 Plastic DIP

±1

MAX192AEWP

-40°C to +85°C

20 Wide SO

±1/2

 

 

 

 

MAX192BEWP

-40°C to +85°C

20 Wide SO

±1

 

 

 

 

MAX192AEAP

-40°C to +85°C

20 SSOP

±1/2

MAX192BEAP

-40°C to +85°C

20 SSOP

±1

MAX192AMJP

-55°C to +125°C

20 CERDIP

±1/2

 

 

 

 

MAX192BMJP

-55°C to +125°C

20 CERDIP

±1

 

 

 

 

___________________Pin Configuration

TOP VIEW

 

CH0

 

 

 

 

 

 

 

VDD

 

 

1

 

 

 

 

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CH1

 

2

 

 

 

 

19

SCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CH2

 

3

 

 

 

 

18

 

CS

 

 

CH3

 

 

 

MAX192

 

 

 

 

 

 

4

17

DIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CH4

 

5

 

 

 

 

16

SSTRB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CH5

 

6

 

 

 

 

15

DOUT

 

CH6

 

 

 

 

 

 

 

DGND

 

 

7

 

 

 

 

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CH7

 

8

 

 

 

 

13

AGND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AGND

 

9

 

 

 

 

12

REFADJ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SHDN

 

10

 

 

 

 

11

VREF

 

 

 

 

 

 

 

 

 

 

 

 

 

DIP/SO/SSOP

________________________________________________________________ Maxim Integrated Products 1

MAX192

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468.

MAX192

Low-Power, 8-Channel,

Serial 10-Bit ADC

ABSOLUTE MAXIMUM RATINGS

VDD to AGND...........................................................

-0.3V to +6V

AGND to DGND....................................................

-0.3V to +0.3V

CH0–CH7 to AGND, DGND ......................

-0.3V to (VDD + 0.3V)

CH0–CH7 Total Input Current..........................................

±20mA

VREF to AGND ..........................................

-0.3V to (VDD + 0.3V)

REFADJ to AGND......................................

-0.3V to (VDD + 0.3V)

Digital Inputs to DGND..............................

-0.3V to (VDD + 0.3V)

Digital Outputs to DGND...........................

-0.3V to (VDD + 0.3V)

Digital Output Sink Current .................................................

25mA

Continuous Power Dissipation (TA = +70°C)

 

 

Plastic DIP (derate 11.11mW/°C above +70°C)

......... 889mW

SO (derate 10.00mW/°C above +70°C)......................

 

800mW

SSOP (derate 8.00mW/°C above +70°C) ...................

 

640mW

CERDIP (derate 11.11mW/°C above +70°C)..............

 

889mW

Operating Temperature Ranges

 

 

MAX192_C_P .....................................................

 

0°C to +70°C

MAX192_E_P ..................................................

-40°C to +85°C

MAX192_MJP ...............................................

-55°C to +125°C

Storage Temperature Range ............................

-60°C to +150°C

Lead Temperature (soldering, 10sec) ............................

 

+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(VDD = 5V ±5%, fCLK = 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

 

 

 

DC ACCURACY (Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Resolution

 

 

10

 

 

Bits

 

 

 

 

 

 

 

 

 

Relative Accuracy (Note 2)

 

MAX192A

 

 

±1/2

LSB

 

 

 

 

 

 

 

 

MAX192B

 

 

±1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Differential Nonlinearity

DNL

No missing codes over temperature

 

 

±1

LSB

 

 

 

 

 

 

 

 

 

Offset Error

 

 

 

 

±2

LSB

 

 

 

 

 

 

 

 

 

Gain Error

 

External reference, 4.096V

 

 

±2

LSB

 

 

 

 

 

 

 

 

 

Gain Temperature Coefficient

 

External reference, 4.096V

 

±0.8

 

ppm/°C

 

 

 

 

 

 

 

 

 

Channel-to-Channel

 

 

 

±0.1

 

LSB

 

Offset Matching

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096Vp-p, 133ksps, 2.0MHz external

clock)

 

 

 

 

 

 

 

 

 

 

 

 

Signal-to-Noise + Distortion Ratio

SINAD

 

 

66

 

dB

 

 

 

 

 

 

 

 

 

Total Harmonic Distortion

THD

 

 

-70

 

dB

 

(up to the 5th harmonic)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Spurious-Free Dynamic Range

SFDR

 

 

70

 

dB

 

 

 

 

 

 

 

 

 

Channel-to-Channel Crosstalk

 

65kHz, VIN = 4.096Vp-p (Note 3)

 

-75

 

dB

 

 

 

 

 

 

 

 

 

Small-Signal Bandwidth

 

-3dB rolloff

 

4.5

 

MHz

 

 

 

 

 

 

 

 

 

Full-Power Bandwidth

 

 

 

800

 

kHz

 

 

 

 

 

 

 

 

CONVERSION RATE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Conversion Time (Note 4)

tCONV

Internal clock

5.5

 

10

µs

 

 

 

 

 

 

External clock, 2MHz, 12 clocks/conversion

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Track/Hold Acquisition Time

tAZ

 

 

 

1.5

µs

 

 

 

 

 

 

 

 

 

Aperture Delay

 

 

 

10

 

ns

 

 

 

 

 

 

 

 

 

Aperture Jitter

 

 

 

<50

 

ps

 

 

 

 

 

 

 

 

 

Internal Clock Frequency

 

 

 

1.7

 

MHz

 

 

 

 

 

 

 

 

 

2 _______________________________________________________________________________________

Low-Power, 8-Channel,

Serial 10-Bit ADC

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 5V ±5%, fCLK = 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

External compensation, 4.7µF

0.1

 

2.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

External Clock Frequency

 

Internal compensation (Note 5)

0.1

 

0.4

 

MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Used for data transfer only

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ANALOG INPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Common-mode range (any input)

0

 

 

VDD

 

 

 

 

 

 

 

 

 

 

 

 

 

Analog Input Voltage

 

Single-ended range (unipolar only)

0

 

VREF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Unipolar

 

0

 

VREF

V

(Note 6)

 

 

 

 

 

Differential range

 

 

 

 

 

 

 

 

 

 

 

Bipolar

 

-VREF

 

+VREF

 

 

 

 

 

 

-2

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Multiplexer Leakage Current

 

On/off leakage current; VIN = 0V, 5V

 

 

±0.01

±1

 

µA

 

 

 

 

 

 

 

 

 

 

 

 

Input Capacitance

 

(Note 5)

 

 

16

 

 

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

INTERNAL REFERENCE (reference buffer

enabled)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF Output Voltage

 

TA = +25°C (Note 7)

4.066

4.096

4.126

 

V

 

 

 

 

 

 

 

 

 

 

 

 

VREF Short-Circuit Current

 

 

 

 

 

 

 

30

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

VREF Tempco

 

 

 

 

 

 

±30

 

 

 

ppm/°C

 

 

 

 

 

 

 

 

 

 

 

 

Load Regulation (Note 8)

 

0mA to 0.5mA output load

 

 

2.5

 

 

 

mV

 

 

 

 

 

 

 

 

 

 

 

 

Capacitive Bypass at VREF

 

Internal compensation

0

 

 

 

 

µF

 

 

 

 

 

 

 

 

 

 

 

External compensation

4.7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Capacitive Bypass at REFADJ

 

Internal compensation

0.01

 

 

 

 

µF

 

 

 

 

 

 

 

 

 

 

 

External compensation

0.01

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REFADJ Adjustment Range

 

 

 

 

 

 

±1.5

 

 

 

%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXTERNAL REFERENCE AT VREF (buffer

disabled, VREF = 4.096V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Voltage Range

 

 

 

 

2.5

 

VDD +

V

 

 

 

 

 

50mV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Current

 

 

 

 

 

 

200

350

 

µA

 

 

 

 

 

 

 

 

 

 

 

 

Input Resistance

 

 

 

 

12

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Shutdown VREF Input Current

 

 

 

 

 

 

1.5

10

 

µA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Buffer Disable Threshold

 

 

 

 

VDD -

 

 

 

 

V

 

 

 

 

 

 

 

 

REFADJ

 

 

 

 

50mV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXTERNAL REFERENCE AT REFADJ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Capacitive Bypass at VREF

 

Internal compensation mode

0

 

 

 

 

µF

 

 

 

 

 

 

 

 

 

 

 

External compensation mode

4.7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reference-Buffer Gain

 

 

 

 

 

 

1.678

 

 

 

V/V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REFADJ Input Current

 

 

 

 

 

 

 

±50

 

µA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX192

_______________________________________________________________________________________ 3

MAX192

Low-Power, 8-Channel,

Serial 10-Bit ADC

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 5V ±5%, fCLK = 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7µF capacitor at VREF pin, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

 

–—– –———–

 

 

 

 

 

 

 

 

 

 

 

 

DIGITALEXTERNALINPUTSREFERE(DIN,CESCLK,AT REFADJCS , SHDN )

 

 

 

 

 

 

DIN,SCLK, CS Input High Voltage

VINH

 

2.4

 

 

V

 

 

 

 

 

 

 

 

 

DIN,SCLK, CS Input Low Voltage

VINL

 

 

 

0.8

V

 

 

 

 

 

 

 

 

 

DIN, SCLK, CS Input Hysteresis

VHYST

 

 

0.15

 

V

 

 

 

 

 

 

 

 

 

DIN, SCLK, CS Input Leakage

IIN

VIN = 0V or VDD

 

 

±1

µA

 

 

 

 

 

 

 

 

 

DIN,SCLK, CS Input Capacitance

CIN

(Note 5)

 

 

15

pF

 

 

 

 

 

 

 

 

 

SHDN Input High Voltage

VINH

 

VDD - 0.5

 

 

V

 

 

 

 

 

 

 

 

 

SHDN Input Low Voltage

VINL

 

 

 

0.5

V

 

 

 

 

 

 

 

 

 

SHDN Input Current, High

IINH

SHDN = VDD

 

 

4.0

µA

 

 

 

 

 

 

 

 

 

SHDN Input Current, Low

IINL

SHDN = 0V

-4.0

 

 

µA

 

 

 

 

 

 

 

 

 

SHDN Input Mid Voltage

VIM

 

1.5

 

VDD - 1.5

V

 

 

 

 

 

 

 

 

 

SHDN Voltage, Floating

VFLT

SHDN = open

 

2.75

 

V

 

 

 

 

 

 

 

 

 

SHDN Max Allowed Leakage,

 

SHDN = open

-100

 

100

nA

 

Mid Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIGITAL OUTPUTS (DOUT, SSTRB)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Voltage Low

VOL

ISINK = 5mA

 

 

0.4

V

 

 

 

 

ISINK = 16mA

 

0.3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Voltage High

VOH

ISOURCE = 1mA

4

 

 

V

 

 

 

 

 

 

 

 

 

Three-State Leakage Current

IL

CS = 5V

 

 

±10

µA

 

 

 

 

 

 

 

 

 

Three-State Leakage Capacitance

COUT

CS = 5V (Note 5)

 

 

15

pF

 

 

 

 

 

 

 

 

 

POWER REQUIREMENTS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Positive Supply Voltage

VDD

 

 

5 ±5%

 

V

 

 

 

 

 

 

 

 

 

 

 

Operating mode

 

1.5

2.5

mA

 

 

 

 

 

 

 

 

 

Positive Supply Current

IDD

Fast power-down

 

30

70

µA

 

 

 

 

 

 

 

 

 

 

Full power-down

 

2

10

 

 

 

 

 

 

 

 

 

 

 

 

 

Positive Supply Rejection

PSR

VDD = 5V ±5%; external reference, 4.096V;

 

±0.06

±0.5

mV

 

(Note 9)

full-scale input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 1: Tested at VDD = 5.0V; single-ended, unipolar.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated.

Note 3: Grounded on-channel; sine wave applied to all off channels.

Note 4: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle. Note 5: Guaranteed by design. Not subject to production testing.

Note 6: The common-mode range for the analog inputs is from AGND to VDD. Note 7: Sample tested to 0.1% AQL.

Note 8: External load should not change during conversion for specified accuracy. Note 9: Measured at VSUPPLY + 5% and VSUPPLY - 5% only.

4 _______________________________________________________________________________________

Low-Power, 8-Channel,

Serial 10-Bit ADC

TIMING CHARACTERISTICS

(VDD = 5V ±5%, TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

 

 

 

Acquisition Time

tAZ

 

1.5

 

 

µs

 

 

 

 

 

 

 

 

 

DIN to SCLK Setup

tDS

 

100

 

 

ns

 

 

 

 

 

 

 

 

 

DIN to SCLK Hold

tDH

 

 

 

0

ns

 

 

 

 

 

 

 

 

 

SCLK Fall to Output Data Valid

tDO

CLOAD = 100pF

20

 

150

ns

 

 

 

 

 

 

 

 

 

CS Fall to Output Enable

tDV

CLOAD = 100pF

 

 

100

ns

 

 

 

 

 

 

 

 

 

CS Rise to Output Disable

tTR

CLOAD = 100pF

 

 

100

ns

 

 

 

 

 

 

 

 

 

CS to SCLK Rise Setup

tCSS

 

100

 

 

ns

 

 

 

 

 

 

 

 

 

CS to SCLK Rise Hold

tCSH

 

0

 

 

ns

 

 

 

 

 

 

 

 

 

SCLK Pulse Width High

tCH

 

200

 

 

ns

 

 

 

 

 

 

 

 

 

SCLK Pulse Width Low

tCL

 

200

 

 

ns

 

 

 

 

 

 

 

 

 

SCLK Fall to SSTRB

tSSTRB

CLOAD = 100pF

 

 

200

ns

 

 

 

 

 

 

 

 

 

CS Fall to SSTRB Output Enable

tSDV

External clock mode only, CLOAD = 100pF

 

 

200

ns

 

(Note 5)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CS Rise to SSTRB Output

tSTR

External clock mode only, CLOAD = 100pF

 

 

200

ns

Disable (Note 5)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSTRB Rise to SCLK Rise

tSCK

Internal clock mode only

0

 

 

ns

 

(Note 5)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 5: Guaranteed by design. Not subject to production testing.

 

 

 

 

 

MAX192

__________________________________________Typical Operating Characteristics

PSR (LSBs)

POWER-SUPPLY REJECTION vs. TEMPERATURE

0.30

VDD = +5V ±5%

0.25

0.20

0.15

0.10

0.05

0

-0.05

-60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C)

INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE

 

2.456

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(V)

2.455

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREFADJ

2.454

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.453

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.452

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-60 -40 -20 0 20 40 60 80 100 120 140

 

 

 

 

 

TEMPERATURE (°C)

OFFSET MATCHING (LSBs)

CHANNEL-TO-CHANNEL OFFSET MATCHING vs. TEMPERATURE

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0 -60 -40 -20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

_______________________________________________________________________________________ 5

MAX192

Low-Power, 8-Channel,

Serial 10-Bit ADCs

Pin Description

 

PIN

NAME

FUNCTION

 

 

 

 

 

 

1–8

CH0–CH7

Sampling Analog Inputs

 

 

 

 

 

9, 13

AGND

Analog Ground. Also INInput for single-enabled conversions. Connect both AGND pins to

analog ground.

 

 

 

 

 

 

 

 

 

 

 

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX192 down to 10µA (max) supply cur-

10

SHDN

rent, otherwise the MAX192 is fully operational. Pulling SHDN high puts the reference-buffer amplifi-

er in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external

 

 

 

 

 

 

compensation mode.

 

 

 

 

 

11

VREF

Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier.

Add a 4.7µF capacitor to ground when using external compensation mode. Also functions as an

 

 

 

input when used with a precision external reference.

 

 

 

 

 

 

12

REFADJ

Reference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie REFADJ to VDD.

 

 

 

 

 

 

 

14

DGND

Digital Ground

 

 

 

 

 

 

 

15

DOUT

Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is

 

 

high.

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX192 begins the A/D

 

 

16

SSTRB

conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high

 

 

for one clock period before the MSB decision. SSTRB is high impedance when CS is high

 

 

 

 

 

 

 

 

(external mode).

 

 

 

 

 

 

 

17

DIN

Serial Data Input. Data is clocked in at the rising edge of SCLK.

 

 

 

 

 

 

 

18

CS

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT

 

 

is high impedance.

 

 

 

 

 

 

 

 

 

 

 

19

SCLK

Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets

 

 

the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)

 

 

 

 

 

 

 

 

 

 

 

20

VDD

Positive Supply Voltage, +5V ±5%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+3V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3k

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3k

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DOUT

 

 

 

 

DOUT

 

 

 

 

 

 

 

 

 

 

 

DOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3k

 

 

 

 

 

 

 

 

 

 

 

 

CLOAD

 

 

 

 

 

 

 

 

CLOAD

 

 

3k

 

 

 

 

 

 

 

 

 

CLOAD

 

 

 

 

 

 

 

 

CLOAD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DGND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DGND

 

 

 

 

 

 

DGND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DGND

a) High-Z to VOH and VOL to VOH

b) High-Z to VOL and VOH to VOL

 

 

 

 

 

a) VOH to High-Z

 

b) VOL to High-Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1.

Load Circuits for Enable Time

 

Figure 2.

Load Circuits for Disabled Time

6 ________________________________________________________________________________________________

Maxim MAX192BMJP, MAX192BCWP, MAX192BCPP, MAX192BCAP, MAX192AMJP Datasheet

Low-Power, 8-Channel,

Serial 10-Bit ADC

CS

18

 

 

 

 

 

 

 

SCLK

19

 

 

 

 

 

 

 

DIN

17

INPUT

 

 

INT

 

 

 

 

 

SHIFT

CONTROL

CLOCK

 

 

SHDN

10

REGISTER

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

CH0

1

 

 

 

 

OUTPUT

15

DOUT

2

 

 

 

 

CH1

 

 

 

 

 

 

 

 

 

SHIFT

16

 

3

 

 

 

 

 

CH2

 

 

 

 

REGISTER

SSTRB

 

 

 

 

 

CH3

4

ANALOG

T/H

 

 

 

 

 

CH4

5

INPUT

CLOCK

 

 

 

 

 

 

 

MUX

 

 

 

 

CH5

6

 

IN

 

 

 

 

 

 

SAR

 

 

 

CH6

7

 

 

 

 

 

 

 

 

ADC

 

 

 

CH7

8

 

 

 

OUT

 

 

 

 

 

REF

20

 

AGND

13

 

 

 

 

VDD

 

 

 

 

 

AGND

9

+2.46V

 

A 1.65

 

14

DGND

 

 

 

20k

 

 

 

 

 

REFERENCE

 

 

 

 

 

 

 

 

 

 

 

REFADJ

12

 

 

 

 

MAX192

 

 

 

 

 

+4.096V

 

 

VREF

11

 

 

 

 

 

 

 

 

 

 

CAPACITIVE DAC

 

VREF

 

 

 

INPUT

 

CHOLD

COMPARATOR

ZERO

MUX

+

CH0

 

 

 

CH1

 

16pF

 

CH2

 

10k

CH3

 

RS

 

CSWITCH

HOLD

CH4

 

TRACK

CH5

 

AT THE SAMPLING INSTANT,

 

 

CH6

 

T/H

THE MUX INPUT SWITCHES

 

FROM THE SELECTED IN+

CH7

 

 

SWITCH

 

CHANNEL TO THE SELECTED

AGND

 

 

 

 

INCHANNEL.

SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = AGND.

DIFFERENTIAL MODE (BIPOLAR): IN+ AND INSELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.

Figure 3. Block Diagram

Figure 4. Equivalent Input Circuit

MAX192

Detailed Description

The MAX192 uses a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 10-bit digital output. A flexible serial interface provides easy interface to microprocessors. No external hold capacitors are required. Figure 3 shows the block diagram for the MAX192.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog comparator is illustrated in the Equivalent Input Circuit (Figure 4). In single-ended mode, IN+ is internally switched to CH0–CH7 and INis switched to AGND. In differential mode, IN+ and INare selected from pairs of CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Refer to Tables 1 and 2 to configure the channels.

In differential mode, INand IN+ are internally switched to either one of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best results) with

respect to AGND during a conversion. Accomplish this by connecting a 0.1µF capacitor from AIN- (the selected analog input, respectively) to AGND.

During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+.

The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, INis simply AGND. This unbalances node ZERO at the input of the comparator. The capacitive DAC adjusts during the remainder of the conversion cycle to restore its node ZERO to 0V within the limits of its resolution. This action is equivalent to transferring a charge of 16pF x (VIN+ - VIN-) from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal.

_______________________________________________________________________________________ 7

MAX192

Low-Power, 8-Channel,

Serial 10-Bit ADC

Track/Hold

The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. The T/H enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for single-ended inputs, INis connected to AGND, and the converter samples the “+” input. If the converter is set up for differential inputs, INconnects to the “-” input, and the difference of ½IN+ - IN-½ is sampled. At the end of the conversion, the positive input connects back to IN+, and CHOLD charges to the input signal.

The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. Acquisition time is calculated by:

tAZ = 9 (RS + RIN) 16pF

where RIN = 5kΩ , RS = the source impedance of the input signal, and tAZ is never less than 1.5µs. Note that source impedances below 5kW do not significantly affect the AC performance of the ADC. Higher source impedances can be used if an input capacitor is connected to the analog inputs, as shown in Figure 5. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC’s signal bandwidth.

Input Bandwidth

The ADC’s input tracking circuitry has a 4.5MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency

band of interest, anti-alias filtering is recommended. See the data sheets for the MAX291–MAX297 filters.

Analog Input Range and Input Protection

Internal protection diodes, which clamp the analog input to VDD and AGND, allow the channel input pins to swing from AGND - 0.3V to VDD + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV, or be lower than AGND by 50mV.

If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of off channels over 2mA.

The MAX192 can be configured for differential (unipolar or bipolar) or single-ended (unipolar only) inputs, as selected by bits 2 and 3 of the control byte (Table 3).

In the single-ended mode, set the UNI/BIP bit to unipolar. In this mode, analog inputs are internally referenced to AGND, with a full-scale input range from 0V to VREF.

In differential mode, both unipolar and bipolar settings can be used. Choosing unipolar mode sets the differential input range at 0V to VREF. The output code is invalid (code zero) when a negative differential input voltage is applied. Bipolar mode sets the differential input range to ±VREF / 2. Note that in this differential mode, the com- mon-mode input range includes both supply rails. Refer to Tables 4a and 4b for input voltage ranges.

Quick Look

To evaluate the analog performance of the MAX192 quickly, use Figure 5’s circuit. The MAX192 requires a control byte to be written to DIN before each conversion. Tying DIN to +5V feeds in control bytes of

Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)

SEL2

SEL1

SEL0

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

AGND

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

 

+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

 

 

+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

 

 

 

+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

0

 

 

 

 

+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

0

 

 

 

 

 

+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

1

 

 

 

 

 

 

+

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

 

 

 

 

 

 

+

 

 

 

 

 

 

 

 

 

 

 

 

8 _______________________________________________________________________________________

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