Maxim MAX188CMJP, MAX188CEWP, MAX188CEPP, MAX188CEAP, MAX188CCWP Datasheet

...
0 (0)

19-0123; Rev. 4; 8/96

KIT

Low-Power, 8-Channel,

EVALUATION

AVAILABLE

 

Serial 12-Bit ADCs

_______________General Description

The MAX186/MAX188 are 12-bit data-acquisition systems that combine an 8-channel multiplexer, high-band- width track/hold, and serial interface together with high conversion speed and ultra-low power consumption. The devices operate with a single +5V supply or dual ±5V supplies. The analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation.

The 4-wire serial interface directly connects to SPI™, QSPI™ and Microwire™ devices without external logic. A serial strobe output allows direct connection to TMS320 family digital signal processors. The MAX186/MAX188 use either the internal clock or an external serial-interface clock to perform successive-approximation A/D conversions. The serial interface can operate beyond 4MHz when the internal clock is used.

The MAX186 has an internal 4.096V reference while the MAX188 requires an external reference. Both parts have a reference-buffer amplifier that simplifies gain trim .

The MAX186/MAX188 provide a hard-wired SHDN pin and two software-selectable power-down modes. Accessing the serial interface automatically powers up the devices, and the quick turn-on time allows the MAX186/MAX188 to be shut down between every conversion. Using this technique of powering down between conversions, supply current can be cut to under 10µA at reduced sampling rates.

The MAX186/MAX188 are available in 20-pin DIP and SO packages, and in a shrink small-outline package (SSOP), that occupies 30% less area than an 8-pin DIP. For applications that call for a parallel interface, see the MAX180/MAX181 data sheet. For anti-aliasing filters, consult the MAX274/MAX275 data sheet.

________________________Applications

Portable Data Logging

Data-Acquisition

High-Accuracy Process Control

Automatic Testing

Robotics

Battery-Powered Instruments

Medical Instruments

SPI and QSPI are registered trademarks of Motorola.

Microwire is a registered trademark of National Semiconductor.

____________________________Features

8-Channel Single-Ended or 4-Channel Differential Inputs

Single +5V or ±5V Operation

Low Power: 1.5mA (operating mode)

2µA (power-down mode)

Internal Track/Hold, 133kHz Sampling Rate

Internal 4.096V Reference (MAX186)

SPI-, QSPI-, Microwire-, TMS320-Compatible 4-Wire Serial Interface

Software-Configurable Unipolar or Bipolar Inputs

20-Pin DIP, SO, SSOP Packages

Evaluation Kit Available

______________Ordering Information

PART

TEMP. RANGE

PIN-PACKAGE

MAX186_CPP

0°C to +70°C

20 Plastic DIP

 

 

 

MAX186_CWP

0°C to +70°C

20 SO

 

 

 

MAX186_CAP

0°C to +70°C

20 SSOP

 

 

 

MAX186DC/D

0°C to +70°C

Dice*

 

 

 

MAX186_EPP

-40°C to +85°C

20 Plastic DIP

 

 

 

MAX186_EWP

-40°C to +85°C

20 SO

 

 

 

MAX186_EAP

-40°C to +85°C

20 SSOP

 

 

 

MAX186_MJP

-55°C to +125°C

20 CERDIP**

 

 

 

Ordering Information continued on last page.

NOTE: Parts are offered in grades A, B, C and D (grades defined in Electrical Characteristics). When ordering, please specify grade. Contact factory for availability of A-grade in SSOP package.

*Dice are specified at +25°C, DC parameters only.

** Contact factory for availability and processing to MIL-STD-883.

____________________Pin Configuration

TOP VIEW

 

 

 

 

 

 

 

 

 

 

 

 

 

CH0

 

 

 

 

VDD

 

 

1

 

20

 

 

 

 

 

 

 

 

 

 

 

CH1

 

2

 

19

SCLK

 

 

 

 

 

 

 

 

 

 

 

CH2

 

3

 

18

 

CS

 

 

CH3

 

 

 

 

 

 

 

 

 

4

MAX186

17

DIN

 

 

 

 

 

 

 

 

 

 

CH4

 

5

MAX188

16

SSTRB

 

 

 

 

 

 

 

 

 

 

 

CH5

 

6

 

15

DOUT

 

CH6

 

 

 

 

DGND

 

 

7

 

14

 

 

 

 

 

 

 

 

 

 

 

CH7

 

8

 

13

AGND

 

 

 

 

 

 

 

 

 

 

 

VSS

 

9

 

12

REFADJ

 

 

 

 

 

 

 

 

 

 

SHDN

10

 

11

VREF

 

 

 

 

 

 

 

 

 

 

DIP/SO/SSOP

________________________________________________________________ Maxim Integrated Products 1

MAX186/MAX188

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

MAX186/MAX188

Low-Power, 8-Channel,

Serial 12-Bit ADCs

ABSOLUTE MAXIMUM RATINGS

VDD to AGND............................................................

-0.3V to +6V

VSS to AGND ............................................................

+0.3V to -6V

VDD to VSS ..............................................................

-0.3V to +12V

AGND to DGND.....................................................

-0.3V to +0.3V

CH0–CH7 to AGND, DGND .............

(VSS - 0.3V) to (VDD + 0.3V)

CH0–CH7 Total Input Current ..........................................

±20mA

VREF to AGND ...........................................

-0.3V to (VDD + 0.3V)

REFADJ to AGND.......................................

-0.3V to (VDD + 0.3V)

Digital Inputs to DGND...............................

-0.3V to (VDD + 0.3V)

Digital Outputs to DGND............................

-0.3V to (VDD + 0.3V)

Digital Output Sink Current .................................................

25mA

Continuous Power Dissipation (TA = +70°C)

 

 

Plastic DIP (derate 11.11mW/°C above +70°C)

...........889mW

SO (derate 10.00mW/°C above +70°C)........................

 

800mW

SSOP (derate 8.00mW/°C above +70°C) .....................

 

640mW

CERDIP (derate 11.11mW/°C above +70°C)................

 

889mW

Operating Temperature Ranges:

 

 

MAX186_C/MAX188_C ........................................

 

0°C to +70°C

MAX186_E/MAX188_E......................................

-40°C to +85°C

MAX186_M/MAX188_M ..................................

-55°C to +125°C

Storage Temperature Range .............................

-60°C to +150°C

Lead Temperature (soldering, 10sec) .............................

 

+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186— 4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

 

 

DC ACCURACY (Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Resolution

 

 

 

12

 

 

Bits

 

 

 

 

 

 

 

 

 

 

MAX186A/MAX188A

 

 

 

±0.5

 

 

 

 

 

 

 

 

 

 

 

MAX186B/MAX188B

 

 

 

±0.5

 

Relative Accuracy (Note 2)

 

 

 

 

 

 

LSB

 

MAX186C

 

 

 

±1.0

 

 

 

 

 

 

 

 

 

 

MAX188C

 

 

 

±0.75

 

 

 

 

 

 

 

 

 

 

 

MAX186D/MAX188D

 

 

 

±1.0

 

 

 

 

 

 

 

 

 

Differential Nonlinearity

DNL

No missing codes over temperature

 

 

±1

LSB

 

 

 

 

 

 

 

 

 

 

MAX186A/MAX188A

 

 

 

±2.0

 

 

 

 

 

 

 

 

 

Offset Error

 

MAX186B/MAX188B

 

 

 

±3.0

LSB

 

 

 

 

 

 

 

MAX186C/MAX188C

 

 

 

±3.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX186D/MAX188D

 

 

 

±3.0

 

 

 

 

 

 

 

 

 

 

 

MAX186 (all grades)

 

 

 

±3.0

 

 

 

 

 

 

 

 

 

 

 

 

MAX188A

 

 

±1.5

 

 

 

 

 

 

 

 

 

Gain Error (Note 3)

 

External reference

MAX188B

 

 

±2.0

LSB

 

 

4.096V (MAX188)

MAX188C

 

 

±2.0

 

 

 

 

 

 

 

 

 

 

 

 

MAX188D

 

 

±3.0

 

 

 

 

 

 

 

 

 

Gain Temperature Coefficient

 

External reference, 4.096V

 

±0.8

 

ppm/°C

 

 

 

 

 

 

 

 

Channel-to-Channel

 

 

 

 

±0.1

 

LSB

Offset Matching

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DYNAMIC SPECIFICATIONS (10kHz sine wave input, 4.096VP-P, 133ksps, 2.0MHz external clock, bipolar input mode)

 

Signal-to-Noise + Distortion Ratio

SINAD

 

 

70

 

 

dB

 

 

 

 

 

 

 

 

Total Harmonic Distortion

THD

 

 

 

 

-80

dB

(up to the 5th harmonic)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Spurious-Free Dynamic Range

SFDR

 

 

80

 

 

dB

 

 

 

 

 

 

 

 

Channel-to-Channel Crosstalk

 

65kHz, VIN = 4.096VP-P (Note 4)

 

-85

 

dB

2 _______________________________________________________________________________________

Low-Power, 8-Channel,

Serial 12-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186— 4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

 

 

Small-Signal Bandwidth

 

-3dB rolloff

 

4.5

 

MHz

 

 

 

 

 

 

 

 

Full-Power Bandwidth

 

 

 

 

800

 

kHz

 

 

 

 

 

 

 

 

CONVERSION RATE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Conversion Time (Note 5)

t CONV

Internal clock

5.5

 

10

µs

 

 

 

 

 

External clock, 2MHz, 12 clocks/conversion

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Track/Hold Acquisition Time

tAZ

 

 

 

 

1.5

µs

 

 

 

 

 

 

 

 

Aperture Delay

 

 

 

 

10

 

ns

 

 

 

 

 

 

 

 

Aperture Jitter

 

 

 

 

<50

 

ps

 

 

 

 

 

 

 

 

Internal Clock Frequency

 

 

 

 

1.7

 

MHz

 

 

 

 

 

 

 

 

 

 

External compensation, 4.7µF

0.1

 

2.0

 

 

 

 

 

 

 

 

 

External Clock Frequency Range

 

Internal compensation (Note 6)

0.1

 

0.4

MHz

 

 

 

 

 

 

 

 

 

 

Used for data transfer only

 

10

 

 

 

 

 

 

 

 

 

 

ANALOG INPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Voltage Range,

 

Unipolar, VSS = 0V

 

 

0 to

 

 

 

 

VREF

V

Single-Ended and Differential

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(Note 9)

 

Bipolar, VSS = -5V

 

 

±VREF/2

 

 

 

 

 

 

 

 

 

Multiplexer Leakage Current

 

On/off leakage current, VIN = ±5V

 

±0.01

±1

µA

Input Capacitance

 

(Note 6)

 

16

 

pF

 

 

 

 

 

 

 

 

INTERNAL REFERENCE (MAX186 only, reference buffer enabled)

 

 

 

 

 

 

 

 

 

 

 

VREF Output Voltage

 

TA = +25°C

4.076

4.096

4.116

V

VREF Short-Circuit Current

 

 

 

 

 

30

mA

 

 

 

 

 

 

 

 

 

 

MAX186A, MAX186B,

MAX186_C

 

±30

±50

 

 

 

 

 

 

 

 

 

 

MAX186_E

 

±30

±60

 

VREF Tempco

 

MAX186C

 

 

 

 

ppm/°C

 

MAX186_M

 

±30

±80

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX186D

 

±30

 

 

 

 

 

 

 

 

 

Load Regulation (Note 7)

 

0mA to 0.5mA output load

 

2.5

 

mV

 

 

 

 

 

 

 

Capacitive Bypass at VREF

 

Internal compensation

0

 

 

µF

 

 

 

 

 

 

 

External compensation

4.7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Capacitive Bypass at REFADJ

 

Internal compensation

0.01

 

 

µF

 

 

 

 

 

 

 

External compensation

0.01

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REFADJ Adjustment Range

 

 

 

 

±1.5

 

%

 

 

 

 

 

 

 

 

EXTERNAL REFERENCE AT VREF (Buffer disabled, VREF = 4.096V)

 

 

 

 

 

 

 

 

 

 

 

 

Input Voltage Range

 

 

 

2.50

 

VDD +

V

 

 

 

 

50mV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Current

 

 

 

 

200

350

µA

 

 

 

 

 

 

 

 

Input Resistance

 

 

 

12

20

 

 

 

 

 

 

 

 

 

Shutdown VREF Input Current

 

 

 

 

1.5

10

µA

 

 

 

 

 

 

 

 

Buffer Disable Threshold REFADJ

 

 

 

VDD -

 

 

V

 

 

 

50mV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX186/MAX188

_______________________________________________________________________________________ 3

MAX186/MAX188

Low-Power, 8-Channel,

Serial 12-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186— 4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

 

EXTERNAL REFERENCE AT REFADJ

 

 

 

 

 

 

 

 

 

 

 

 

 

Capacitive Bypass at VREF

 

 

Internal compensation mode

0

 

 

µF

 

 

 

 

 

 

 

 

External compensation mode

4.7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reference-Buffer Gain

 

 

MAX186

 

1.678

 

V/V

 

 

 

 

 

 

 

 

MAX188

 

1.638

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REFADJ Input Current

 

 

MAX186

 

 

±50

µA

 

 

 

 

 

 

 

 

MAX188

 

 

±5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIGITAL INPUTS (DIN, SCLK,

,

)

 

 

 

 

 

 

 

 

 

 

 

 

 

DIN, SCLK, CS Input High Voltage

 

VINH

 

2.4

 

 

V

 

 

 

 

 

 

 

 

DIN, SCLK, CS Input Low Voltage

 

VINL

 

 

 

0.8

V

 

 

 

 

 

 

 

 

DIN, SCLK, CS Input Hysteresis

 

VHYST

 

 

0.15

 

V

 

 

 

 

 

 

 

 

DIN, SCLK, CS Input Leakage

 

IIN

VIN = 0V or VDD

 

 

±1

µA

DIN, SCLK, CS Input Capacitance

 

CIN

(Note 6)

 

 

15

pF

SHDN Input High Voltage

 

VINH

 

VDD - 0.5

 

 

V

SHDN Input Low Voltage

 

VINL

 

 

 

0.5

V

 

 

 

 

 

 

 

 

SHDN Input Current, High

 

IINH

SHDN = VDD

 

 

4.0

µA

SHDN Input Current, Low

 

IINL

SHDN = 0V

-4.0

 

 

µA

 

 

 

 

 

 

 

 

SHDN Input Mid Voltage

 

VIM

 

1.5

 

VDD -1.5

V

SHDN Voltage, Floating

 

VFLT

SHDN = open

 

2.75

 

V

 

 

 

 

 

 

 

 

SHDN Max Allowed Leakage,

 

 

SHDN = open

-100

 

100

nA

Mid Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIGITAL OUTPUTS (DOUT, SSTRB)

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Voltage Low

 

VOL

ISINK = 5mA

 

 

0.4

V

 

ISINK = 16mA

 

0.3

 

 

 

 

 

 

 

Output Voltage High

 

VOH

ISOURCE = 1mA

4

 

 

V

 

 

 

 

 

 

 

 

Three-State Leakage Current

 

IL

CS = 5V

 

 

±10

µA

Three-State Output Capacitance

 

COUT

CS = 5V (Note 6)

 

 

15

pF

 

 

 

 

 

 

 

 

POWER REQUIREMENTS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Positive Supply Voltage

 

VDD

 

 

5 ±5%

 

V

 

 

 

 

 

 

 

 

Negative Supply Voltage

 

VSS

 

 

0 or

 

V

 

 

 

-5 ±5%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operating mode

 

1.5

2.5

mA

 

 

 

 

 

 

 

 

Positive Supply Current

 

IDD

Fast power-down

 

30

70

µA

 

 

 

Full power-down

 

2

10

 

 

 

 

 

 

 

 

 

 

 

 

 

Negative Supply Current

 

ISS

Operating mode and fast power-down

 

 

50

µA

 

 

 

 

 

 

Full power-down

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 _______________________________________________________________________________________

Low-Power, 8-Channel,

Serial 12-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186— 4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

 

Positive Supply Rejection

PSR

VDD = 5V ±5%; external reference, 4.096V;

 

±0.06

±0.5

mV

(Note 8)

full-scale input

 

 

 

 

 

 

 

 

 

 

 

 

 

Negative Supply Rejection

PSR

VSS = -5V ±5%; external reference, 4.096V;

 

±0.01

±0.5

mV

(Note 8)

full-scale input

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 1: Tested at VDD = 5.0V; VSS = 0V; unipolar input mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated.

Note 3: MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled. Note 4: Ground on-channel; sine wave applied to all off channels.

Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle. Note 6: Guaranteed by design. Not subject to production testing.

Note 7: External load should not change during conversion for specified accuracy.

Note 8: Measured at VSUPPLY +5% and VSUPPLY -5% only.

Note 9: The common-mode range for the analog inputs is from VSS to VDD.

TIMING CHARACTERISTICS

(VDD = 5V ±5%; VSS =0V or -5V, TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

 

 

Acquisition Time

tAZ

 

 

1.5

 

 

µs

DIN to SCLK Setup

tDS

 

 

100

 

 

ns

DIN to SCLK Hold

tDH

 

 

 

 

0

ns

SCLK Fall to Output Data Valid

tDO

CLOAD = 100pF

MAX18_ _C/E

20

 

150

ns

 

 

 

 

 

MAX18_ _M

20

 

200

ns

 

 

 

 

 

 

 

 

 

 

 

 

CS Fall to Output Enable

tDV

CLOAD = 100pF

 

 

 

100

ns

CS Rise to Output Disable

tTR

CLOAD = 100pF

 

 

100

ns

CS to SCLK Rise Setup

tCSS

 

 

100

 

 

ns

CS to SCLK Rise Hold

tCSH

 

 

0

 

 

ns

SCLK Pulse Width High

tCH

 

 

200

 

 

ns

SCLK Pulse Width Low

tCL

 

 

200

 

 

ns

SCLK Fall to SSTRB

tSSTRB

CLOAD = 100pF

 

 

200

ns

CS Fall to SSTRB Output Enable

tSDV

External clock mode only, CLOAD = 100pF

 

 

200

ns

(Note 6)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CS Rise to SSTRB Output Disable

tSTR

External clock mode only, CLOAD = 100pF

 

 

200

ns

(Note 6)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSTRB Rise to SCLK Rise

tSCK

Internal clock mode only

0

 

 

ns

(Note 6)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX186/MAX188

_______________________________________________________________________________________ 5

MAX186/MAX188

Low-Power, 8-Channel,

Serial 12-Bit ADCs

__________________________________________Typical Operating Characteristics

 

 

 

POWER-SUPPLY REJECTION

 

INTERNAL REFERENCE VOLTAGE

 

CHANNEL-TO-CHANNEL OFFSET MATCHING

 

 

 

 

vs. TEMPERATURE

 

 

 

vs. TEMPERATURE

 

 

 

vs. TEMPERATURE

 

0.30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.25

 

 

 

 

 

 

 

VDD = +5V ±5%

 

 

2.456

 

 

 

 

 

 

 

 

 

 

 

0.14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS = 0V or -5V

 

 

 

 

 

 

 

 

 

 

 

 

 

(LSBs)

0.12

 

 

 

 

 

 

 

 

 

 

 

 

0.20

 

 

 

 

 

 

 

 

 

2.455

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(LSBs)PSR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(V)VREFADJ

 

 

 

 

 

 

 

 

 

 

MATCHINGOFFSET

0.04

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.15

 

 

 

 

 

 

 

 

 

 

 

 

 

2.454

 

 

 

 

 

 

 

 

 

 

 

0.10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.08

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.453

 

 

 

 

 

 

 

 

 

 

 

0.06

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.05

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.00

 

 

 

 

 

 

 

 

 

 

 

 

 

2.452

 

 

 

 

 

 

 

 

 

 

 

0.02

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-0.05

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-40 -20 0 20 40 60 80 100 120

 

 

 

 

 

 

 

 

 

 

 

 

 

-60 -40 -20 0 20 40 60 80 100 120 140

 

-60 -40 -20 0 20 40 60 80 100 120 140

 

 

 

 

TEMPERATURE (°C)

 

 

 

TEMPERATURE (°C)

 

 

 

 

TEMPERATURE (°C)

 

 

 

MAX186/MAX188 FFT PLOT – 133kHz

 

 

 

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

-20

 

 

 

 

 

 

(dB)

 

 

ft = 10kHz

 

 

 

 

 

 

 

 

 

-40

 

 

fs = 133kHz

 

 

 

AMPLITUDE

-60

 

 

TA = +25°C

 

 

 

 

 

 

 

 

 

-80

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-100

 

 

 

 

 

 

 

-120

 

 

 

 

 

 

 

-140

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

33.25kHz

66.5kHz

 

 

 

FREQUENCY

 

 

_____________________________________________________________Pin Description

PIN

NAME

FUNCTION

 

 

 

1-8

CH0-CH7

Sampling Analog Inputs

 

 

 

9

VSS

Negative Supply Voltage. Tie to -5V ±5% or AGND

 

 

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX186/MAX188 down to 10µA (max)

10

SHDN

supply current, otherwise the MAX186/MAX188 are fully operational. Pulling SHDN high puts the ref-

erence-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer

 

 

 

 

amplifier in external compensation mode.

 

 

 

 

 

Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier

11

VREF

(4.096V in the MAX186, 1.638 x REFADJ in the MAX188). Add a 4.7µF capacitor to ground when

using external compensation mode. Also functions as an input when used with a precision external

 

 

 

 

reference.

 

 

 

6 ________________________________________________________________________________________________

Maxim MAX188CMJP, MAX188CEWP, MAX188CEPP, MAX188CEAP, MAX188CCWP Datasheet

Low-Power, 8-Channel,

Serial 12-Bit ADCs

________________________________________________Pin Description (continued)

PIN

NAME

FUNCTION

 

 

 

12

REFADJ

Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to

VDD.

 

 

13

AGND

Analog Ground. Also INInput for single-ended conversions.

 

 

 

14

DGND

Digital Ground

 

 

 

15

DOUT

Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.

 

 

 

 

 

Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the

16

SSTRB

A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses

 

 

high for one clock period before the MSB decision. High impedance when CS is high (external mode).

 

 

 

17

DIN

Serial Data Input. Data is clocked in at the rising edge of SCLK.

 

 

 

18

CS

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT

is high impedance.

 

 

 

 

 

19

SCLK

Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets

the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)

 

 

 

 

 

20

VDD

Positive Supply Voltage, +5V ±5%

 

 

 

+5V

 

 

 

 

 

 

 

 

 

DOUT

 

 

3k

CS

18

 

 

 

 

 

 

 

 

 

DOUT

 

 

 

 

 

 

 

 

 

 

 

SCLK

19

 

 

 

 

 

 

 

 

3k

CLOAD

CLOAD

DIN

17

INPUT

 

 

INT

 

 

 

 

SHIFT

 

 

 

 

 

 

 

 

 

 

 

 

 

CLOCK

 

 

 

 

 

 

 

SHDN

10

REGISTER

CONTROL

 

 

 

 

 

DGND

DGND

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a. High-Z to VOH and VOL to VOH

b. High-Z to VOL and VOH to VOL

CH0

1

 

 

 

 

OUTPUT

15

DOUT

2

 

 

 

 

CH1

 

 

 

 

 

 

 

 

 

3

 

 

 

 

SHIFT

16

 

 

 

 

 

CH2

 

 

 

 

REGISTER

SSTRB

Figure 1.

Load Circuits for Enable Time

 

 

 

 

 

CH3

4

ANALOG

T/H

 

 

 

 

 

 

 

 

 

CH4

5

INPUT

 

CLOCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MUX

 

 

 

 

 

 

 

 

 

CH5

6

 

 

IN12-BIT

 

 

 

 

 

 

+5V

 

 

 

 

 

 

 

 

 

CH6

7

 

 

 

 

 

 

 

 

 

 

 

 

SAR

 

 

 

 

 

 

 

CH7

8

 

 

 

ADC OUT

20

 

 

 

 

3k

AGND

13

 

 

 

REF

 

VDD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A 1.65

 

14

DOUT

 

DOUT

 

 

 

+2.46V

20k

 

DGND

 

 

 

 

 

 

REFERENCE

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

 

 

12

(MAX186)

 

 

 

VSS

 

3k

CLOAD

CLOAD

REFADJ

 

 

 

 

MAX186

 

 

 

 

 

 

 

 

 

11

 

 

 

+4.096V

 

 

 

 

 

 

VREF

 

 

 

MAX188

 

 

 

 

DGND

DGND

 

 

 

 

 

 

 

 

 

 

 

a VOH to High-Z

b VOL to High-Z

 

 

 

 

 

 

 

 

 

Figure 2. Load Circuits for Disabled Time

Figure 3. Block Diagram

MAX186/MAX188

_______________________________________________________________________________________ 7

MAX186/MAX188

Low-Power, 8-Channel,

Serial 12-Bit ADCs

_______________Detailed Description

The MAX186/MAX188 use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to microprocessors. No external hold capacitors are required. Figure 3 shows the block diagram for the MAX186/MAX188.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog comparator is illustrated in the Equivalent Input Circuit (Figure 4). In single-ended mode, IN+ is internally switched to CH0-CH7 and INis switched to AGND. In differential mode, IN+ and INare selected from pairs of CH0/CH1, CH2/CH3, CH4/CH5 and CH6/CH7. Configure the channels with Table 3 and Table 4.

In differential mode, INand IN+ are internally switched to either one of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best results) with respect to AGND during a conversion. Accomplish this by connecting a 0.1µF capacitor from AIN- (the selected analog input, respectively) to AGND.

During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+.

The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, INis simply AGND. This unbalances node ZERO at the input of the comparator. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 12-bit resolution. This action is equivalent to transferring a charge of 16pF x

[(VIN+) - (VIN-)] from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital represen-

tation of the analog input signal.

Track/Hold

The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. The T/H enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for

12-BIT CAPACITIVE DAC

 

VREF

 

 

 

 

INPUT

 

CHOLD

 

COMPARATOR

ZERO

 

MUX

+

 

CH0

 

 

 

 

CH1

 

16pF

 

 

CH2

 

 

10k

 

CH3

CSWITCH

RS

 

HOLD

 

CH4

 

TRACK

 

CH5

 

 

AT THE SAMPLING INSTANT,

 

 

 

CH6

 

 

T/H

THE MUX INPUT SWITCHES

 

 

FROM THE SELECTED IN+

CH7

 

 

 

SWITCH

 

CHANNEL TO THE SELECTED

AGND

 

 

 

 

 

 

IN– CHANNEL.

SINGLE-ENDED MODE: IN+ = CHO-CH7, IN– = AGND.

DIFFERENTIAL MODE:

IN+ AND IN– SELECTED FROM PAIRS OF

 

 

CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.

Figure 4. Equivalent Input Circuit

single-ended inputs, INis connected to AGND, and the converter samples the “+” input. If the converter is set up for differential inputs, INconnects to the “-” input, and the difference of |IN+ - IN-| is sampled. At the end of the conversion, the positive input connects back to IN+, and CHOLD charges to the input signal.

The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. Acquisition time is calculated by:

tAZ = 9 x (RS + RIN) x 16pF,

where RIN = 5kΩ , RS = the source impedance of the input signal, and tAZ is never less than 1.5µs. Note that source impedances below 5kΩ do not significantly affect the AC performance of the ADC. Higher source impedances can be used if an input capacitor is connected to the analog inputs, as shown in Figure 5. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC’s signal bandwidth.

Input Bandwidth

The ADC’s input tracking circuitry has a 4.5MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.

8 _______________________________________________________________________________________

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