19-0123; Rev. 4; 8/96
KIT |
Low-Power, 8-Channel, |
EVALUATION |
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AVAILABLE |
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Serial 12-Bit ADCs |
_______________General Description
The MAX186/MAX188 are 12-bit data-acquisition systems that combine an 8-channel multiplexer, high-band- width track/hold, and serial interface together with high conversion speed and ultra-low power consumption. The devices operate with a single +5V supply or dual ±5V supplies. The analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation.
The 4-wire serial interface directly connects to SPI™, QSPI™ and Microwire™ devices without external logic. A serial strobe output allows direct connection to TMS320 family digital signal processors. The MAX186/MAX188 use either the internal clock or an external serial-interface clock to perform successive-approximation A/D conversions. The serial interface can operate beyond 4MHz when the internal clock is used.
The MAX186 has an internal 4.096V reference while the MAX188 requires an external reference. Both parts have a reference-buffer amplifier that simplifies gain trim .
The MAX186/MAX188 provide a hard-wired SHDN pin and two software-selectable power-down modes. Accessing the serial interface automatically powers up the devices, and the quick turn-on time allows the MAX186/MAX188 to be shut down between every conversion. Using this technique of powering down between conversions, supply current can be cut to under 10µA at reduced sampling rates.
The MAX186/MAX188 are available in 20-pin DIP and SO packages, and in a shrink small-outline package (SSOP), that occupies 30% less area than an 8-pin DIP. For applications that call for a parallel interface, see the MAX180/MAX181 data sheet. For anti-aliasing filters, consult the MAX274/MAX275 data sheet.
________________________Applications
Portable Data Logging
Data-Acquisition
High-Accuracy Process Control
Automatic Testing
Robotics
Battery-Powered Instruments
Medical Instruments
SPI and QSPI are registered trademarks of Motorola.
Microwire is a registered trademark of National Semiconductor.
____________________________Features
♦8-Channel Single-Ended or 4-Channel Differential Inputs
♦Single +5V or ±5V Operation
♦Low Power: 1.5mA (operating mode)
2µA (power-down mode)
♦Internal Track/Hold, 133kHz Sampling Rate
♦Internal 4.096V Reference (MAX186)
♦SPI-, QSPI-, Microwire-, TMS320-Compatible 4-Wire Serial Interface
♦Software-Configurable Unipolar or Bipolar Inputs
♦20-Pin DIP, SO, SSOP Packages
♦Evaluation Kit Available
______________Ordering Information
PART† |
TEMP. RANGE |
PIN-PACKAGE |
MAX186_CPP |
0°C to +70°C |
20 Plastic DIP |
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MAX186_CWP |
0°C to +70°C |
20 SO |
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MAX186_CAP |
0°C to +70°C |
20 SSOP |
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MAX186DC/D |
0°C to +70°C |
Dice* |
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MAX186_EPP |
-40°C to +85°C |
20 Plastic DIP |
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MAX186_EWP |
-40°C to +85°C |
20 SO |
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MAX186_EAP |
-40°C to +85°C |
20 SSOP |
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MAX186_MJP |
-55°C to +125°C |
20 CERDIP** |
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Ordering Information continued on last page.
† NOTE: Parts are offered in grades A, B, C and D (grades defined in Electrical Characteristics). When ordering, please specify grade. Contact factory for availability of A-grade in SSOP package.
*Dice are specified at +25°C, DC parameters only.
** Contact factory for availability and processing to MIL-STD-883.
____________________Pin Configuration
TOP VIEW |
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CH0 |
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VDD |
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1 |
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20 |
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CH1 |
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2 |
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19 |
SCLK |
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CH2 |
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3 |
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18 |
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CS |
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CH3 |
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4 |
MAX186 |
17 |
DIN |
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CH4 |
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5 |
MAX188 |
16 |
SSTRB |
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CH5 |
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6 |
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15 |
DOUT |
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CH6 |
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DGND |
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7 |
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14 |
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CH7 |
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8 |
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13 |
AGND |
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VSS |
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9 |
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12 |
REFADJ |
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SHDN |
10 |
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11 |
VREF |
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DIP/SO/SSOP
________________________________________________________________ Maxim Integrated Products 1
MAX186/MAX188
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to AGND............................................................ |
-0.3V to +6V |
VSS to AGND ............................................................ |
+0.3V to -6V |
VDD to VSS .............................................................. |
-0.3V to +12V |
AGND to DGND..................................................... |
-0.3V to +0.3V |
CH0–CH7 to AGND, DGND ............. |
(VSS - 0.3V) to (VDD + 0.3V) |
CH0–CH7 Total Input Current .......................................... |
±20mA |
VREF to AGND ........................................... |
-0.3V to (VDD + 0.3V) |
REFADJ to AGND....................................... |
-0.3V to (VDD + 0.3V) |
Digital Inputs to DGND............................... |
-0.3V to (VDD + 0.3V) |
Digital Outputs to DGND............................ |
-0.3V to (VDD + 0.3V) |
Digital Output Sink Current ................................................. |
25mA |
Continuous Power Dissipation (TA = +70°C) |
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Plastic DIP (derate 11.11mW/°C above +70°C) |
...........889mW |
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SO (derate 10.00mW/°C above +70°C)........................ |
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800mW |
SSOP (derate 8.00mW/°C above +70°C) ..................... |
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640mW |
CERDIP (derate 11.11mW/°C above +70°C)................ |
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889mW |
Operating Temperature Ranges: |
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MAX186_C/MAX188_C ........................................ |
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0°C to +70°C |
MAX186_E/MAX188_E...................................... |
-40°C to +85°C |
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MAX186_M/MAX188_M .................................. |
-55°C to +125°C |
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Storage Temperature Range ............................. |
-60°C to +150°C |
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Lead Temperature (soldering, 10sec) ............................. |
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+300°C |
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186— 4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER |
SYMBOL |
CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
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DC ACCURACY (Note 1) |
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Resolution |
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12 |
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Bits |
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MAX186A/MAX188A |
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±0.5 |
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MAX186B/MAX188B |
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±0.5 |
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Relative Accuracy (Note 2) |
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LSB |
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MAX186C |
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±1.0 |
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MAX188C |
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±0.75 |
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MAX186D/MAX188D |
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±1.0 |
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Differential Nonlinearity |
DNL |
No missing codes over temperature |
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±1 |
LSB |
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MAX186A/MAX188A |
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±2.0 |
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Offset Error |
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MAX186B/MAX188B |
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±3.0 |
LSB |
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MAX186C/MAX188C |
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±3.0 |
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MAX186D/MAX188D |
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±3.0 |
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MAX186 (all grades) |
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±3.0 |
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MAX188A |
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±1.5 |
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Gain Error (Note 3) |
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External reference |
MAX188B |
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±2.0 |
LSB |
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4.096V (MAX188) |
MAX188C |
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±2.0 |
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MAX188D |
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±3.0 |
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Gain Temperature Coefficient |
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External reference, 4.096V |
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±0.8 |
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ppm/°C |
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Channel-to-Channel |
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±0.1 |
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LSB |
Offset Matching |
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DYNAMIC SPECIFICATIONS (10kHz sine wave input, 4.096VP-P, 133ksps, 2.0MHz external clock, bipolar input mode) |
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Signal-to-Noise + Distortion Ratio |
SINAD |
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70 |
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dB |
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Total Harmonic Distortion |
THD |
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-80 |
dB |
(up to the 5th harmonic) |
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Spurious-Free Dynamic Range |
SFDR |
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80 |
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dB |
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Channel-to-Channel Crosstalk |
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65kHz, VIN = 4.096VP-P (Note 4) |
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-85 |
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dB |
2 _______________________________________________________________________________________
Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186— 4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER |
SYMBOL |
CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
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Small-Signal Bandwidth |
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-3dB rolloff |
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4.5 |
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MHz |
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Full-Power Bandwidth |
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800 |
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kHz |
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CONVERSION RATE |
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Conversion Time (Note 5) |
t CONV |
Internal clock |
5.5 |
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10 |
µs |
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External clock, 2MHz, 12 clocks/conversion |
6 |
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Track/Hold Acquisition Time |
tAZ |
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1.5 |
µs |
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Aperture Delay |
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10 |
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ns |
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Aperture Jitter |
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<50 |
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ps |
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Internal Clock Frequency |
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1.7 |
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MHz |
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External compensation, 4.7µF |
0.1 |
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2.0 |
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External Clock Frequency Range |
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Internal compensation (Note 6) |
0.1 |
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0.4 |
MHz |
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Used for data transfer only |
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10 |
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ANALOG INPUT |
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Input Voltage Range, |
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Unipolar, VSS = 0V |
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0 to |
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VREF |
V |
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Single-Ended and Differential |
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(Note 9) |
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Bipolar, VSS = -5V |
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±VREF/2 |
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Multiplexer Leakage Current |
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On/off leakage current, VIN = ±5V |
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±0.01 |
±1 |
µA |
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Input Capacitance |
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(Note 6) |
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16 |
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pF |
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INTERNAL REFERENCE (MAX186 only, reference buffer enabled) |
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VREF Output Voltage |
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TA = +25°C |
4.076 |
4.096 |
4.116 |
V |
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VREF Short-Circuit Current |
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30 |
mA |
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MAX186A, MAX186B, |
MAX186_C |
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±30 |
±50 |
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MAX186_E |
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±30 |
±60 |
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VREF Tempco |
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MAX186C |
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ppm/°C |
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MAX186_M |
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±30 |
±80 |
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MAX186D |
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±30 |
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Load Regulation (Note 7) |
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0mA to 0.5mA output load |
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2.5 |
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mV |
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Capacitive Bypass at VREF |
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Internal compensation |
0 |
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µF |
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External compensation |
4.7 |
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Capacitive Bypass at REFADJ |
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Internal compensation |
0.01 |
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µF |
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External compensation |
0.01 |
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REFADJ Adjustment Range |
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±1.5 |
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% |
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EXTERNAL REFERENCE AT VREF (Buffer disabled, VREF = 4.096V) |
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Input Voltage Range |
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2.50 |
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VDD + |
V |
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50mV |
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Input Current |
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200 |
350 |
µA |
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Input Resistance |
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12 |
20 |
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kΩ |
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Shutdown VREF Input Current |
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1.5 |
10 |
µA |
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Buffer Disable Threshold REFADJ |
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VDD - |
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V |
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50mV |
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MAX186/MAX188
_______________________________________________________________________________________ 3
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186— 4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER |
SYMBOL |
CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
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EXTERNAL REFERENCE AT REFADJ |
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Capacitive Bypass at VREF |
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Internal compensation mode |
0 |
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µF |
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External compensation mode |
4.7 |
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Reference-Buffer Gain |
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MAX186 |
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1.678 |
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V/V |
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MAX188 |
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1.638 |
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REFADJ Input Current |
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MAX186 |
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±50 |
µA |
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MAX188 |
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±5 |
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DIGITAL INPUTS (DIN, SCLK, |
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DIN, SCLK, CS Input High Voltage |
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VINH |
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2.4 |
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V |
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DIN, SCLK, CS Input Low Voltage |
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VINL |
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0.8 |
V |
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DIN, SCLK, CS Input Hysteresis |
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VHYST |
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0.15 |
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V |
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DIN, SCLK, CS Input Leakage |
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IIN |
VIN = 0V or VDD |
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±1 |
µA |
DIN, SCLK, CS Input Capacitance |
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CIN |
(Note 6) |
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15 |
pF |
SHDN Input High Voltage |
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VINH |
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VDD - 0.5 |
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V |
SHDN Input Low Voltage |
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VINL |
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0.5 |
V |
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SHDN Input Current, High |
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IINH |
SHDN = VDD |
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4.0 |
µA |
SHDN Input Current, Low |
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IINL |
SHDN = 0V |
-4.0 |
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µA |
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SHDN Input Mid Voltage |
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VIM |
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1.5 |
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VDD -1.5 |
V |
SHDN Voltage, Floating |
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VFLT |
SHDN = open |
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2.75 |
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V |
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SHDN Max Allowed Leakage, |
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SHDN = open |
-100 |
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100 |
nA |
Mid Input |
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DIGITAL OUTPUTS (DOUT, SSTRB) |
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Output Voltage Low |
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VOL |
ISINK = 5mA |
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0.4 |
V |
|
ISINK = 16mA |
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0.3 |
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Output Voltage High |
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VOH |
ISOURCE = 1mA |
4 |
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V |
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Three-State Leakage Current |
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IL |
CS = 5V |
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±10 |
µA |
Three-State Output Capacitance |
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COUT |
CS = 5V (Note 6) |
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15 |
pF |
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POWER REQUIREMENTS |
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Positive Supply Voltage |
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VDD |
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5 ±5% |
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V |
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Negative Supply Voltage |
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VSS |
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0 or |
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V |
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-5 ±5% |
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Operating mode |
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1.5 |
2.5 |
mA |
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Positive Supply Current |
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IDD |
Fast power-down |
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30 |
70 |
µA |
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Full power-down |
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2 |
10 |
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Negative Supply Current |
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ISS |
Operating mode and fast power-down |
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50 |
µA |
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Full power-down |
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10 |
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4 _______________________________________________________________________________________
Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186— 4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER |
SYMBOL |
CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
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Positive Supply Rejection |
PSR |
VDD = 5V ±5%; external reference, 4.096V; |
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±0.06 |
±0.5 |
mV |
(Note 8) |
full-scale input |
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Negative Supply Rejection |
PSR |
VSS = -5V ±5%; external reference, 4.096V; |
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±0.01 |
±0.5 |
mV |
(Note 8) |
full-scale input |
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Note 1: Tested at VDD = 5.0V; VSS = 0V; unipolar input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated.
Note 3: MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled. Note 4: Ground on-channel; sine wave applied to all off channels.
Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle. Note 6: Guaranteed by design. Not subject to production testing.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: Measured at VSUPPLY +5% and VSUPPLY -5% only.
Note 9: The common-mode range for the analog inputs is from VSS to VDD.
TIMING CHARACTERISTICS
(VDD = 5V ±5%; VSS =0V or -5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER |
SYMBOL |
CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
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Acquisition Time |
tAZ |
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1.5 |
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µs |
DIN to SCLK Setup |
tDS |
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100 |
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ns |
DIN to SCLK Hold |
tDH |
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0 |
ns |
SCLK Fall to Output Data Valid |
tDO |
CLOAD = 100pF |
MAX18_ _C/E |
20 |
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150 |
ns |
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MAX18_ _M |
20 |
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200 |
ns |
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CS Fall to Output Enable |
tDV |
CLOAD = 100pF |
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100 |
ns |
CS Rise to Output Disable |
tTR |
CLOAD = 100pF |
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100 |
ns |
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CS to SCLK Rise Setup |
tCSS |
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100 |
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ns |
CS to SCLK Rise Hold |
tCSH |
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0 |
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ns |
SCLK Pulse Width High |
tCH |
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200 |
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ns |
SCLK Pulse Width Low |
tCL |
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200 |
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ns |
SCLK Fall to SSTRB |
tSSTRB |
CLOAD = 100pF |
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200 |
ns |
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CS Fall to SSTRB Output Enable |
tSDV |
External clock mode only, CLOAD = 100pF |
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200 |
ns |
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(Note 6) |
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CS Rise to SSTRB Output Disable |
tSTR |
External clock mode only, CLOAD = 100pF |
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200 |
ns |
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(Note 6) |
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SSTRB Rise to SCLK Rise |
tSCK |
Internal clock mode only |
0 |
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ns |
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(Note 6) |
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MAX186/MAX188
_______________________________________________________________________________________ 5
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
__________________________________________Typical Operating Characteristics
|
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POWER-SUPPLY REJECTION |
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INTERNAL REFERENCE VOLTAGE |
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CHANNEL-TO-CHANNEL OFFSET MATCHING |
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vs. TEMPERATURE |
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vs. TEMPERATURE |
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vs. TEMPERATURE |
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0.30 |
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0.16 |
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0.25 |
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VDD = +5V ±5% |
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2.456 |
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0.14 |
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VSS = 0V or -5V |
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(LSBs) |
0.12 |
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0.20 |
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2.455 |
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(LSBs)PSR |
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(V)VREFADJ |
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MATCHINGOFFSET |
0.04 |
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0.15 |
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2.454 |
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0.10 |
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0.08 |
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0.10 |
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2.453 |
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0.06 |
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0.05 |
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0.00 |
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2.452 |
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0.02 |
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-0.05 |
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-40 -20 0 20 40 60 80 100 120 |
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-60 -40 -20 0 20 40 60 80 100 120 140 |
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-60 -40 -20 0 20 40 60 80 100 120 140 |
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TEMPERATURE (°C) |
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|
TEMPERATURE (°C) |
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TEMPERATURE (°C) |
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|
MAX186/MAX188 FFT PLOT – 133kHz |
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20 |
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0 |
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-20 |
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(dB) |
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ft = 10kHz |
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-40 |
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fs = 133kHz |
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AMPLITUDE |
-60 |
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TA = +25°C |
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-80 |
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-100 |
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-120 |
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-140 |
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0 |
33.25kHz |
66.5kHz |
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FREQUENCY |
|
|
_____________________________________________________________Pin Description
PIN |
NAME |
FUNCTION |
|
|
|
|
|
1-8 |
CH0-CH7 |
Sampling Analog Inputs |
|
|
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|
|
9 |
VSS |
Negative Supply Voltage. Tie to -5V ±5% or AGND |
|
|
|
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX186/MAX188 down to 10µA (max) |
|
10 |
SHDN |
supply current, otherwise the MAX186/MAX188 are fully operational. Pulling SHDN high puts the ref- |
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erence-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer |
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amplifier in external compensation mode. |
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Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier |
|
11 |
VREF |
(4.096V in the MAX186, 1.638 x REFADJ in the MAX188). Add a 4.7µF capacitor to ground when |
|
using external compensation mode. Also functions as an input when used with a precision external |
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reference. |
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|
6 ________________________________________________________________________________________________
Low-Power, 8-Channel,
Serial 12-Bit ADCs
________________________________________________Pin Description (continued)
PIN |
NAME |
FUNCTION |
|
|
|
|
|
12 |
REFADJ |
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to |
|
VDD. |
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13 |
AGND |
Analog Ground. Also INInput for single-ended conversions. |
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14 |
DGND |
Digital Ground |
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15 |
DOUT |
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high. |
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Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the |
|
16 |
SSTRB |
A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses |
|
|
|
high for one clock period before the MSB decision. High impedance when CS is high (external mode). |
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|
17 |
DIN |
Serial Data Input. Data is clocked in at the rising edge of SCLK. |
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|
18 |
CS |
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT |
|
is high impedance. |
|||
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||
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|
19 |
SCLK |
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets |
|
the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.) |
|||
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|
||
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|
20 |
VDD |
Positive Supply Voltage, +5V ±5% |
|
|
|
+5V |
|
|
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DOUT |
|
|
3k |
CS |
18 |
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DOUT |
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Figure 1. |
Load Circuits for Enable Time |
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Figure 2. Load Circuits for Disabled Time |
Figure 3. Block Diagram |
MAX186/MAX188
_______________________________________________________________________________________ 7
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
_______________Detailed Description
The MAX186/MAX188 use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to microprocessors. No external hold capacitors are required. Figure 3 shows the block diagram for the MAX186/MAX188.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog comparator is illustrated in the Equivalent Input Circuit (Figure 4). In single-ended mode, IN+ is internally switched to CH0-CH7 and INis switched to AGND. In differential mode, IN+ and INare selected from pairs of CH0/CH1, CH2/CH3, CH4/CH5 and CH6/CH7. Configure the channels with Table 3 and Table 4.
In differential mode, INand IN+ are internally switched to either one of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best results) with respect to AGND during a conversion. Accomplish this by connecting a 0.1µF capacitor from AIN- (the selected analog input, respectively) to AGND.
During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+.
The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, INis simply AGND. This unbalances node ZERO at the input of the comparator. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 12-bit resolution. This action is equivalent to transferring a charge of 16pF x
[(VIN+) - (VIN-)] from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Track/Hold
The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. The T/H enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for
12-BIT CAPACITIVE DAC |
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CH1 |
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16pF |
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CH2 |
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CH3 |
CSWITCH |
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TRACK |
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AT THE SAMPLING INSTANT, |
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T/H |
THE MUX INPUT SWITCHES |
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FROM THE SELECTED IN+ |
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IN– CHANNEL. |
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Figure 4. Equivalent Input Circuit
single-ended inputs, INis connected to AGND, and the converter samples the “+” input. If the converter is set up for differential inputs, INconnects to the “-” input, and the difference of |IN+ - IN-| is sampled. At the end of the conversion, the positive input connects back to IN+, and CHOLD charges to the input signal.
The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. Acquisition time is calculated by:
tAZ = 9 x (RS + RIN) x 16pF,
where RIN = 5kΩ , RS = the source impedance of the input signal, and tAZ is never less than 1.5µs. Note that source impedances below 5kΩ do not significantly affect the AC performance of the ADC. Higher source impedances can be used if an input capacitor is connected to the analog inputs, as shown in Figure 5. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC’s signal bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 4.5MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
8 _______________________________________________________________________________________