Maxim MAX1294BEEI, MAX1294BCEI, MAX1294AEEI, MAX1294ACEI, MAX1296BEEG Datasheet

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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

General Description

The MAX1294/MAX1296 low-power, 12-bit analog-to- digital converters (ADCs) feature a successive-approxi- mation ADC, automatic power-down, fast wake-up (2µs), on-chip clock, +2.5V internal reference, and high-speed 12-bit parallel interface. They operate with a single +5V analog supply.

Power consumption is only 10mW at the maximum sampling rate of 420ksps. Two software-selectable powerdown modes enable the MAX1294/MAX1296 to be shut down between conversions; accessing the parallel interface returns them to normal operation. Powering down between conversions can reduce supply below 10µA at lower sampling rates.

Both devices offer software-configurable analog inputs for unipolar/bipolar and single-ended/pseudo-differential operation. In single-ended mode, the MAX1294 has six input channels and the MAX1296 has two (three input channels and one input channel, respectively, when in pseudo-differential mode).

Excellent dynamic performance and low power combined with ease of use and small package size make these converters ideal for battery-powered and data-acquisition applications or for other circuits with demanding powerconsumption and space requirements. The MAX1294 is offered in a 28-pin QSOP package, while the MAX1296 is available in a 24-pin QSOP. For pin-compatible +3V, 12-bit versions, see the MAX1295/MAX1297.

		Applications
Industrial Control Systems	Data Logging
Energy Management	Patient Monitoring
Data-Acquisition Systems	Touchscreens

Ordering Information

	PART	TEMP. RANGE	PIN-PACKAGE	INL
				(LSB)
	MAX1294ACEI	0°C to +70°C	28 QSOP	±0.5
	MAX1294BCEI	0°C to +70°C	28 QSOP	±1
	MAX1294AEEI	-40°C to +85°C	28 QSOP	±0.5
	MAX1294BEEI	-40°C to +85°C	28 QSOP	±1
	MAX1296ACEG	0°C to +70°C	24 QSOP	±0.5
	MAX1296BCEG	0°C to +70°C	24 QSOP	±1
	MAX1296AEEG	-40°C to +85°C	24 QSOP	±0.5
	MAX1296BEEG	-40°C to +85°C	24 QSOP	±1

Features

♦12-Bit Resolution, ±0.5LSB Linearity

♦Single +5V Operation

♦Internal +2.5V Reference

♦Software-Configurable Analog Input Multiplexer 6-Channel Single-Ended/

3-Channel Pseudo-Differential (MAX1294)

2-Channel Single-Ended/

1-Channel Pseudo-Differential (MAX1296)

♦Software-Configurable Unipolar/Bipolar Analog Inputs

♦Low Current

2.0mA (420ksps) 1.0mA (100ksps) 400µA (10ksps)

2µA (shutdown)

♦Internal 6MHz Full-Power Bandwidth Track/Hold

♦Parallel 12-Bit Interface

♦Small Footprint

28-Pin QSOP (MAX1294)

24-Pin QSOP (MAX1296)

Pin Configurations

TOP VIEW

	D9		1					24		D10
	D8		2					23		D11
	D7		3					22		VDD
	D6		4					21		REF
	D5		5					20		REFADJ
				MAX1296
	D4		6					19		GND
	D3		7					18		COM
	D2		8					17		CH0
	D1		9					16		CH1
	D0		10					15		CS
	INT		11					14		CLK
	RD		12					13		WR

QSOP

Pin Configurations continued at end of data sheet.

Typical Operating Circuits appear at end of data sheet.

________________________________________________________________ Maxim Integrated Products 1

MAX1294/MAX1296

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone]. For small orders, phone [phone].

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

ABSOLUTE MAXIMUM RATINGS

VDD to GND ..............................................................		-0.3V to +6V	Operating Temperature Ranges
CH0–CH5, COM to GND ............................	-0.3V to (VDD + 0.3V)		MAX1294_C_ _/MAX1296_C_ _.........................	0°C to +70°C
REF, REFADJ to GND.................................	-0.3V to (VDD + 0.3V)		MAX1294_E_ _/MAX1296_E_ _ ......................	-40°C to +85°C
Digital Inputs to GND ...............................................		-0.3V to +6V	Storage Temperature Range .............................	-65°C to +150°C
Digital Outputs (D0–D11, INT) to GND.......	-0.3V to (VDD + 0.3V)		Lead Temperature (soldering, 10sec) .............................	+300°C
Continuous Power Dissipation (TA = +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C)..........		762mW
28-Pin QSOP (derate 8.00mW/°C above +70°C)........		667mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(VDD = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER		SYMBOL	CONDITIONS		MIN	TYP	MAX	UNITS
DC ACCURACY (Note 1)
Resolution		RES			12			Bits
Relative Accuracy (Note 2)		INL	MAX129_A				±0.5	LSB
			MAX129_B				±1
Differential Nonlinearity		DNL	No missing codes over temperature				±1	LSB
Offset Error							±4	LSB
Gain Error (Note 3)							±4	LSB
Gain Temperature Coefficient						±2.0		ppm/°C
Channel-to-Channel Offset						±0.2		LSB
Matching
DYNAMIC SPECIFICATIONS (f		IN(sine wave) = 50kHz, VIN = 2.5Vp-p, 420ksps, external fCLK =			7.6MHz, bipolar input mode)
Signal-to-Noise Plus Distortion		SINAD			67	70		dB
Total Harmonic Distortion		THD					-80	dB
(including 5th-order harmonic)
Spurious-Free Dynamic Range		SFDR			-80			dB
Intermodulation Distortion		IMD	fIN1 = 49kHz, fIN2 = 52kHz			76		dB
Channel-to-Channel Crosstalk			fIN = 175kHz (Note 4)			-78		dB
Full-Linear Bandwidth			SINAD > 68dB			350		kHz
Full-Power Bandwidth			-3dB rolloff			6		MHz
CONVERSION RATE
			External clock mode		2.1
Conversion Time (Note 5)		tCONV	External acquisition/internal clock mode		2.5	3.0	3.5	µs
			Internal acquisition/internal clock mode		3.2	3.6	4
T/H Acquisition Time		tACQ					400	ns
Aperture Delay			External acquisition or external clock mode			25		ns
Aperture Jitter			External acquisition or external clock mode			<50		ps
			Internal acquisition/internal clock mode			<200
External Clock Frequency		fCLK			0.1		7.6	MHz
Duty Cycle				30			70	%

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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER		SYMBOL	CONDITIONS				MIN	TYP	MAX	UNITS
ANALOG INPUTS
Analog Input Voltage Range			Unipolar, VCOM = 0				0		VREF
Single-Ended and Differential		VIN	Bipolar, VCOM = VREF/2				-VREF/2		+VREF/2	V
(Note 6)
Multiplexer Leakage Current			On/off-leakage current, VIN = 0 or VDD					±0.01	±1	µA
Input Capacitance		CIN						12		pF
INTERNAL REFERENCE
REF Output Voltage							2.49	2.5	2.51	V
REF Short-Circuit Current								15		mA
REF Temperature Coefficient		TCREF						±20		ppm/°C
REFADJ Input Range			For small adjustments					±100		mV
REFADJ High Threshold			To power down the internal reference				VDD - 1			V
Load Regulation (Note 7)			0 to 0.5mA output load					0.2	0.5	mV/mA
Capacitive Bypass at REFADJ								0.01	1	µF
Capacitive Bypass at REF							4.7		10	µF
EXTERNAL REFERENCE AT REF
REF Input Voltage Range		VREF					1.0		VDD +	V
									50mV
REF Input Current		IREF	VREF = 2.5V, fSAMPLE = 420ksps					200	300	µA
			Shutdown mode						2	µA
DIGITAL INPUTS AND OUTPUTS
Input Voltage High		VIH					4.0			V
Input Voltage Low		VIL							0.8	V
Input Hysteresis		VHYS						200		mV
Input Leakage Current		IIN	VIN = 0 or VDD					±0.1	±1	µA
Input Capacitance		CIN						15		pF
Output Voltage Low		VOL	ISINK = 1.6mA						0.4	V
Output Voltage High		VOH	ISOURCE = 1mA				VDD - 0.5			V
Three-State Leakage Current		ILEAKAGE	CS = VDD					±0.1	±1	µA
Three-State Output Capacitance		COUT	CS = VDD					15		pF
POWER REQUIREMENTS
Analog Supply Voltage		VDD					4.5		5.5	V
			Operating mode,			Internal reference		2.6	2.9
			fSAMPLE = 420ksps
		IDD				External reference		2.2	2.5	mA
Positive Supply Current						Internal reference		1.0	1.2
		IDD	Standby mode
						External reference		0.5	0.8
			Shutdown mode					2	10	µA
Power-Supply Rejection		PSR	VDD = 5V ±10%, full-scale input					±0.3	±0.7	mV

MAX1294/MAX1296

_______________________________________________________________________________________ 3

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

TIMING CHARACTERISTICS

(VDD = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER		SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
CLK Period		tCP		132			ns
CLK Pulse Width High		tCH		40			ns
CLK Pulse Width Low		tCL		40			ns
Data Valid to WR Rise Time		tDS		40			ns
WR Rise to Data Valid Hold Time		tDH		0			ns
WR to CLK Fall Setup Time		tCWS		60			ns
CLK Fall to WR Hold Time		tCWH		40			ns
CS to CLK or WR Setup Time		tCSWS		40			ns
CLK or WR to CS Hold Time		tCSWH		0			ns
CS Pulse Width		tCS		100			ns
WR Pulse Width (Note 8)		tWR		60			ns
CS Rise to Output Disable		tTC	CLOAD = 20pF, Figure 1	10		60	ns
				10		40
RD Rise to Output Disable		tTR	CLOAD = 20pF, Figure 1				ns
RD Fall to Output Data Valid		tDO	CLOAD = 20pF, Figure 1	10		50	ns
RD Fall to INT High Delay		tINT1	CLOAD = 20pF, Figure 1			50	ns
CS Fall to Output Data Valid		tDO2	CLOAD = 20pF, Figure 1			100	ns

Note 1: Tested at VDD = +5V, COM = GND, unipolar single-ended input mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed.

Note 3: Offset nulled.

Note 4: On channel is grounded; sine wave applied to off channels.

Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle. Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD. Note 7: External load should not change during conversion for specified accuracy.

Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.

VDD

3k

DOUT

CLOAD

DOUT

3k

CLOAD

20pF

20pF

GND

GND

a) High-Z to VOH and VOL to VOH

b) High-Z to VOL and VOH to VOL

Figure 1. Load Circuits for Enable/Disable Times

4 _______________________________________________________________________________________

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

Typical Operating Characteristics

(VDD = +5V, VREF = +2.500V, fCLK = 7.6MHz, CL = 20pF, TA = +25°C, unless otherwise noted.)

			INTEGRAL NONLINEARITY vs.													DIFFERENTIAL NONLINEARITY vs.											SUPPLY CURRENT vs. SAMPLE FREQUENCY
	0.5			DIGITAL OUTPUT CODE										0.5			DIGITAL OUTPUT CODE
												MAX1294/6-01													MAX1294/6-02		10,000																								MAX1294/6-02A
	0.3													0.3																							WITH				INTERNAL			REFERENCE
	0.4													0.4													1000
	0.2													0.2
(LSB)	0.1												(LSB)	0.1												(μA)
	0													0													100
INL													DNL													I
																										DD
	-0.1													-0.1
	-0.2													-0.2													10
	-0.3													-0.3
	-0.4													-0.4																											WITH		EXTERNAL			REFERENCE
	-0.5													-0.5													0
																																											1k
	0		1000		2000		3000		4000		5000			0		1000		2000		3000		4000		5000			0.1			1					10				100						10k		100k			1M
					DIGITAL OUTPUT CODE													DIGITAL OUTPUT CODE																						fSAMPLE (Hz)

	SUPPLY CURRENT vs. SUPPLY VOLTAGE																				SUPPLY CURRENT vs. TEMPERATURE																STANDBY CURRENT vs. SUPPLY VOLTAGE
	2.2																toc03		2.3																toc04		990															toc05
			RL = ∞																		RL = ∞
			CODE = 101010100000														MAX1294/6				CODE = 101010100000														MAX1294/6		980															MAX1294/6
	2.1																		2.2																	A)(μ
(mA)																		(mA)	2.1																		970
																																				I
																																				DD
I	2.0																	I	2.0																	STANDBY	960
DD																		DD
	1.9																		1.9																		950
																			1.8																		940
	1.8																		1.7																		930
	4.50			4.75			5.00						5.25			5.50				-40		-15			10		35				60			85			4.50			4.75			5.00					5.25			5.50
								VDD (V)																TEMPERATURE (°C)																				VDD (V)
																						POWER-DOWN CURRENT																		POWER-DOWN CURRENT
	STANDBY CURRENT vs. TEMPERATURE																						vs. SUPPLY VOLTAGE																			vs. TEMPERATURE
	990																toc06		3.0																toc07		2.2															toc08
	980																MAX1294/6	(μA)	2.5																MAX1290/2	(μA)	2.1															MAX1294/6
(μA)	970
																		DD																		DD
DD																		I																		I
STANDBYI	960																	DOWN-POWER	2.0																	DOWN-POWER	2.0
	950																		1.5																		1.9
	940
																			1.0
	930																																				1.8
																				4.50		4.75					5.00				5.25			5.50
	-40			-15			10				35		60			85																					-40			-15			10			35		60			85
						TEMPERATURE (°C)																					VDD (V)																TEMPERATURE (°C)

MAX1294/MAX1296

_______________________________________________________________________________________ 5

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

Typical Operating Characteristics (continued)

(VDD = +5V, VREF = +2.500V, fCLK = 7.6MHz, CL = 20pF, TA = +25°C, unless otherwise noted.)

			INTERNAL REFERENCE VOLTAGE												REFERENCE VOLTAGE
			vs. SUPPLY VOLTAGE													vs. TEMPERATURE										OFFSET ERROR vs. SUPPLY VOLTAGE
	2.53									MAX1294/6-09		2.53											MAX1294/6-10		1.0									MAX1294/6 toc11
	2.52											2.52
																								(LSB)	0.5
	2.51											2.51
REF											REF													ERROR	0
(V)											(V)
V	2.50										V	2.50												OFFSET
																									-0.5
	2.49											2.49
	2.48											2.48													-1.0
	4.50		4.75		5.00		5.25		5.50			-40		-15		10		35		60		85			4.50		4.75		5.00		5.25		5.50
					VDD (V)											TEMPERATURE (°C)													VDD (V)

		OFFSET ERROR vs. TEMPERATURE													GAIN ERROR vs. SUPPLY VOLTAGE																		GAIN ERROR vs. TEMPERATURE
2											MAX1294/6 toc12	2																		MAX1294/6 toc13	2.0											MAX1294/6 toc14
1												1																			1.5
											GAIN ERROR (LSB)
0												0																			1.0
OFFSETERROR(LSB)																															ERRORGAIN(LSB)
-1												-1																			0.5
-2												-2																			0
-40		-15		10		35		60		85		4.50			4.75					5.00				5.25				5.50			-40		-15		10		35		60		85
				TEMPERATURE (°C)															VDD (V)																TEMPERATURE (°C)
																		FFT PLOT
												20
																														15
																						VDD = 5V								-
																														MAX1294/6
												0										fIN		= 50kHz
																						fSAMPLE = 400ksps
												-20
											(dB)
												-40
											AMPLITUDE	-60
												-80
												-100
												-120
												-140
												0			200			400		600				800			1000

FREQUENCY (kHz)

6 _______________________________________________________________________________________