KIT EVALUATION
AVAILABLE
Channel,
Serial 12-Bit ADCs in QSOP-16
Description
data-acquisition systems high-bandwidth with high conversion
. The MAX1246 oper-
.6V supply; the MAX1247 to +5.25V supply. Both configurable for
operation.
directly to SPI™/ without external logic. A connection to TMS320The MAX1246/MAX1247 external serial-interface analog-to-
2.5V reference, while the
. Both parts have with a ±1.5% voltage-
____________________________Features
♦4-Channel Single-Ended or 2-Channel Differential Inputs
♦Single-Supply Operation:
+2.7V to +3.6V (MAX1246)
+2.7V to +5.25V (MAX1247)
♦Internal 2.5V Reference (MAX1246)
♦Low Power: 1.2mA (133ksps, 3V supply)
54µA (1ksps, 3V supply) 1µA (power-down mode)
♦SPI/QSPI/Microwire/TMS320-Compatible 4-Wire Serial Interface
♦Software-Configurable Unipolar or Bipolar Inputs
♦16-Pin QSOP Package (same area as 8-pin SO)
-wired SHDN pin and a and can be prodown at the end of a coninterface automatically and the quick turn-on between all conversupply current to under
60µA at reduced sampling rates.
The MAX1246/MAX1247 are available in a 16-pin DIP and a small QSOP that occupies the same board area as an 8-pin SO.
For 8-channel versions of these devices, see the MAX146/MAX147 data sheet.
________________________Applications
Portable Data Logging |
Data Acquisition |
Medical Instruments |
Battery-Powered Instruments |
Pen Digitizers |
Process Control |
Pin Configuration appears at end of data sheet.
______________Ordering Information
PART† |
TEMP. RANGE |
PIN-PACKAGE |
INL |
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(LSB) |
MAX1246ACPE |
0°C to +70°C |
16 Plastic DIP |
±1/2 |
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MAX1246BCPE |
0°C to +70°C |
16 Plastic DIP |
±1 |
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MAX1246ACEE |
0°C to +70°C |
16 QSOP |
±1/2 |
MAX1246BCEE |
0°C to +70°C |
16 QSOP |
±1 |
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Ordering Information continued at end of data sheet.
†Contact factory for availability of alternate surface-mount packages.
__________Typical Operating Circuit
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+3V |
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CH0 |
VDD |
VDD |
0V TO |
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DGND |
0.1μF |
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+2.5V |
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ANALOG |
MAX1246 AGND |
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INPUTS |
CPU |
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CH3 |
COM |
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4.7μF |
VREF |
CS |
I/O |
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SCLK |
SCK (SK) |
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DIN |
MOSI (SO) |
0.047μF |
REFADJ |
DOUT |
MISO (SI) |
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SSTRB |
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VSS |
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SHDN |
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SPI and QSPI are registered trademarks of Motorola, Inc. Microwire is a registered trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX1246/MAX1247
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND................................................. |
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- 0.3V to 6V |
AGND to DGND ...................................................... |
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- 0.3V to 0.3V |
CH0–CH3, COM to AGND, DGND ............ |
-0.3V to (VDD + 0.3V) |
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VREF to AGND........................................... |
-0.3V to (VDD + 0.3V) |
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Digital Inputs to DGND .............................................. |
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- 0.3V to 6V |
Digital Outputs to DGND ........................... |
-0.3V to (VDD + 0.3V) |
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Digital Output Sink Current ................................................. |
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25mA |
Continuous Power Dissipation (TA = +70°C) |
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Plastic DIP (derate 10.53mW/°C above +70°C) |
......... 842mW |
QSOP (derate 8.36mW/°C above +70°C)................... |
667mW |
CERDIP (derate 10.00mW/°C above +70°C).............. |
800mW |
Operating Temperature Ranges |
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MAX1246_C_E/MAX1247_C_E .......................... |
0°C to +70°C |
MAX1246_E_E/MAX1247_E_E........................ |
-40°C to +85°C |
MAX1246_MJE/MAX1247_MJE .................... |
-55°C to +125°C |
Storage Temperature Range ............................ |
-60°C to +150°C |
Lead Temperature (soldering, 10sec) ............................ |
+300°C |
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX1246); VDD = +2.7V to +5.25V (MAX1247); COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX; unless otherwise noted.)
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PARAMETER |
SYMBOL |
CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
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DC ACCURACY (Note 1) |
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Resolution |
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12 |
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Bits |
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Relative Accuracy (Note 2) |
INL |
MAX124_A |
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±0.5 |
LSB |
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MAX124_B |
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±1.0 |
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Differential Nonlinearity |
DNL |
No missing codes over temperature |
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±1 |
LSB |
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Offset Error |
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MAX124_A |
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±0.5 |
±3 |
LSB |
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MAX124_B |
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±0.5 |
±4 |
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Gain Error (Note 3) |
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±0.5 |
±4 |
LSB |
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Gain Temperature Coefficient |
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±0.25 |
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ppm/°C |
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Channel-to-Channel Offset |
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±0.25 |
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LSB |
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Matching |
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DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)
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Signal-to-Noise + Distortion Ratio |
SINAD |
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70 |
73 |
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dB |
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Total Harmonic Distortion |
THD |
Up to the 5th harmonic |
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-88 |
-80 |
dB |
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Spurious-Free Dynamic Range |
SFDR |
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80 |
90 |
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dB |
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Channel-to-Channel Crosstalk |
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65kHz, 2.500Vp-p (Note 4) |
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-85 |
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dB |
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Small-Signal Bandwidth |
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-3dB rolloff |
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2.25 |
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MHz |
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Full-Power Bandwidth |
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1.0 |
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MHz |
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CONVERSION RATE |
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Internal clock, SHDN = FLOAT |
5.5 |
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7.5 |
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Conversion Time (Note 5) |
tCONV |
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µs |
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Internal clock, SHDN = VDD |
35 |
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65 |
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External clock = 2MHz, 12 clocks/conversion |
6 |
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Track/Hold Acquisition Time |
tACQ |
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1.5 |
µs |
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Aperture Delay |
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30 |
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ns |
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Aperture Jitter |
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<50 |
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ps |
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Internal Clock Frequency |
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SHDN = FLOAT |
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1.8 |
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MHz |
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SHDN = VDD |
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0.225 |
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External Clock Frequency |
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0.1 |
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2.0 |
MHz |
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Data transfer only |
0 |
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2.0 |
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2 _______________________________________________________________________________________
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX1246); VDD = +2.7V to +5.25V (MAX1247); COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER |
SYMBOL |
CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
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ANALOG/COM INPUTS |
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Input Voltage Range, Single- |
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Unipolar, COM = 0V |
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0 to VREF |
V |
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Ended and Differential (Note 6) |
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Bipolar, COM = VREF / 2 |
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±VREF / 2 |
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Multiplexer Leakage Current |
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On/off leakage current, VCH_ = 0V or VDD |
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±0.01 |
±1 |
µA |
Input Capacitance |
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16 |
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pF |
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INTERNAL REFERENCE (MAX1246 only, reference buffer enabled) |
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VREF Output Voltage |
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TA = +25°C |
2.480 |
2.500 |
2.520 |
V |
VREF Short-Circuit Current |
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30 |
mA |
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MAX1246_C |
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±30 |
±50 |
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VREF Temperature Coefficient |
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MAX1246_E |
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±30 |
±60 |
ppm/°C |
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MAX1246_M |
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±30 |
±80 |
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Load Regulation (Note 8) |
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0mA to 0.2mA output load |
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±0.35 |
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mV |
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Capacitive Bypass at VREF |
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Internal compensation mode |
0 |
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µF |
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External compensation mode |
4.7 |
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Capacitive Bypass at REFADJ |
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0.047 |
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µF |
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REFADJ Adjustment Range |
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±1.5 |
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% |
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EXTERNAL REFERENCE AT VREF (Buffer |
disabled) |
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VREF Input Voltage Range |
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1.0 |
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VDD + |
V |
(Note 9) |
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50mV |
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VREF Input Current |
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VREF = 2.500V |
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100 |
150 |
µA |
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VREF Input Resistance |
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18 |
25 |
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kΩ |
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Shutdown VREF Input Current |
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0.01 |
10 |
µA |
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REFADJ Buffer Disable Threshold |
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VDD - |
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V |
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0.5 |
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EXTERNAL REFERENCE AT REFADJ |
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Capacitive Bypass at VREF |
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Internal compensation mode |
0 |
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µF |
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External compensation mode |
4.7 |
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Reference Buffer Gain |
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MAX1246 |
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2.06 |
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V/V |
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MAX1247 |
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2.00 |
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REFADJ Input Current |
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MAX1246 |
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±50 |
µA |
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MAX1247 |
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±10 |
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MAX1246/MAX1247
_______________________________________________________________________________________ 3
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX1246); VDD = +2.7V to +5.25V (MAX1247); COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER |
SYMBOL |
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CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
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DIGITAL INPUTS (DIN, SCLK, |
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CS, |
SHDN) |
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DIN, SCLK, CS Input High Voltage |
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VIH |
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VDD ≤ 3.6V |
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2.0 |
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V |
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VDD > 3.6V, MAX1247 only |
3.0 |
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DIN, SCLK, CS Input Low Voltage |
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VIL |
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0.8 |
V |
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DIN, SCLK, CS Input Hysteresis |
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VHYST |
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0.2 |
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V |
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DIN, SCLK, CS Input Leakage |
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IIN |
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VIN = 0V or VDD |
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±0.01 |
±1 |
µA |
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DIN, SCLK, CS Input Capacitance |
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CIN |
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(Note 7) |
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15 |
pF |
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SHDN Input High Voltage |
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VSH |
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VDD - 0.4 |
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V |
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SHDN Input Mid Voltage |
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VSM |
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1.1 |
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VDD - 1.1 |
V |
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SHDN Input Low Voltage |
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VSL |
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0.4 |
V |
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SHDN Input Current |
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IS |
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= 0V or VDD |
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±4.0 |
µA |
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SHDN |
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SHDN Voltage, Floating |
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VFLT |
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SHDN |
= FLOAT |
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VDD / 2 |
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V |
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SHDN Maximum Allowed |
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SHDN = FLOAT |
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±100 |
nA |
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Leakage, Mid Input |
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DIGITAL OUTPUTS (DOUT, SSTRB) |
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Output Voltage Low |
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VOL |
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ISINK = 5mA |
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0.4 |
V |
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ISINK = 16mA |
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0.8 |
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Output Voltage High |
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VOH |
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ISOURCE = 0.5mA |
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VDD - 0.5 |
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V |
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Three-State Leakage Current |
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IL |
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CS = VDD |
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±0.01 |
±10 |
µA |
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Three-State Output Capacitance |
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COUT |
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CS = VDD (Note 7) |
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15 |
pF |
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POWER REQUIREMENTS |
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Positive Supply Voltage |
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VDD |
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MAX1246 |
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2.70 |
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3.60 |
V |
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MAX1247 |
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2.70 |
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5.25 |
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Operating mode, full-scale input |
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1.2 |
2.0 |
mA |
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Positive Supply Current, MAX1246 |
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IDD |
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VDD = 3.6V |
Fast power-down |
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30 |
70 |
µA |
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Full power-down |
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1.2 |
10 |
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Operating mode, |
VDD = 5.25V |
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1.8 |
2.5 |
mA |
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full-scale input |
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VDD = 3.6V |
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0.9 |
1.5 |
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Positive Supply Current, MAX1247 |
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IDD |
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Fast power-down |
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30 |
70 |
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Full power-down |
VDD = 5.25V |
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3.5 |
15 |
µA |
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VDD = 3.6V |
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1.2 |
10 |
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Supply Rejection (Note 10) |
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PSR |
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VDD = 2.7V to VDD(MAX), full-scale input, |
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±0.3 |
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mV |
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external reference = 2.500V |
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4 _______________________________________________________________________________________
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX1246); VDD = +2.7V to +5.25V (MAX1247); TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER |
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SYMBOL |
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CONDITIONS |
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MIN |
TYP |
MAX |
UNITS |
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Acquisition Time |
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tACQ |
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1.5 |
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µs |
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DIN to SCLK Setup |
tDS |
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100 |
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ns |
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DIN to SCLK Hold |
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tDH |
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0 |
ns |
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SCLK Fall to Output Data Valid |
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tDO |
Figure 1 |
MAX124_ _C/E |
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20 |
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200 |
ns |
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MAX124Figure _ _M |
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20 |
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240 |
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CS Fall to Output Enable |
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tDV |
Figure 1 |
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240 |
ns |
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CS Rise to Output Disable |
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tTR |
Figure 2 |
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240 |
ns |
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CS to SCLK Rise Setup |
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tCSS |
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100 |
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ns |
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CS to SCLK Rise Hold |
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tCSH |
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0 |
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ns |
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SCLK Pulse Width High |
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tCH |
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200 |
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ns |
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SCLK Pulse Width Low |
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tCL |
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200 |
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ns |
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SCLK Fall to SSTRB |
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tSSTRB |
Figure 1 |
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240 |
ns |
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CS Fall to SSTRB Output Enable |
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tSDV |
External clock mode only, Figure 1 |
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240 |
ns |
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CS Rise to SSTRB Output Disable |
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tSTR |
External clock mode only, Figure 2 |
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240 |
ns |
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SSTRB Rise to SCLK Rise |
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tSCK |
Internal clock mode only (Note 7) |
0 |
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ns |
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Note 1: Tested at VDD = 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated.
Note 3: MAX1246—internal reference, offset nulled; MAX1247—external reference (VREF = +2.500V), offset nulled. Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Guaranteed by design. Not subject to production testing.
Note 8: External load should not change during conversion for specified accuracy. Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p. Note 10: Measured as |VFS(2.7V) - VFS(VDD, MAX)|.
__________________________________________Typical Operating Characteristics
(VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY |
INTEGRAL NONLINEARITY |
INTEGRAL NONLINEARITY |
vs. CODE |
vs. SUPPLY VOLTAGE |
vs. TEMPERATURE |
|
0.5 |
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MAX1247-01 |
|
0.50 |
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MAX1247-02 |
|
0.50 |
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VDD = 2.7V |
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MAX1247-03 |
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0.4 |
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0.45 |
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0.45 |
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0.3 |
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0.40 |
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MAX1246 |
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0.40 |
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0.2 |
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0.35 |
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0.35 |
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(LSB) |
0.1 |
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(LSB) |
0.30 |
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(LSB) |
0.30 |
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MAX1246 |
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0 |
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0.25 |
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0.25 |
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INL |
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INL |
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INL |
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-0.1 |
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0.20 |
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0.20 |
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MAX1247 |
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MAX1247 |
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-0.2 |
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0.15 |
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0.15 |
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-0.3 |
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0.10 |
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0.10 |
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-0.4 |
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0.05 |
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0.05 |
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-0.5 |
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0.00 |
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0.00 |
-60 |
-20 |
20 |
60 |
100 |
140 |
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0 |
1024 |
2048 |
3072 |
4096 |
|
2.25 |
2.75 |
3.25 |
3.75 |
4.25 |
4.75 |
5.25 |
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||||||
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CODE |
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VDD (V) |
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TEMPERATURE (°C) |
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_______________________________________________________________________________________ |
5 |
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
MAX1246/MAX1247 |
____________________________Typical Operating Characteristics (continued) |
|||||||||||||||||||||
(VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.) |
|
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|||||||||||||||||
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SUPPLY CURRENT |
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SHUTDOWN SUPPLY CURRENT |
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|
INTERNAL REFERENCE VOLTAGE |
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|||||||||
|
2.00 |
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vs. SUPPLY VOLTAGE |
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4.0 |
vs. SUPPLY VOLTAGE |
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vs. SUPPLY VOLTAGE |
|
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|||||||
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RL = ∞ |
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04 |
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05 |
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2.5020 |
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5.25MAX1247-06 |
||||
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- |
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FULL POWER-DOWN |
- |
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||||||
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CLOAD = 50pF |
MAX1247 |
|
3.5 |
|
MAX1247 |
|
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||||||||
|
1.75 |
CODE = 101010100000 |
SHUTDOWN SUPPLY CURRENT (μA) |
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2.5015 |
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SUPPLY CURRENT (mA) |
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3.0 |
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1.50 |
MAX1246 |
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2.5 |
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2.5010 |
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VREF (V) |
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1.25 |
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2.0 |
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2.5005 |
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1.00 |
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1.5 |
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2.5000 |
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CLOAD |
= 20pF |
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1.0 |
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0.75 |
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MAX1247 |
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0.5 |
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2.4995 |
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0.50 |
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0 |
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2.4990 |
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2.25 |
2.75 3.25 |
3.75 |
4.25 |
4.75 |
5.25 |
2.25 |
2.75 3.25 |
3.75 |
4.25 |
4.75 |
5.25 |
2.25 |
2.75 3.25 |
3.75 |
4.25 |
4.75 |
SUPPLY VOLTAGE (V) |
VDD (V) |
VDD (V) |
SUPPLY CURRENT (mA)
SUPPLY CURRENT vs. TEMPERATURE
1.3 |
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07 |
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MAX1247- |
1.2 |
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MAX1246 |
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1.1
1.0
MAX1247
0.9
RLOAD = ∞
CODE = 101010100000
0.8
-60 |
-20 |
20 |
60 |
100 |
140 |
|
|
TEMPERATURE (°C) |
|
|
SHUTDOWN CURRENT (μA)
SHUTDOWN CURRENT vs. TEMPERATURE
2.0
MAX1247-08
1.6
1.2
0.8
0.4
0
-60 |
-20 |
20 |
60 |
100 |
140 |
TEMPERATURE (°C)
VREF (V)
2.501
2.500
2.499
2.498
2.497
2.496
2.495
2.494
-60
MAX1246
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1247-09
VDD = 3.6V
VDD = 2.7V
-20 |
20 |
60 |
100 |
140 |
|
TEMPERATURE (°C) |
|
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AMPLITUDE (dB)
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FFT PLOT |
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20 |
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-10 |
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VDD = 2.7V |
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MAX1247 |
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0 |
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fIN = 10k |
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fSAMPLE = 133k |
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-20 |
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-40 |
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-60 |
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-80 |
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-100 |
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-120 |
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0 |
10 |
20 |
30 |
40 |
50 |
60 |
70 |
|||||||||
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FREQUENCY (kHz) |
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|
EFFECTIVE NUMBER OF BITS
EFFECTIVE NUMBER OF BITS vs. FREQUENCY
12.0 |
|
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-11 |
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||
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|
VDD = 2.7V |
|
MAX1247 |
11.8
11.6
11.4
11.2
11.0
1 |
10 |
100 |
FREQUENCY (kHz)
6 _______________________________________________________________________________________
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
____________________________Typical Operating Characteristics (continued)
(VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
|
GAIN ERROR |
CHANNEL-TO-CHANNEL GAIN MATCHING |
OFFSET vs. SUPPLY VOLTAGE |
vs. SUPPLY VOLTAGE |
vs. SUPPLY VOLTAGE |
OFFSET (LSB)
0.50 |
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-12 |
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0.45 |
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MAX1247 |
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0.40 |
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0.35 |
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0.30 |
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0.25 |
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0.20 |
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0.15 |
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0.10 |
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0.05 |
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0 |
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2.25 |
2.75 |
3.25 |
3.75 |
4.25 |
4.75 |
5.25 |
GAIN ERROR (LSB)
0.50 |
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-13 |
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0.45 |
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MAX1247 |
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0.40 |
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0.35 |
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0.30 |
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0.25 |
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0.20 |
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0.15 |
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0.10 |
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0.05 |
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2.75 |
3.25 |
3.75 |
4.25 |
4.75 |
5.25 |
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-14 |
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MAX1247 |
(LSB) |
0.40 |
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MATCHING |
0.30 |
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0.20 |
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GAIN |
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0.15 |
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0.10 |
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2.25 |
2.75 |
3.25 |
3.75 |
4.25 |
4.75 |
5.25 |
VDD (V) VDD (V) VDD (V)
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GAIN ERROR |
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MAX1247-15 |
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MAX1247-16 |
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MAX1247-17 |
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0.45 |
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0.45 |
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0.45 |
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(LSB)OFFSET |
0.40 |
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(LSB)ERRORGAIN |
0.40 |
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(LSB)MATCHINGGAIN |
0.40 |
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0.35 |
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0.35 |
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0.30 |
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0.30 |
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0.30 |
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0.25 |
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0.25 |
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0.25 |
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0.20 |
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0.20 |
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0.20 |
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0.15 |
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0.15 |
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0.15 |
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0.10 |
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0.10 |
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0.10 |
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0.05 |
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0.05 |
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0.05 |
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0 |
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0 |
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-55 -30 -5 20 45 70 95 120 |
145 |
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-55 -30 -5 20 45 70 95 |
120 145 |
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-55 -30 -5 20 45 70 95 |
120 145 |
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TEMPERATURE (˚C) |
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TEMPERATURE (˚C) |
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TEMPERATURE (˚C) |
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CHANNEL-TO-CHANNEL OFFSET MATCHING vs. SUPPLY VOLTAGE
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0.50 |
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-18 |
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0.45 |
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MAX1247 |
(LSB) |
0.40 |
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0.35 |
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MATCHING |
0.30 |
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0.25 |
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0.20 |
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OFFSET |
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0.15 |
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0.10 |
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0.05 |
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0 |
2.75 |
3.25 |
3.75 |
4.25 |
4.75 |
5.25 |
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2.25 |
VDD (V)
CHANNEL-TO-CHANNEL OFFSET MATCHING vs. TEMPERATURE
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0.50 |
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-19 |
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0.45 |
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MAX1247 |
(LSB) |
0.40 |
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0.35 |
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MATCHING |
0.30 |
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0.25 |
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0.20 |
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OFFSET |
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0.15 |
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0.10 |
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0.05 |
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0 |
-30 |
-5 |
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-55 |
20 |
45 |
70 |
95 |
120 |
145 |
TEMPERATURE (˚C)
MAX1246/MAX1247
_______________________________________________________________________________________ 7
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
______________________________________________________________Pin Description
PIN |
NAME |
FUNCTION |
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1 |
VDD |
Positive Supply Voltage |
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2–5 |
CH0–CH3 |
Sampling Analog Inputs |
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6 |
COM |
Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be |
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stable to ±0.5LSB. |
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Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1246/MAX1247 down; otherwise, they |
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7 |
SHDN |
are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation |
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mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode. |
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Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. |
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8 |
VREF |
In internal reference mode (MAX1246 only), the reference buffer provides a 2.500V nominal output, |
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externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling |
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REFADJ to VDD. |
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9 |
REFADJ |
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD. |
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10 |
AGND |
Analog Ground |
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11 |
DGND |
Digital Ground |
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12 |
DOUT |
Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high. |
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Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1246/MAX1247 begin the |
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13 |
SSTRB |
A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses |
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high for one clock period before the MSB decision. High impedance when CS is high (external clock |
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mode). |
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14 |
DIN |
Serial Data Input. Data is clocked in at SCLK’s rising edge. |
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15 |
CS |
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is |
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high impedance. |
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16 |
SCLK |
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets |
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the conversion speed. (Duty cycle must be 40% to 60%.) |
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VDD |
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VDD |
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6k |
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6k |
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DOUT |
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DOUT |
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DOUT |
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DOUT |
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6k |
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CLOAD |
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CLOAD |
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6k |
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CLOAD |
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CLOAD |
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50pF |
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50pF |
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DGND |
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50pF |
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50pF |
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DGND |
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DGND |
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DGND |
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a) High-Z to VOH and VOL to VOH |
b) High-Z to VOL and VOH to VOL |
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a) VOH to High-Z |
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b) VOL to High-Z |
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Figure 1. |
Load Circuits for Enable Time |
|
Figure 2. Load Circuits for Disable Time |
8 _______________________________________________________________________________________